DATASHEET ICL8069. Features. Pinouts. Ordering Information. Low Voltage Reference. FN3172 Rev.3.00 Page 1 of 6. Jan FN3172 Rev.3.00.

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1 DATASHEET Low Voltage Reference The is a 1.2V temperature-compensated voltage reference. It uses the band-gap principle to achieve excellent stability and low noise at reverse currents down to 50 A. Applications include analog-to-digital converters, digital-toanalog converters, threshold detectors, and voltage regulators. Its low power consumption makes it especially suitable for battery operated equipment. Ordering Information Features FN3172 Rev.3.00 Low Bias Current (Min) A Low Dynamic Impedance Low Reverse Voltage Low Cost Pinouts PART NUMBER MAXIMUM TEMPCO TEMP. RANGE ( o C) PACKAGE PKG. DWG. # (SOIC) TOP VIEW CCZR 0.005%/ o C 0 to 70 SIP Package (TO-92) Z V+ DCZR 0.01%/ o C 0 to 70 SIP Package (TO-92) Z3.05 CCBA 0.005%/ o C 0 to 70 8 Ld SOIC M V- 4 5 (SIP TO-92) TOP VIEW V+ V FN3172 Rev.3.00 Page 1 of 6

2 Functional Block Diagrams SIMPLE REFEREE (1.2V OR LESS) +5V 6.8k 4.7 F (NOTE 1) V+ 10k V- V OUT BUFFERED 10V REFEREE USING A SINGLE SUPPLY +15V V- V+ 15k LM k F 1k 8.2k +10V OUT DOUBLE REGULATED 100mV REFEREE FOR ICL7107 ONE-CHIP DPM CIRCUIT +5V 2.2k ICL7107 V+ V- 10k 1k +V REF HI COMMON REF LO FN3172 Rev.3.00 Page 2 of 6

3 Absolute Maximum Ratings Reverse Voltage See Note 3 Forward Current mA Reverse Current mA Operating Conditions Temperature Ranges C o C to 70 o C Thermal Information Thermal Resistance (Typical, Note 1) JA ( o C/W) JC ( o C/W) SOIC Package N/A SIP (TO-92) Package N/A Power Dissipation Limited by MAX Forward/Reverse Current Maximum Junction Temperature (SOIC Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = 25 o C Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Reverse Breakdown Voltage I R = 500 A V Reverse Breakdown Voltage Change 50 A l R 5mA mv Reverse Dynamic Impedance l R = 50 A l R = 50 A Forward Voltage Drop l F = 500 A V RMS Noise Voltage 10Hz F 10kHz, l R = 50 A V Long Term Stability l R = 4.75mA, T A = 25 o C ppm/khr Breakdown Voltage Temperature Coefficient I R = 500 A, T A = Operating C Temperature Range %/ o C D %/ o C Reverse Current Range 1.18V to 1.27V ma NOTES: 2. If circuit strays in excess of 200pF are anticipated, a 4.7 F shunt capacitor will ensure stability under all operating conditions. 3. In normal use, the reverse voltage cannot exceed the reference voltage. However when plugging units into a powered-up test fixture, an instantaneous voltage equal to the compliance of the test circuit will be seen. This should not exceed 20V. FN3172 Rev.3.00 Page 3 of 6

4 Typical Performance Curves mA OUTPUT VOLTAGE CHANGE (mv) o C o C, o C mA 10mA REVERSE CURRENT (A) REVERSE CURRENT (A) 1mA o C -55 o C 25 o C REVERSE VOLTAGE (V) FIGURE 1. VOLTAGE CHANGE AS A FUTION OF REVERSE CURRENT FIGURE 2. REVERSE VOLTAGE AS A FUTION OF CURRENT I R = 500 A OUTPUT VOLTAGE (V) TEMPERATURE ( o C) FIGURE 3. REVERSE VOLTAGE AS A FUTION OF TEMPERATURE FN3172 Rev.3.00 Page 4 of 6

5 Single-In-Line Plastic Packages (SIP) b W L e1 S1 e E-PIN Ø A D E (2X) NOTES: 1. Package body dimensions do not include any mold flash or protrusions. 2. Package outline dimensions do not include burrs. 3. Controlling dimension: IH. R Z3.05 (JEDEC STYLE TO-92 MODIFIED) 3 LEAD PLASTIC SINGLE-IN-LINE PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b E e e L R S W D o 6 o 4 o 6 o - Rev. 0 2/94 FN3172 Rev.3.00 Page 5 of 6

6 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.25(0.010) M C A M E -B- -A- -C- SEATING PLANE A B S H A1 µ 0.25(0.010) M B 0.10(0.004) L M h x 45 o NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC 1.27 BSC - H h L N o 8 o 0 o 8 o - Rev. 0 12/93 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3172 Rev.3.00 Page 6 of 6