CA124, CA224, CA324, LM324, LM2902

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1 OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT CA, CA, CA, LM, LM9 Data Sheet May File Number itle 9 b- ad, Hz, raal plis i- - -, usl, lis) tho y- ds er- Quad, MHz, Operational Amplifiers for Commercial, Industrial, and Military Applications The CA, CA, CA, LM, and LM9 consist of four independent, high-gain operational amplifiers on a single monolithic substrate. An on-chip capacitor in each of the amplifiers provides frequency compensation for unity gain. These devices are designed specially to operate from either single or dual supplies, and the differential voltage range is equal to the power-supply voltage. Low power drain and an input common-mode voltage range from V to V -.5V (single-supply operation) make these devices suitable for battery operation. Part Number Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PACKAGE PKG. NO. CAE -55 to 5 Ld PDIP E. CAM () CAM96 () -55 to 5 Ld SOIC M.5-55 to 5 Ld SOIC Tape and Reel M.5 CAE - to 85 Ld PDIP E. CAM () -to85 LdSOIC M.5 CAE to 7 Ld PDIP E. CAM () CAM96 () to7 LdSOIC M.5 to7 LdSOICTapeand Reel M.5 LMN to 7 Ld PDIP E. LM9N - to 85 Ld PDIP E. LM9M (9) LM9M96 (9) -to85 LdSOIC M.5 -to85 LdSOICTapeand Reel M.5 Features Operation from Single or Dual Supplies Unity-GainBandwidth...MHz(Typ) DCVoltageGain...dB (Typ) InputBiasCurrent...5nA (Typ) InputOffsetVoltage... mv(typ) Input Offset Current - CA, CA, LM, LM nA(Typ) - CA...nA(Typ) Replacement for Industry Types,, Applications Summing Amplifiers Multivibrators Oscillators Transducer Amplifiers DC Gain Blocks Pinout CA, CA, CA, LM9 (PDIP, SOIC) LM (PDIP) TOP VIEW OUTPUT NEG. INPUT POS. INPUT V POS. INPUT NEG. INPUT OUTPUT OUTPUT NEG. INPUT POS. INPUT V- POS. INPUT NEG. INPUT OUTPUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or -7-7 Intersil and Design is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.

2 CA, CA, CA, LM, LM9 Absolute Maximum Ratings SupplyVoltage...Vor±6V DifferentialInputVoltage...V InputVoltage...-.VtoV Input Current (V I <-.V,Note)...5mA Output Short Circuit Duration (V 5V, Note )......Continuous Operating Conditions Temperature Range CA o Cto5 o C CA,LM9...- o Cto85 o C CA,LM... o Cto7 o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIPPackage SOICPackage MaximumJunctionTemperature(Die)...75 o C Maximum Junction Temperature (Plastic Package) o C MaximumStorageTemperatureRange o Cto5 o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. This input current will only exist when the voltage at any of the input leads is driven negative. This current is due to the collector base junction of the input p-n-p transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral n-p-n parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the amplifiers to go to the V voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This transistor action is not destructive and normal output states will reestablish when the input voltage, which was negative, again returns to a value greater than -.V.. The maximum output current is approximately ma independent of the magnitude of V. Continuous short circuits at V > 5V can cause excessive power dissipation and eventual destruction. Short circuits from the output to V can cause overheating and eventual destruction of the device.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Values Apply for Each Operational Amplifier. Supply Voltage V = 5V, V- = V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP. ( o C) CA CA, CA, LM LM9 MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage (Note 6) Average Input Offset Voltage Drift Differential Input Voltage (Note 5) Input Common Mode Voltage Range (Note 5) Common Mode Rejection Ratio Power Supply Rejection Ratio Input Bias Current (Note ) Input Offset Current Average Input Offset Current Drift mv Full mv R S =Ω Full µv/ o C Full - - V - - V - - V V V = V 5 - V V V V = V Full - V - - V V V = 6V Full V - V DC db DC db I I ori I na I I ori I - Full na I I -I I na I I -I I - Full na Full pa/ o C Large Signal Voltage Gain R L kω,v=5v (For Large V O Swing) R L kω, V=5V (For Large V O Swing) db Full db

3 CA, CA, CA, LM, LM9 Electrical Specifications Values Apply for Each Operational Amplifier. Supply Voltage V = 5V, V- = V, Unless Otherwise Specified (Continued) PARAMETER Output Voltage Swing Output Current High Level Low Level Source TEST CONDITIONS R L =kω 5 - V V V R L = kω, V = V Full V R L = kω, V = 6V Full V R L =kω, V = V Full V R L =kω Full mv V I =V,V I -=V, V = 5V TEMP. ( o C) CA CA, CA, LM LM9 MIN TYP MAX MIN TYP MAX MIN TYP MAX ma V I =V,V I -=, Full ma V = 5V Sink V I =V,V I -=V, ma V = 5V V I =V,V I -=V, µa V O =mv V I -=V,V I =, V = 5V Full ma Crosstalk f = to khz db (Input Referred) Total Supply R L = Full ma Current R L =, V = 6V Full ma NOTES:. Due to the PNP input stage the direction of the input current is out of the IC. No loading change exists on the input lines because the current is essentially constant, independent of the state of the output. 5. The input signal voltage and the input common mode voltage should not be allowed to go negative by more than.v. The positive limit of the common mode voltage range is V -.5V, but either or both inputs can go to V without damage. 6. V O =.V,R S =Ω with V from 5V to V, and over the full input common mode voltage range (V to V -.5V). UNITS Schematic Diagram (One of Four Operational Amplifiers) V TO,, Q 6µA Q µa C COMP µa Q INPUTS Q Q Q Q Q 7 Q 6 R SC - Q 8 Q 9 Q V O 9-8 Q 5µA V- TO,,

4 Typical Performance Curves CA, CA, CA, LM, LM9 OPEN-LOOP VOLTAGE GAIN (db) 8 6 T A =- T A 85 o C.µF V I V/ V =TO5V V - V O V=6V OUTPUT VOLTAGE (mv) T A =5 o C V = V V I OUTPUT - 5pF V O INPUT K K K M M FREQUENCY (Hz) FIGURE. OPEN LOOP FREQUENCY RESPONSE TIME (µs) FIGURE. VOLTAGE FOLLOWER PULSE RESPONSE (SMALL SIGNAL) INPUT VOLTAGE (V) T A =5 o C V = 5V R L =kω TIME (µs) OUTPUT VOLTAGE (V) FIGURE. VOLTAGE FOLLOWER PULSE RESPONSE (LARGE SIGNAL) 6 V ICR =V ma V I D INPUT CURRENT (na) 5 V=V 5V 5V SUPPLY CURRENT (ma) T A = o C TO 5 o C TEMPERATURE ( o C) FIGURE. INPUT CURRENT vs AMBIENT TEMPERATURE -55 o C POSITIVE SUPPLY VOLTAGE (V) FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE

5 CA, CA, CA, LM, LM9 Typical Performance Curves (Continued) OUTPUT VOLTAGE SWING (V) 5 5 T A =5 o C V I kω 7V kω 5V - V O kω OUTPUT SOURCE CURRENT (ma) V = 5V K K K M FREQUENCY (Hz) FIGURE 6. LARGE SIGNAL FREQUENCY RESPONSE TEMPERATURE ( o C) FIGURE 7. OUTPUT CURRENT vs AMBIENT TEMPERATURE T A =5 o C T A =5 o C INPUT CURRENT (na) OPEN LOOP VOLTAGE GAIN (db) R L =kω R L =kω POSITIVE SUPPLY VOLTAGE (V) FIGURE 8. INPUT CURRENT vs SUPPLY VOLTAGE POSITIVE SUPPLY VOLTAGE (V) FIGURE 9. VOLTAGE GAIN vs SUPPLY VOLTAGE 5

6 Dual-In-Line Plastic Packages (PDIP) CA, CA, CA, LM, LM9 INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.5M-98.. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-. 5. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.5mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.5mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E8., E6., E8., E8., E.6 will have a B dimension of. -.5 inch (.76 -.mm). -B- A. (.5) M C A A L BS A e C E C L e A C e B E. (JEDEC MS--AA ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e. BSC.5 BSC - e A. BSC 7.6 BSC 6 e B L N 9 Rev. /9 6

7 Small Outline Plastic Packages (SOIC) CA, CA, CA, LM, LM9 N INDEX AREA D e B.5(.) M C A M E -B- -A- -C- SEATING PLANE A B S H A.5(.) M B.(.) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 95.. Dimensioning and tolerancing per ANSI Y.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.6mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. µ α L M hx5 o C M.5 (JEDEC MS--AB ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e.5 BSC.7 BSC - H h L N 7 α o 8 o o 8 o - Rev. /9 All Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at website Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site Sales Office Headquarters NORTH AMERICA Intersil Corporation Palm Bay Rd. Palm Bay, FL 95 TEL: () 7-7 FAX: () EUROPE Intersil SA Mercure Center,RuedelaFusee Brussels, Belgium TEL: ().7. FAX: ().7..5 ASIA Intersil Ltd. 8F-, 96, Sec., Chien-kuo North, Taipei, Taiwan Republic of China TEL: FAX:

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