HA7210. Features. 10kHz to 10MHz, Low Power Crystal Oscillator. Applications. Ordering Information. Typical Application Circuit.

Transcription

1 Data Sheet February 999 File Number 9. khz to MHz, Low Power Crystal Oscillator The HA is a very low power crystal-controlled oscillators that can be externally programmed to operate between khz and MHz. For normal operation it requires only the addition of a crystal. The part exhibits very high stability over a wide operating voltage and temperature range. The HA also features a disable mode that switches the output to a high impedance state. This feature is useful for minimizing power dissipation during standby and when multiple oscillator circuits are employed. Ordering Information PART NUMBER (BRAND) Pinout TEMP. RANGE ( o C) PACKAGE HAIP - to Ld PDIP E. HA (PDIP, SOIC) TOP VIEW PKG. NO. HAIB - to Ld SOIC M. (HI) HAY - to DIE Features Single Supply Operation at khz V to V Operating Frequency Range khz to MHz Supply Current at khz µa Supply Current at MHz µa Drives CMOS Loads Only Requires an External Crystal for Operation Applications Battery Powered Circuits Remote Metering Embedded Microprocessors Palm Top/Notebook PC Related Literature - AN9, Improving HA Start-Up Time Typical Application Circuit.µF OSC IN OSC OUT ENABLE FREQ FREQ.kHz CRYSTAL HA (NOTE ).khz CLOCK V SS OUTPUT.kHz MICROPOWER CLOCK OSCILLATOR NOTE:. Internal pull-up resistors provided on EN, FREQ, and FREQ inputs. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. or --9 Copyright Intersil Corporation 999

2 Simplified Block Diagram (NOTE ) ENABLE EXTERNAL CRYSTAL OSC IN R F OSC OUT pf pf -.V -.V -.V S A S S V RN + - S B S C V RN LEVEL SHIFTER OUTPUT BUFFER -.V I BIAS OF DECODE S BUFFER AMP V SS FREQ FREQ (NOTE ) (NOTE ) R F IN P P N V RN OSCILLATOR OUT FREQUENCY SELECTION TRUTH TABLE ENABLE FREQ FREQ SWITCH OUTPUT RANGE S A, S B, S C khz - khz S khz - MHz S MHz - MHz S MHz - MHz+ X X X High Impedance NOTE:. Logic input pull-up resistors are constant current source of.µa.

3 Absolute Maximum Ratings Supply Voltage V Voltage (Any Pin) V SS -.V to +.V ESD Rating Human Body Model (Per MIL-STD- Method.)...V Operating Conditions Temperature Range (Note ) o C to o C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. This product is production tested at o C only.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SS = GND, T A = o C, Unless Otherwise Specified = V = V PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Supply Range f OSC = khz V I DD Supply Current f OSC = khz, EN = (Standby) µa f OSC = khz, C L = pf (Note ), EN =, Freq =, Freq = f OSC = khz, C L = pf, EN =, Freq =, Freq = f OSC = MHz, C L = pf (Note ), EN =, Freq =, Freq = f OSC = MHz, C L = pf, EN =, Freq =, Freq = µa µa µa - - µa V OH Output High Voltage I OUT = -ma V V OL Output Low Voltage I OUT = ma V I OH Output High Current V OUT V ma I OL Output Low Current V OUT.V ma Three-State Leakage Current V OUT = V, V, T A = o C, - o C na V OUT = V, V, T A = o C na I IN Enable, Freq, Freq Input Current V IN = V SS to µa V IH Input High Voltage Enable, Freq, Freq V V IL Input Low Voltage Enable, Freq, Freq V Enable Time C L = pf, R L = kω ns Disable Time C L = pf, R L = kω ns t r Output Rise Time % - 9%, f OSC = khz, C L = pf ns t f Output Fall Time % - 9%, f OSC = khz, C L = pf ns Duty Cycle, Packaged Part Only (Note ) C L = pf, f OSC = MHz % Duty Cycle, (See Typical Curves) C L = pf, f OSC = khz % Frequency Stability vs Supply Voltage f OSC = khz, = V, C L = pf ppm/v Frequency Stability vs Temperature f OSC = khz, = V, C L = pf ppm/ o C Frequency Stability vs Load f OSC = khz, = V, C L = pf ppm/pf NOTES:. Calculated using the equation I DD = I DD (No Load) + ( ) (f OSC )(C L ). Duty cycle will vary with supply voltage, oscillation frequency, and parasitic capacitance on the crystal pins.

4 Test Circuit V P-P Ω.µF pf In production the HA is tested with a khz and a MHz crystal. However for characterization purposes data was taken using a sinewave generator as the frequency determining element, as shown in Figure. The V P-P input is a smaller amplitude than what a typical crystal would generate so the transitions are slower. In general the Generator data will show a worst case number for I DD, duty cycle, and rise/fall time. The Generator test method is useful for testing a variety of frequencies quickly and provides curves which can be used for understanding performance trends. Data for the HA using crystals has also been taken. This data has been overlaid onto the generator data to provide a reference for comparison. Application Information Theory Of Operation +V FIGURE. HA The HA is a Pierce Oscillator optimized for low power consumption, requiring no external components except for a bypass capacitor and a Parallel Mode Crystal. The Simplified Block Diagram shows the Crystal attached to pins and, the Oscillator input and output. The crystal drive circuitry is detailed showing the simple CMOS inverter stage and the P-channel device being used as biasing resistor R F. The inverter will operate mostly in its linear region increasing the amplitude of the oscillation until limited by its transconductance and voltage rails, and V RN. The inverter is self biasing using R F to center the oscillating waveform at the input threshold. Do not interfere with this bias function with external loads or excessive leakage on pin. Nominal value for R F is MΩ in the lowest frequency range to MΩ in the highest frequency range. The HA optimizes its power for frequency ranges selected by digital inputs Freq and Freq as shown in the Block Diagram. Internal pull up resistors (constant current.µa) on Enable, Freq and Freq allow the user simply to leave one or all digital inputs not connected for a corresponding state. All digital inputs may be left open for khz to khz operation. A current source develops selectable reference voltages through series resistors. The selected voltage, V RN, is buffered and used as the negative supply rail for the oscillator section of the circuit. The use of a current source in the reference string allows for wide supply variation with minimal effect on performance. The reduced operating C L ENABLE FREQ FREQ pf V OUT voltage of the oscillator section reduces power consumption and limits transconductance and bandwidth to the frequency range selected. For frequencies at the edge of a range, the higher range may provide better performance. The OSC OUT waveform on pin is squared up through a series of inverters to the output drive stage. The Enable function is implemented with a NAND gate in the inverter string, gating the signal to the level shifter and output stage. Also during Disable the output is set to a high impedance state useful for minimizing power during standby and when multiple oscillators are OR ed to a single node. Design Considerations The low power CMOS transistors are designed to consume power mostly during transitions. Keeping these transitions short requires a good decoupling capacitor as close as possible to the supply pins and. A ceramic.µf is recommended. Additional supply decoupling on the circuit board with µftoµfwill further reduce overshoot, ringing and power consumption. The HA, when compared to a crystal and inverter alone, will speed clock transition times, reducing power consumption of all CMOS circuitry run from that clock. Power consumption may be further reduced by minimizing the capacitance on moving nodes. The majority of the power will be used in the output stage driving the load. Minimizing the load and parasitic capacitance on the output, pin, will play the major role in minimizing supply current. A secondary source of wasted supply current is parasitic or crystal load capacitance on pins and. The HA is designed to work with most available crystals in its frequency range with no external components required. Two pf capacitors are internally switched onto crystal pins and on the HA to compensate the oscillator in the khz to khz frequency range. The supply current of the HA may be approximately calculated from the equation: I DD = I DD (Disabled) + f OSC C L where: I DD = Total supply current = Total voltage from (pin ) to V SS (pin ) f OSC = Frequency of Oscillation C L = Output (pin ) load capacitance EXAMPLE #: = V, f OSC = khz, C L = pf I DD (Disabled) =.µa (Figure ) I DD =.µa + (V)(kHz)(pF) = 9.µA Measured I DD =.µa EXAMPLE #: = V, f OSC = MHz, C L = pf I DD (Disabled) = µa (Figure 9) I DD = µa + (V)(MHz)(pF) = µa Measured I DD = 9µA

5 Crystal Selection For general purpose applications, a Parallel Mode Crystal is a good choice for use with the HA. However for applications where a precision frequency is required, the designer needs to consider other factors. Crystals are available in two types or modes of oscillation, Series and Parallel. Series Mode crystals are manufactured to operate at a specified frequency with zero load capacitance and appear as a near resistive impedance when oscillating. Parallel Mode crystals are manufactured to operate with a specific capacitive load in series, causing the crystal to operate at a more inductive impedance to cancel the load capacitor. Loading a crystal with a different capacitance will pull the frequency off its value. The HA has operating frequency ranges. The higher three ranges do not add any loading capacitance to the oscillator circuit. The lowest range, khz to khz, automatically switches in two pf capacitors onto OSC IN and OSC OUT to eliminate potential start-up problems. These capacitors create an effective crystal loading capacitor equal to the series combination of these two capacitors. For the HA in the lowest range, the effective loading capacitance is.pf. Therefore the choice for a crystal, in this range, should be a Parallel Mode crystal that requires a.pf load. In the higher frequency ranges, the capacitance on OSC IN and OSC OUT will be determined by package and layout parasitics, typically to pf. Ideally the choice for crystal should be a Parallel Mode set for.pf load. A crystal manufactured for a different load will be pulled from its nominal frequency (see Crystal Pullability). frequency. In Method two these two goals can be at odds with each other; either the oscillator is trimmed to frequency by de-tuning the load circuit, or stability is increased at the expense of absolute frequency accuracy. Method one allows these two conditions to be met independently. The two fixed capacitors, C and C, provide the optimum load to the oscillator and crystal. C adjusts the frequency at which the circuit oscillates without appreciably changing the load (and thus the stability) of the system. Once a value for C has been determined for the particular type of crystal being used, it could be replaced with a fixed capacitor. For the most precise control over oscillator frequency, C should remain adjustable. This three capacitor tuning method will be more accurate and stable than method two and is recommended for khz tuning fork crystals; without it they may leap into an overtone mode when power is initially applied. Method two has been used for many years and may be preferred in applications where cost or space is critical. Note that in both cases the crystal loading capacitors are connected between the oscillator and ; do not use V SS as an AC ground. The Simplified Block Diagram shows that the oscillating inverter does not directly connect to V SS but is referenced to and V RN. Therefore is the best AC ground available. C C XTAL OSC IN OSC OUT +V C C +V HA + - V REG XTAL C OSC IN OSC OUT HA FIGURE. + - V REG FIGURE. Typical values of the capacitors in Figure are shown below. Some trial and error may be required before the best combination is determined. The values listed are total capacitance including parasitic or other sources. Remember that in the khz to khz frequency range setting the HA switches in two internal pf capacitors. Frequency Fine Tuning Two Methods will be discussed for fine adjustment of the crystal frequency. The first and preferred method (Figure ), provides better frequency accuracy and oscillator stability than method two (Figure ). Method one also eliminates start-up problems sometimes encountered with khz tuning fork crystals. For best oscillator performance, two conditions must be met: the capacitive load must be matched to both the inverter and crystal to provide ideal conditions for oscillation, and the frequency of the oscillator must be adjustable to the desired CRYSTAL FREQUENCY LOAD CAPS C, C TRIMMER CAP C khz pf pf to pf MHz pf pf to pf MHz pf pf to pf MHz pf pf to pf

6 Crystal Pullability Figure shows the basic equivalent circuit for a crystal and its loading circuit. C M LM R M C C OSC IN C Where: C M = Motional Capacitance L M = Motional Inductance R M = Motional Resistance C = Shunt Capacitance FIGURE. C CL = = Equivalent Crystal Load C C If loading capacitance is connected to a Series Mode Crystal, the new Parallel Mode frequency of resonance may be calculated with the following equation: C M f P = f S + C ( + C CL ) Where: f P = Parallel Mode Resonant Frequency f S = Series Mode Resonant Frequency OSC OUT In a similar way, the Series Mode resonant frequency may be calculated from a Parallel Mode crystal and then you may calculate how much the frequency will pull with a new load. Layout Considerations Due to the extremely low current (and therefore high impedance) the circuit board layout of the HA must be given special attention. Stray capacitance should be minimized. Keep the oscillator traces on a single layer of the PCB. Avoid putting a ground plane above or below this layer. The traces between the crystal, the capacitors, and the OSC pins should be as short as possible. Completely surround the oscillator components with a thick trace of to minimize coupling with any digital signals. The final assembly must be free from contaminants such as solder flux, moisture, or any other potential source of leakage. A good solder mask will help keep the traces free of moisture and contamination over time. Further Reading Al Little HA Low Power Oscillator: Micropower Clock Oscillator and Op Amps Provide System Shutdown for Battery Circuits. Harris Semiconductor Application Note AN9. Robert Rood Improving Start-Up Time at khz for the HA Low Power Crystal Oscillator. Harris Semiconductor Application Note AN9. S. S. Eaton Timekeeping Advances Through COS/MOS Technology. Harris Semiconductor Application Note ICAN-. E. A. Vittoz, et. al. High-Performance Crystal Oscillator Circuits: Theory and Application. IEEE Journal of Solid- State Circuits, Vol., No., June 9, pp-. M. A. Unkrich, et. al. Conditions for Start-Up in Crystal Oscillators. IEEE Journal of Solid-State Circuits, Vol., No., Feb. 9, pp-9. Marvin E. Frerking Crystal Oscillator Design and Temperature Compensation. New York: Van Nostrand- Reinhold, 9. Pierce Oscillators Discussed pp-.

7 Typical Performance Curves C L = pf, f OSC = MHz, = V, V SS = GND C L = pf, f OSC = MHz, = V, V SS = GND.V/DIV..ns/DIV..V/DIV..ns/DIV. FIGURE. OUTPUT WAVEFORM (C L = pf) FIGURE. OUTPUT WAVEFORM (C L = pf) 9 9 f IN = MHz, EN =, F =, F =, C L = pf, = V GENERATOR (V P-P ) (NOTE) X TAL AT o C 9 EN =, F =, F =, f IN = khz, C L = pf, = V GENERATOR (V P-P ) (NOTE) X TAL AT o C - - FIGURE. SUPPLY CURRENT vs TEMPERATURE - - FIGURE. SUPPLY CURRENT vs TEMPERATURE f IN = MHz, EN =, F =, F =, = V. EN =, F =, F =, f IN = khz, = V GENERATOR (V P-P ) (NOTE) X TAL AT o C... GENERATOR (V P-P ) (NOTE) X TAL AT o C - - FIGURE 9. DISABLE SUPPLY CURRENT vs TEMPERATURE NOTE: Refer to Test Circuit (Figure ). - - FIGURE. DISABLE SUPPLY CURRENT vs TEMPERATURE

8 Typical Performance Curves (Continued) EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) = +V = +V EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) = +V = +V = +V 9 FIGURE. SUPPLY CURRENT vs FREQUENCY FIGURE. SUPPLY CURRENT vs FREQUENCY EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) = +V = +V = +V = +V = +V = +V 9 FIGURE. SUPPLY CURRENT vs FREQUENCY 9 FIGURE. SUPPLY CURRENT vs FREQUENCY EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) 9 FIGURE. DISABLED SUPPLY CURRENT vs FREQUENCY NOTE: Refer to Test Circuit (Figure ). = +V = +V = +V EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) = +V 9 = +V = +V FIGURE. DISABLE SUPPLY CURRENT vs FREQUENCY

9 Typical Performance Curves (Continued) EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) = +V = +V = +V 9 EN =, F =, F =, C L = pf, GENERATOR (V P-P ) (NOTE) V DD = +V 9 = +V = +V 9 FIGURE. DISABLE SUPPLY CURRENT vs FREQUENCY FIGURE. DISABLE SUPPLY CURRENT vs FREQUENCY EN =, F =, F =, = +V, GENERATOR (V P-P ) (NOTE) C L = pf C L = pf EN =, F =, F =, = +V, GENERATOR (V P-P ) (NOTE) C L = pf C L = pf 9 FIGURE 9. SUPPLY CURRENT vs FREQUENCY FIGURE. SUPPLY CURRENT vs FREQUENCY EN =, F =, F =, = +V, GENERATOR (V P-P ) (NOTE) 9 FIGURE. SUPPLY CURRENT vs FREQUENCY NOTE: Refer to Test Circuit (Figure ). C L = pf C L = pf EN =, F =, F =, = +V, GENERATOR (V P-P ) (NOTE) C L = pf C L = pf 9 FIGURE. SUPPLY CURRENT vs FREQUENCY 9

10 Typical Performance Curves (Continued) DUTY CYCLE (%) f IN = MHz, F =, F =, C L = pf, = V GENERATOR (V P-P ) (NOTE) X TAL AT o C DUTY CYCLE (%) f IN = khz, F =, F =, C L = pf, = V GENERATOR (V P-P ) (NOTE) X TAL AT o C - - FIGURE. DUTY CYCLE vs TEMPERATURE - - FIGURE. DUTY CYCLE vs TEMPERATURE F = F =, = V, C L = pf, C = C = DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY F =, F =, = V, C L = pf, C = C = DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY DUTY CYCLE (%) DUTY CYCLE (%) F =, F = RECOMMENDED FOR MHz TO MHz RANGE F =, F = RECOMMENDED FOR MHz TO MHz RANGE 9 FIGURE. DUTY CYCLE vs FREQUENCY FIGURE. DUTY CYCLE vs FREQUENCY DUTY CYCLE (%) F =, F = RECOMMENDED FOR khz TO MHz RANGE FIGURE. DUTY CYCLE vs FREQUENCY NOTE: Refer to Test Circuit (Figure ). F =, F =, = V, C L = pf, C = C = DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY DUTY CYCLE (%) F = F =, = V, C L = pf, C = C = DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY F =, F = RECOMMENDED FOR khz TO khz RANGE FIGURE. DUTY CYCLE vs FREQUENCY

11 Typical Performance Curves (Continued) FREQUENCY CHANGE (PPM) SUPPLY VOLTAGE (V) FIGURE 9. FREQUENCY CHANGE vs khz MHz MHz MHz DEVIATION FROM FREQUENCY AT.V EDGE JITTER (% OF PERIOD) = V, C L = pf, GENERATOR (V P-P ) (NOTE) f IN = MHz, F =, F = f IN = khz, F =, F = - - FIGURE. EDGE JITTER vs TEMPERATURE RISE/FALL TIME (ns) 9 f IN = MHz, F =, F =, C L = pf, = V t r GENERATOR (V P-P ) (NOTE) t f GENERATOR (V P-P ) (NOTE) - - t f X TAL AT o C t r X TAL AT o C FIGURE. RISE/FALL TIME vs TEMPERATURE RISE/FALL TIME (ns) 9 f IN = khz, F =, F =, C L = pf, = V t r GENERATOR (V P-P ) (NOTE) t f GENERATOR (V P-P ) (NOTE) - - t f X TAL AT o C t r X TAL AT o C FIGURE. RISE/FALL TIME vs TEMPERATURE RISE/FALL TIME (ns) = V, GENERATOR (V P-P ) (NOTE) t f (f IN = MHz) t f (f IN = khz) 9 C L (pf) t r (f IN = MHz) t r (f IN = khz) RISE/FALL TIME (ns) 9 C L = pf, GENERATOR (V P-P ) (NOTE) t f (f IN = MHz) t f (f IN = khz) t r (f IN = MHz) t r (f IN = khz) 9 (+V) FIGURE. RISE/FALL TIME vs C L NOTE: Refer to Test Circuit (Figure ). FIGURE. RISE/FALL TIME vs

12 Typical Performance Curves (Continued) TRANSCONDUCTANCE (µa/v).µa/v pf µf o Ω HA Ω = V, V SS = GND F =, F = PHASE (DEGREES) pf µf Ω HA K K M M K K M M FREQUENCY (Hz) FREQUENCY (Hz) TRANSCONDUCTANCE (µa/v) F =, F = = V, V SS = GND.µA/V o Ω PHASE (DEGREES) FIGURE. TRANSCONDUCTANCE vs FREQUENCY FIGURE. TRANSCONDUCTANCE vs FREQUENCY TRANSCONDUCTANCE (µa/v) = V, V SS = GND F =, F =.µa/v. o pf µf Ω HA Ω K K M M FREQUENCY (Hz) FIGURE. TRANSCONDUCTANCE vs FREQUENCY PHASE (DEGREES) TRANSCONDUCTANCE (µa/v) = V, V SS = GND F =, F =.µa/v o pf µf Ω Ω HA K K M FREQUENCY (Hz) FIGURE. TRANSCONDUCTANCE vs FREQUENCY PHASE (DEGREES) F = F =, = V, C L = pf, T A = o C, f OSC =.khz DUTY CYCLE (%) EPSON PART # C-R.K-A NDK PART # MX- R S (kω) OSC IN XTAL R S OSC OUT HA NOTE: Figure 9 (Duty Cycle vs R S at khz) should only be used for khz crystals. R S may be used at other frequencies to adjust Duty Cycle but experimentation will be required to find an appropriate value. The R S value will be proportional to the effective series resistance of the crystal being used. FIGURE 9. DUTY CYCLE vs R S at khz NOTE: Refer to Test Circuit (Figure ).

13 Die Characteristics DIE DIMENSIONS: mils x mils x mils METALLIZATION: Type: SiAl Thickness: kå ±kå SUBSTRATE POTENTIAL: V SS PASSIVATION: Type: Nitride (Si N ) Over Silox (SiO, % Phos) Silox Thickness: kå ±kå Nitride Thickness: kå ±kå Metallization Mask Layout HA () () FREQ CRYSTAL () CRYSTAL () () FREQ V SS () OUTPUT () () ENABLE

14 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E -B- A. (.) M C A A L BS NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-9.. Symbols are defined in the MO Series Symbol List in Section. of Publication No. 9.. Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E., E., E., E., E. will have a B dimension of. -. inch (. -.mm). A e C E C L e A C e B E. (JEDEC MS--BA ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B...., C D D E.... E.... e. BSC. BSC - e A. BSC. BSC e B L...9. N 9 Rev. /9

15 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B.(.) M C A M E -B- -A- -C- SEATING PLANE A B S H.(.) M B A α.(.) L M h x o NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M-9.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (. inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured.mm (. inch) or greater above the seating plane, shall not exceed a maximum value of.mm (. inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M. (JEDEC MS--AA ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E.9... e. BSC. BSC - H h L.... N α o o o o - Rev. /9 All Intersil semiconductor products are manufactured, assembled and tested under ISO9 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box, Mail Stop - Melbourne, FL 9 TEL: () - FAX: () - For information regarding Intersil Corporation and its products, see web site EUROPE Intersil SA Mercure Center, Rue de la Fusee Brussels, Belgium TEL: ().. FAX: ()... ASIA Intersil (Taiwan) Ltd. F-, No. Fu Hsing North Road Taipei, Taiwan Republic of China TEL: () 9 FAX: () 9