Features PKG. DWG. # M16.3 M16.3 M16.3 M16.15 M16.15 M16.15 E16.3. NUMBER OF RECEIVERS ACTIVE IN SHUTDOWN HIN232A +5V Capacitors No/No 0

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1 DATASHEET HINA High Speed V Powered RS Transmitters/Receivers FN Rev.00 The HINA highspeed RS transmitter/receiver interface circuit meets all ElA highspeed RSE and V. specifications, and is particularly suited for those applications where V is not available. They require a single V power supply and feature onboard charge pump voltage converters which generate V and V supplies from the V supply. The drivers feature true TTL/CMOS input compatibility, slew ratelimited output, and 00 poweroff source impedance. The receivers can handle up to 0V input, and have a k to k input impedance. The receivers also feature hysteresis to greatly improve noise rejection. Ordering Information TEMP. RANGE ( o C) PACKAGE PART PART NO. MARKING HINACB ACB 0 to 0 Ld SOIC M. HINACBT ACB 0 to 0 Ld SOIC Tape and Reel HINACBZ (See Note) HINACBZT (See Note) ACBZ 0 to 0 Ld SOIC (Pbfree) ACBZ 0 to 0 Ld SOIC Tape and Reel (Pbfree) PKG. DWG. # M. M. M. HINACBN ACBN 0 to 0 Ld SOIC (N) M. HINACBNT ACBN 0 to 0 Ld SOIC (N) Tape and Reel M. HINACBNZ (See Note) HINACBNZT (See Note) ACBNZ 0 to 0 Ld SOIC (N) (Pbfree) ACBNZ 0 to 0 Ld SOIC (N) Tape and Reel (Pbfree) M. M. HINACP HINACP 0 to 0 Ld PDIP E. HINACPZ (See Note) ACPZ 0 to 0 Ld PDIP* (Pbfree) E. *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and 0% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD00. Selection Table Features Meets All RSE and V. Specifications Requires Only or Greater External Capacitors High Data Rate kbit/s Requires Only Single V Power Supply Onboard Voltage Doubler/Inverter Low Power Consumption (Typ) ma Multiple Drivers V Output Swing for V lnput 00 PowerOff Source Impedance Output Current Limiting TTL/CMOS Compatible Multiple Receivers 0V Input Voltage Range k to k Input Impedance 0.V Hysteresis to Improve Noise Rejection PbFree Plus Anneal Available (RoHS Compliant) Applications Any System Requiring HighSpeed RS Communication Ports Computer Portable, Mainframe, Laptop Peripheral Printers and Terminals Instrumentation, UPS Modems PART NUMBER POWER SUPPLY VOLTAGE NUMBER OF RS DRIVERS NUMBER OF RS RECEIVERS NUMBER OF EXTERNAL CAPACITORS LOW POWER SHUTDOWN/TTL THREE STATE NUMBER OF RECEIVERS ACTIVE IN SHUTDOWN HINA V Capacitors No/No 0 FN Rev.00 Page of

2 Pinout HINA (PDIP, SOIC) TOP VIEW V C V GND T OUT R IN R OUT T IN T IN R OUT C C C C C C C V T OUT R IN V TO V VOLTAGE INVERTER V TO V VOLTAGE INVERTER V V T IN V 00k T T OUT T IN V 00k T T OUT R OUT R k R IN R OUT R k R IN GND Pin Descriptions PIN FUNCTION Power Supply Input V %. V Internally generated positive supply (V nominal). V Internally generated negative supply (V nominal). GND Ground Lead. Connect to 0V. C External capacitor ( terminal) is connected to this lead. C External capacitor ( terminal) is connected to this lead. C External capacitor ( terminal) is connected to this lead. C External capacitor ( terminal) is connected to this lead. T IN T OUT R IN R OUT Transmitter Inputs. These leads accept TTL/CMOS levels. An internal 00k pullup resistor to is connected to each lead. Transmitter Outputs. These are RS levels (nominally V). Receiver Inputs. These inputs accept RS input levels. An internal k pulldown resistor to GND is connected to each input. Receiver Outputs. These are TTL/CMOS levels. FN Rev.00 Page of

3 Absolute Maximum Ratings to Ground (GND 0.V) < < V V to Ground ( 0.V) <V < V V to Ground V < V < (GND 0.V) Input Voltages T IN V < V IN < (V 0.V) R IN 0V Output Voltages T OUT (V 0.V) < V TXOUT < (V 0.V) R OUT (GND 0.V) < V RXOUT < (V 0.V) Short Circuit Duration T OUT Continuous R OUT Continuous ESD Classification See Specification Table Thermal Information Thermal Resistance (Typical, Note ) JA ( o C/W) Ld SOIC (N) Package Ld SOIC (W) Package Ld PDIP Package* Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to o C Maximum Lead Temperature (Soldering s) o C (SOIC Lead Tips Only) *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range HINACX o C to 0 o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB for details. Electrical Specifications Test Conditions: = V %, CC = ; T A = Operating Temperature Range PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SUPPLY CURRENTS Power Supply Current, I CC No Load, T A = o C ma LOGIC AND TRANSMITTER INPUTS, RECEIVER OUTPUTS Input Logic Low, V ll T IN 0. V Input Logic High, V lh T IN.0 V Transmitter Input Pullup Current, I P T IN = 0V 00 A TTL/CMOS Receiver Output Voltage Low, V OL I OUT =.ma V TTL/CMOS Receiver Output Voltage High, V OH I OUT = ma.. V RECEIVER INPUTS RS Input Voltage Range, V IN 0 0 V Receiver Input Impedance, R IN V IN = V, T A = o C k Receiver Input Low Threshold, V IN (HL) = V, T A = o C. V Receiver Input High Threshold, V IN (LH) = V, T A = o C.. V Receiver Input Hysteresis, V HYST = V V TIMING CHARACTERISTICS Transmitter, Receiver Propagation Delay, t PD 0. s Transition Region Slew Rate, SR T R L = k, C L = 00pF, Measured from V to 0 V/ s V or V to V, (Note ) Transmitter Switching TRANSMITTER OUTPUTS Output Voltage Swing, T OUT Transmitter Outputs, k to Ground V Output Resistance, T OUT = V = V = 0V, V OUT = V 00 RS Output Short Circuit Current, I SC T OUT Shorted to GND ma ESD PERFORMANCE RS Pins Human Body Model kv (T OUT, R IN ) IEC00 Contact Discharge kv IEC00 Air Gap (Note ) kv All Other Pins Human Body Model kv NOTES:. Guaranteed by design.. Meets level. FN Rev.00 Page of

4 Test Circuits (HINA) C C k C C T OUT GND T OUT R IN R OUT T IN T IN.V TO.V INPUT k T OUTPUT RS 0V INPUT TTL/CMOS OUTPUT TTL/CMOS INPUT TTL/CMOS INPUT C V C C C V C V C C C V T OUT R IN GND T OUT R IN R OUT T IN T IN R OUT T OUTPUT RS 0V INPUT R IN R OUT TTL/CMOS OUTPUT R OUT = V IN /I V IN = V T OUT T OUT A FIGURE. GENERAL TEST CIRCUIT FIGURE. POWEROFF SOURCE RESISTANCE CONFIGURATION VOLTAGE DOUBLER VOLTAGE INVERTER S C S V = S C S GND GND C C C C GND S C S S C S V = (V) RC OSCILLATOR FIGURE. CHARGE PUMP Detailed Description The HINA is a highspeed RS transmitter/receiver that is powered by a single V power supply, features low power consumption, and meets all ElA RSC and V. specifications. The circuit is divided into three sections: the charge pump, transmitter, and receiver. Charge Pump An equivalent circuit of the charge pump is illustrated in Figure. The charge pump contains two sections: The voltage doubler and the voltage inverter. Each section is driven by a two phase, internally generated clock to generate V and V. The nominal clock frequency is khz. During phase one of the clock, capacitor C is charged to. During phase two, the voltage on C is added to, producing a signal across C equal to twice. During phase two, C is also charged to, and then during phase one, it is inverted with respect to ground to produce a signal across C equal to. The charge pump accepts input voltages up to.v. The output impedance of the voltage doubler section (V) is approximately 00, and the output impedance of the voltage inverter section (V) is approximately 0. A typical application uses capacitors for CC, however, the value is not critical. Increasing the values of C and C will lower the output impedance of the voltage doubler and inverter, increasing the values of the reservoir capacitors, C and C, lowers the ripple on the V and V supplies. Transmitters The transmitters are TTL/CMOS compatible inverters which translate the inputs to RS outputs. The input logic threshold is about % of, or.v for = V. A logic at the input results in a voltage of between V and V at the output, and a logic 0 results in a voltage between V and (V 0.V). Each transmitter input has an internal 00k pullup resistor so any unused input can be left unconnected and its output remains in its low state. The output voltage swing meets the RSC specifications of V minimum with the worst case conditions of: all transmitters driving k minimum load impedance, =.V, and maximum allowable operating temperature. The FN Rev.00 Page of

5 transmitters have an internally limited output slew rate which is less than 0V/ s. The outputs are short circuit protected and can be shorted to ground indefinitely. The powered down output impedance is a minimum of 00 with V applied to the outputs and = 0V. Receivers The receiver inputs accept up to 0V while presenting the required k to k input impedance even if the power is off ( = 0V). The receivers have a typical input threshold of.v which is within the V limits, known as the transition region, of the RS specifications. The receiver output is 0V to. The output will be low whenever the input is greater than.v and high whenever the input is floating or driven between 0.V and 0V. The receivers feature 0.V hysteresis (except during shutdown) to improve noise rejection. V 00k T XIN GND < T XIN < V 00 FIGURE. TRANSMITTER R XIN 0V < R XIN < 0V GND k T OUT V < V TOUT < V R OUT GND < V ROUT < T IN OR R IN T OUT OR R OUT t PHL Application Information t PLH AVERAGE PROPAGATION DELAY = t PHL t PLH FIGURE. PROPAGATION DELAY DEFINITION V OH V OL The HINA may be used for all RS data terminal and communication links. It is particularly useful in applications where V power supplies are not available for conventional RS interface circuits. The applications presented represent typical interface configurations. A simple duplex RS port with CTS/RTS handshaking is illustrated in Figure. Fixed output signals such as DTR (data terminal ready) and DSRS (data signaling rate select) is generated by driving them through a k resistor connected to V. In applications requiring four RS inputs and outputs (Figure ), note that each circuit requires two charge pump capacitors (C and C) but can share common reservoir capacitors (C and C). The benefit of sharing common reservoir capacitors is the elimination of two capacitors and the reduction of the charge pump source impedance which effectively increases the output swing of the transmitters. FIGURE. RECEIVER INPUTS OUTPUTS TTL/CMOS C C V TD RTS RD CTS HINA T T R R CTR (0) DATA TERMINAL READY DSRS () DATA SIGNALING RATE SELECT RS INPUTS AND OUTPUTS TD () TRANSMIT DATA RTS () REQUEST TO SEND RD () RECEIVE DATA CTS () CLEAR TO SEND SIGNAL GROUND () FIGURE. SIMPLE DUPLEX RS PORT WITH CTS/RTS HANDSHAKING FN Rev.00 Page of

6 INPUTS OUTPUTS TTL/CMOS C TD RTS RD CTS HINA T T R R C TD () TRANSMIT DATA RTS () REQUEST TO SEND RD () RECEIVE DATA CTS () CLEAR TO SEND C 0. F V V C 0. F V RS INPUTS AND OUTPUTS INPUTS OUTPUTS TTL/CMOS C DTR DSRS DCD R HINA T T R R C DTR (0) DATA TERMINAL READY DSRS () DATA SIGNALING RATE SELECT DCD () DATA CARRIER DETECT R () RING INDICATOR SIGNAL GROUND () FIGURE. COMBINING TWO HINAs FOR PAIRS OF RS INPUTS AND OUTPUTS Typical Performance Curves V SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) V ( = V) V ( = V) V ( = V) T A = o C TRANSMITTER OUTPUTS OPEN CIRCUIT I LOAD (ma) V ( = V) 0 FIGURE. V SUPPLY VOLTAGE vs FIGURE. V, V OUTPUT VOLTAGE vs LOAD FN Rev.00 Page of

7 Die Characteristics DIE DIMENSIONS 0 mils x mils METALLIZATION Type: Al Thickness: kå kå SUBSTRATE POTENTIAL V PASSIVATION Type: Nitride over Silox Nitride Thickness: kå Silox Thickness: kå TRANSISTOR COUNT PROCESS CMOS Metal Gate FN Rev.00 Page of

8 DualInLine Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B C A N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M.. Symbols are defined in the MO Series Symbol List in Section. of Publication No... Dimensions A, A and L are measured with the package seated in JE DEC seating plane gauge GS.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.0 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum C.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.0 inch (0.mm).. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E., E., E., E., E. will have a B dimension of inch (0..mm). B A 0.0 (0.) M C A A L B S A e C E C L e A C e B E. (JEDEC MS00BB ISSUE D) LEAD DUALINLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.. A A B B , C D D E E e 0.0 BSC. BSC e A 0.00 BSC. BSC e B 0.0. L N Rev. 0 / FN Rev.00 Page of

9 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.0) M C A M E B A C SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x C M. (JEDEC MS0AA ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC. BSC H h L N 0 0 Rev. /0 FN Rev.00 Page of

10 N Small Outline Plastic Packages (SOIC) INDEX AREA e D B 0.(0.0) M C A M E B A C SEATING PLANE A B S H A µ 0.(0.0) M B 0.(0.00) L M h x o C M. (JEDEC MS0AC ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC. BSC H h L N 0 o o 0 o o Rev. 0/0 NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO00 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN Rev.00 Page of