ICL3224, ICL3226, ICL3238, ICL3244

Transcription

1 ICL3, ICL3, ICL338, ICL3 Data Sheet FN87.0 Microamp, 3V to.v, 0kbps, RS-3 Transceivers with Enhanced Automatic Powerdown The Intersil ICL3XX devices are 3.0V to.v powered RS-3 transmitters/receivers which meet ElA/TIA-3 and V.8/V. specifications, even at = 3.0V. Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and enhanced automatic powerdown functions, reduce the standby supply current to a µa trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 0kbps are guaranteed at worst case load conditions. This family is fully compatible with 3.3V only systems, mixed 3.3V and.0v systems, and.0v only systems. The ICL3 is a 3 driver, receiver device that provides a complete serial port suitable for laptop or notebook computers. The ICL3/38 also include a noninverting always-active receiver for RING INDICATOR monitoring. These devices feature an enhanced automatic powerdown function which powers down the on-chip powersupply and driver circuits. This occurs when all receiver and transmitter inputs detect no signal transitions for a period of 30sec. These devices power back up, automatically, whenever they sense a transition on any transmitter or receiver input. Table summarizes the features of the devices represented by this data sheet, while Application Note AN983 summarizes the features of each device comprising the ICL3XX 3V family. Features Pb-Free Plus Anneal Available (RoHS Compliant) ±kv ESD Protected (Human Body Model) Manual and Enhanced Automatic Powerdown Features Drop in Replacements for MAX3, MAX3, MAX338, MAX3 Meets EIA/TIA-3 and V.8/V. Specifications at 3V Latch-Up Free RS-3 Compatible with =.7V On-Chip Voltage Converters Require Only Four External Capacitors Flow-Through Pinout (ICL338) Guaranteed Mouse Driveability (ICL3) Ready to Transmit Indicator Output (ICL3/) Receiver Hysteresis For Improved Noise Immunity Guaranteed Minimum Data Rate kbps Guaranteed Minimum Slew Rate V/µs Wide Power Supply Range Single 3V to.v Low Supply Current in Powerdown State µA Applications Any System Requiring RS-3 Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones - Data Cradles Related Literature TABLE. SUMMARY OF FEATURES Technical Brief TB33 Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) AN983, 3V to.v, 0k-Mbps, RS-3 Transmitters/Receivers PART NUMBER NO. OF Tx. NO. OF Rx. NO. OF MONITOR Rx. (R OUTB ) DATA RATE (kbps) Rx. ENABLE FUNCTION? READY OUTPUT? MANUAL POWER- DOWN? ENHANCED AUTOMATIC POWERDOWN ICL3 0 0 NO YES YES YES ICL3 0 0 NO YES YES YES ICL NO NO YES YES ICL3 3 0 NO NO YES YES CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 0, 0, 0-0. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Ordering Information Ordering Information (Continued) PART NUMBER* PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # PART NUMBER* PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # ICL3CA ICL3CA 0 to 70 Ld SSOP M.9 ICL3CAZ (Note) 3CAZ 0 to 70 Ld SSOP (Pb-free) M.9 ICL3IA ICL3IA -0 to 8 Ld SSOP M.9 ICL3IAZ (Note) 3IAZ -0 to 8 Ld SSOP (Pb-free) M.9 ICL3CA ICL3CA 0 to 70 Ld SSOP M.9 ICL338CAZ (Note) ICL338CAZ 0 to 70 8 Ld SSOP (Pb-free) M8.9 ICL338IA ICL338IA -0 to 8 8 Ld SSOP M8.9 ICL338IAZ (Note) ICL338IAZ -0 to 8 8 Ld SSOP (Pb-free) M8.9 ICL3CA ICL3CA 0 to 70 8 Ld SSOP M8.9 ICL3IA ICL3IA -0 to 8 8 Ld SSOP M8.9 ICL3CAZ (Note) ICL3CAZ 0 to 70 Ld SSOP (Pb-free) M.9 *Most surface mount devices are available on tape and reel; add -T to suffix. ICL3IA ICL3IA -0 to 8 Ld SSOP M.9 ICL3IAZ (Note) ICL3IAZ -0 to 8 Ld SSOP (Pb-free) M.9 ICL338CA ICL338CA 0 to 70 8 Ld SSOP M8.9 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-0. Pinouts ICL3 (SSOP) TOP VIEW ICL3 (SSOP) TOP VIEW READY READY C 9 C V 3 8 V 3 C- 7 T OUT C- 3 T OUT C R IN C C- R OUT C- T IN V- 7 V- 7 0 T OUT 8 3 T IN R IN 8 9 R OUT R IN 9 T IN R OUT 0 FN87.0

3 Pinouts (Continued) ICL338 (SSOP) TOP VIEW ICL3 (SSOP) TOP VIEW C V C- R OUTB R OUT R OUT R3 OUT R OUT R OUT C C- V- T OUT T OUT T3 OUT R IN R IN T OUT R3 IN T OUT C V C- T IN T IN T3 IN R OUT R OUT T IN R3 OUT T IN R OUTB C C- V- R IN R IN R3 IN R IN R IN T OUT T OUT T3 OUT T3 IN T IN T IN 3 FN87.0

4 Pin Descriptions PIN FUNCTION System power supply input (3.0V to.v). V Internally generated positive transmitter supply (.V). V- Internally generated negative transmitter supply (-.V). Ground connection. C External capacitor (voltage doubler) is connected to this lead. C- External capacitor (voltage doubler) is connected to this lead. C External capacitor (voltage inverter) is connected to this lead. C- External capacitor (voltage inverter) is connected to this lead. T IN T OUT R IN R OUT R OUTB READY TTL/CMOS compatible transmitter Inputs. RS-3 level (nominally ±.V) transmitter outputs. RS-3 compatible receiver inputs. TTL/CMOS level receiver outputs. TTL/CMOS level, noninverting, always enabled receiver outputs. Active low output that indicates if no valid RS-3 levels are present on any receiver input. Active high output that indicates when the ICL3XX is ready to transmit (i.e., V- -V) Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and (see Table ). Active high input to override automatic powerdown circuitry thereby keeping transmitters active. ( must be high). Typical Operating Circuits ICL3 ICL3 9 V V- T T R kω R kω C 3 C T OUT T OUT RIN 9 RIN RS-3 LEVELS 3.3V C C C- C C C- 3 T IN T IN TTL/CMOS LOGIC LEVELS R OUT 0 R OUT READY 3.3V C C 3 V C 3 C- C C V- 7 C C- T 3 T IN TTL/CMOS T OUT RS-3 LOGIC 9 8 LEVELS LEVELS R OUT RIN R kω READY 0 TO POWER CONTROL LOGIC 8 TO POWER CONTROL LOGIC FN87.0

5 Typical Operating Circuits (Continued) 3.3V C NOTE 3 C TTL/CMOS LOGIC LEVELS T IN 3 ICL338 T T V 7 C 3 T OUT T IN T OUT T 3 7 R OUTB R OUT R OUT R3 OUT TO POWER CONTROL LOGIC T IN 8 3 R R R 3 C 3 (OPTIONAL CONNECTION, NOTE ) V- kω kω kω T3 IN T3 OUT 9 T 3 0 T IN T OUT 7 T T OUT 8 R IN 9 R IN R3 IN NOTE 3 C RS-3 LEVELS RS-3 LEVELS 3.3V TTL/CMOS LOGIC LEVELS C C 8 C C- C 3 C- 8 C C- C C- T IN T3 IN 3 ICL3 T T V 7 C 3 T OUT T IN T OUT T 3 R OUTB R OUT R OUT R3 OUT R OUT TO POWER CONTROL LOGIC R OUT 3 R R R R 3 R V- kω kω kω kω kω T3 OUT R IN 7 8 R IN R3 IN R IN R IN C RS-3 LEVELS RS-3 LEVELS NOTES:. THE NEGATIVE TERMINAL OF C 3 CAN BE CONNECTED TO EITHER OR.. FOR = 3.V (3.3V -%), USE C - C = OR GREATER. FOR = 3.0V (3.3V -0%), USE C - C = 0.µF. FN87.0

6 Absolute Maximum Ratings to Ground V to V V to Ground V to 7V V- to Ground V to -7V V to V V Input Voltages T IN,, V to V R IN ±V Output Voltages T OUT ±3.V R OUT,, READY V to 0.3V Short Circuit Duration T OUT Continuous ESD Rating See Specification Table Thermal Information Thermal Resistance (Typical, Note ) θ JA ( C/W) Ld SSOP Package Ld SSOP Package Ld SSOP Package Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to 0 C Maximum Lead Temperature (Soldering 0s) C (Lead Tips Only) Operating Conditions Temperature Range ICL3XXC C to 70 C ICL3XXI C to 8 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Test Conditions: = 3V to.v, C - C = (ICL338: C - C = = 3V); Unless Otherwise Specified. Typicals are at T A = C PARAMETER DC CHARACTERISTICS Supply Current, Automatic Powerdown TEST CONDITIONS TEMP ( C) MIN TYP MAX UNITS All R IN Open, =, = µa Supply Current, Powerdown = µa Supply Current, Automatic Powerdown Disabled All Outputs Unloaded, ICL3, = 3V ma = = All Others, = 3.V ma LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low T IN,, Full V Input Logic Threshold High T IN,, = 3.3V Full V =.0V Full. - - V Transmitter Input Hysteresis V Input Leakage Current T IN,, Full - ±0.0 ±.0 µa Output Leakage Current = Full - ±0.0 ±0 µa Output Voltage Low I OUT =.ma Full V Output Voltage High I OUT = -.0mA Full V RECEIVER INPUTS Input Voltage Range Full - - V Input Threshold Low = 3.3V V =.0V V Input Threshold High = 3.3V -.. V =.0V -.8. V Input Hysteresis V Input Resistance 3 7 kω TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full ±.0 ±. - V Output Resistance = V = V- = 0V, Transmitter Output = ±V Full 300 0M - Ω Output Short-Circuit Current Full - ±3 ±0 ma Output Leakage Current V OUT = ±V, = 0V or 3V to.v, Automatic Powerdown or = Full - - ± µa FN87.0

7 Electrical Specifications PARAMETER MOUSE DRIVEABILITY (ICL3 Only) Transmitter Output Voltage (See Figure ) T IN = T IN =, T3 IN =, T3 OUT Loaded with 3kΩ to, T OUT and T OUT Loaded with.ma Each Full ± - - V ENHANCED AUTOMATIC POWERDOWN ( =, = ) Receiver Input Thresholds to High See Figure Full V Receiver Input Thresholds to Low, READY Output Voltage Low, READY Output Voltage High Receiver Positive or Negative Threshold to High Delay (t INVH ) Receiver Positive or Negative Threshold to Low Delay (t INVL ) Receiver or Transmitter Edge to Transmitters Enabled Delay (t WU ) Receiver or Transmitter Edge to Transmitters Disabled Delay (t AUTOPWDN ) Test Conditions: = 3V to.v, C - C = (ICL338: C - C = = 3V); Unless Otherwise Specified. Typicals are at T A = C (Continued) TEST CONDITIONS TEMP ( C) MIN TYP MAX UNITS See Figure Full V I OUT =.ma Full V I OUT = -.0mA Full V ICL µs All Others - - µs ICL µs All Others µs ICL338, Note - - µs All Others, Note µs Note Full 30 0 sec TIMING CHARACTERISTICS Maximum Data Rate R L = 3kΩ, C L = 000pF, One Transmitter Switching Full kbps Receiver Propagation Delay Receiver Input to Receiver t PHL µs Output, C L = 0pF t PLH µs Receiver Output Enable Time Normal Operation (ICL338/ Only) ns Receiver Output Disable Time Normal Operation (ICL338/ Only) ns Transmitter Skew t PHL - t PLH ns Receiver Skew t PHL - t PLH ns Transition Region Slew Rate = 3.3V, C L = 0pF to 000pF - 30 V/µs R L = 3kΩ to 7kΩ, Measured From 3V to -3V or -3V to 3V C L = 0pF to 00pF 8 30 V/µs ESD PERFORMANCE RS-3 Pins (T OUT, R IN ) Human Body Model - ± - kv IEC000-- Contact Discharge - ±8 - kv IEC000-- Air Gap Discharge - ±0 - kv All Other Pins Human Body Model - ±. - kv NOTE:. An edge is defined as a transition through the transmitter or receiver input thresholds. 7 FN87.0

8 Detailed Description These ICL3XX interface ICs operate from a single 3V to.v supply, guarantee a 0kbps minimum data rate, require only four small external capacitors, feature low power consumption, and meet all ElA RS-3C and V.8 specifications. The circuit is divided into three sections: The charge pump, the transmitters, and the receivers. Charge-Pump Intersil s new ICL3XX family utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate ±.V transmitter supplies from a supply as low as 3.0V. This allows these devices to maintain RS-3 compliant output levels over the ±0% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small, external capacitors for the voltage doubler and inverter functions at = 3.3V. See the Capacitor Selection section, and Table 3 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V and V- supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-3 output levels. Coupled with the on-chip ±.V supplies, these transmitters deliver true RS-3 levels over a wide range of single supply system voltages. Transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (see Table ). These outputs may be driven to ±V when disabled. All devices guarantee a 0kbps data rate for full load conditions (3kΩ and 000pF), 3.0V, with one transmitter operating at full speed. Under more typical conditions of 3.3V, R L = 3kΩ, and C L = 0pF, one transmitter easily operates at Mbps. Transmitter inputs float if left unconnected, and may cause I CC increases. Connect unused inputs to for the best performance. Receivers All the ICL3XX devices contain standard inverting receivers, but only the ICL338 and ICL3 receivers can tristate, via the control line. Additionally, the ICL338 and ICL3 include a noninverting (monitor) receiver (denoted by the R OUTB label) that is always active, regardless of the state of any control lines. Both receiver types convert RS-3 signals to CMOS output levels and accept inputs up to ±V while presenting the required 3kΩ to 7kΩ input impedance (see Figure ) even if the power is off ( = 0V). The receivers Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. The ICL338 and ICL3 inverting receivers disable during forced (manual) powerdown, but not during automatic powerdown (see Table ). Conversely, the monitor receiver remains active even during manual powerdown making it extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral s protection diodes (see Figures and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure 3. R XIN -V V RIN V kω R XOUT V ROUT FIGURE. INVERTING RECEIVER CONNECTIONS POWERED DOWN UART Rx Tx V OUT = SHDN = CURRENT FLOW OLD RS-3 CHIP FIGURE. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL POWERED DOWN UART TO WAKE-UP LOGIC R X T X TRANSITION DETECTOR R OUTB V OUT = HI-Z R OUT T IN = ICL338/ R IN T OUT FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN 8 FN87.0

9 RCVR OR XMTR EDGE WITHIN 30 SEC? INPUT INPUT TABLE. POWERDOWN LOGIC TRUTH TABLE TRANSMITTER OUTPUTS RECEIVER OUTPUTS (NOTE ) R OUTB OUTPUTS RS-3 LEVEL PRESENT AT RECEIVER INPUT? OUTPUT MODE OF OPERATION ICL3, ICL3 NO H H Active Active N.A. NO L Normal Operation (Enhanced NO H H Active Active N.A. YES H Auto Powerdown Disabled) YES H L Active Active N.A. NO L Normal Operation (Enhanced YES H L Active Active N.A. YES H Auto Powerdown Enabled) NO H L High-Z Active N.A. NO L Powerdown Due to Enhanced NO H L High-Z Active N.A. YES H Auto Powerdown Logic X L X High-Z Active N.A. NO L Manual Powerdown X L X High-Z Active N.A. YES H ICL3X - DRIVING AND (EMULATES AUTOMATIC POWERDOWN) X NOTE 7 NOTE 7 Active Active N.A. YES H Normal Operation X NOTE 7 NOTE 7 High-Z Active N.A. NO L Forced Auto Powerdown ICL338, ICL3 NO H H Active Active Active NO L Normal Operation (Enhanced NO H H Active Active Active YES H Auto Powerdown Disabled) YES H L Active Active Active NO L Normal Operation (Enhanced YES H L Active Active Active YES H Auto Powerdown Enabled) NO H L High-Z Active Active NO L Powerdown Due to Enhanced NO H L High-Z Active Active YES H Auto Powerdown Logic X L X High-Z High-Z Active NO L Manual Powerdown X L X High-Z High-Z Active YES H ICL338, ICL3 - DRIVING AND (EMULATES AUTOMATIC POWERDOWN) X NOTE 7 NOTE 7 Active Active Active YES H Normal Operation X NOTE 7 NOTE 7 High-Z High-Z Active NO L Forced Auto Powerdown NOTES:. Applies only to the ICL338 and ICL3.. Input is connected to Output. Powerdown Functionality This 3V family of RS-3 interface devices requires a nominal supply current of 0.3mA during normal operation (not in powerdown mode). This is considerably less than the ma to ma current required of V RS-3 devices. The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to µa, because the on-chip charge pump turns off (V collapses to, V- collapses to ), and the transmitter outputs tristate. Inverting receiver outputs may or may not disable in powerdown; refer to Table for details. This micro-power mode makes these devices ideal for battery powered and portable applications. Software Controlled (Manual) Powerdown These devices allow the user to force the IC into the low power, standby state, and utilize a two pin approach where the and inputs determine the IC s mode. For always enabled operation, and are both strapped high. To switch between active and powerdown modes, under logic or software control, only the input need be driven. The state isn t critical, as dominates over. Nevertheless, if strictly manual control over powerdown is desired, the user must strap high to disable the enhanced automatic powerdown circuitry. ICL338 and ICL3 inverting (standard) receiver outputs also disable when the device is in powerdown, thereby eliminating the possible current path through a shutdown peripheral s input protection diode (see Figures and 3). Connecting and together disables the enhanced automatic powerdown feature, enabling them to function as a manual SHUTDOWN input (see Figure ). 9 FN87.0

10 With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 00µs. PWR MGT LOGIC ICL3XX are floating (but pulled to by the internal receiver pull down resistors), the logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, switches high, and the power management logic wakes up the interface block. can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to (as in the case of a powered down driver). CPU I/O UART.7V VALID RS-3 LEVEL - = INDETERMINATE FIGURE. CONNECTIONS FOR MANUAL POWERDOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT When using both manual and enhanced automatic powerdown ( = 0), the ICL3XX won t power up from manual powerdown until both and are driven high, or until a transition occurs on a receiver or transmitter input. Figure illustrates a circuit for ensuring that the ICL3XX powers up as soon as switches high. The rising edge of the Master Powerdown signal forces the device to power up, and the ICL3XX returns to enhanced automatic powerdown mode an RC time constant after this rising edge. The time constant isn t critical, because the ICL3XX remains powered up for 30 seconds after the falling edge, even if there are no signal transitions. This gives slow-to-wake systems (e.g., a mouse) plenty of time to start transmitting, and as long as it starts transmitting within 30 seconds both systems remain enabled. 0.3V -0.3V -.7V LEVEL - = 0 INDETERMINATE VALID RS-3 LEVEL - = FIGURE. DEFINITION OF VALID RS-3 RECEIVER LEVELS Enhanced Automatic Powerdown Even greater power savings is available by using these devices which feature an enhanced automatic powerdown function. When the enhanced powerdown logic determines that no transitions have occurred on any of the transmitter nor receiver inputs for 30 seconds, the charge pump and transmitters powerdown, thereby reducing supply current to µa. The ICL3XX automatically powers back up whenever it detects a transition on one of these inputs. This automatic powerdown feature provides additional system power savings without changes to the existing operating system. POWER MANAGEMENT UNIT MASTER POWERDOWN LINE MΩ ICL3XX Enhanced automatic powerdown operates when the input is low, and the input is high. Tying high disables automatic powerdown, but manual powerdown is always available via the overriding input. Table summarizes the enhanced automatic powerdown functionality. FIGURE. CIRCUIT TO ENSURE IMMEDIATE POWER UP WHEN EXITING FORCED POWERDOWN Output The output always indicates (see Table ) whether or not 30µs have elapsed with invalid RS-3 signals (see Figures and 8) persisting on all of the receiver inputs, giving the user an easy way to determine when the interface block should power down. Invalid receiver levels occur whenever the driving peripheral s outputs are shut off (powered down) or when the RS-3 interface cable is disconnected. In the case of a disconnected interface cable where all the receiver inputs T_IN R_IN EDGE DETECT EDGE DETECT 30sec TIMER FIGURE 7. ENHANCED AUTOMATIC POWERDOWN LOGIC S R AUTOSHDN 0 FN87.0

11 Figure 7 illustrates the enhanced powerdown control logic. Note that once the ICL3XX enters powerdown (manually or automatically), the 30 second timer remains timed out (set), keeping the ICL3XX powered down until transitions high, or until a transition occurs on a receiver or transmitter input. The output signal switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 8), but this has no direct effect on the state of the ICL3XX (see the next sections for methods of utilizing to power down the device). switches high µs after detecting a valid RS-3 level on a receiver input. operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry. The time to recover from automatic powerdown mode is typically 00µs. Emulating Standard Automatic Powerdown If enhanced automatic powerdown isn t desired, the user can implement the standard automatic powerdown feature (mimics the function on the ICL3/3/3) by connecting the output to the and inputs, as shown in Figure 9. After 30µs of invalid receiver levels, switches low and drives the ICL3XX into a forced powerdown condition. switches high as soon as a receiver input senses a valid RS-3 level, forcing the ICL3XX to power on. See the DRIVING AND section of Table for an operational summary. This operational mode is perfect for handheld devices that communicate with another computer via a detachable cable. Detaching the cable allows the internal receiver pull-down resistors to pull the inputs to (an invalid RS-3 level), causing the 30µs timer to time-out and drive the IC into powerdown. Reconnecting the cable restores valid levels, causing the IC to power back up. CPU I/O UART FIGURE 9. CONNECTIONS FOR AUTOMATIC POWERDOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT Hybrid Automatic Powerdown Options For devices which communicate only through a detachable cable, connecting to (with = 0) may be a desirable configuration. While the cable is attached and remain high, so the enhanced automatic powerdown logic powers down the RS- 3 device whenever there is 30 seconds of inactivity on the receiver and transmitter inputs. Detaching the cable allows the receiver inputs to drop to an invalid level (), so switches low and forces the RS-3 device to power down. The ICL3XX remains powered down until the cable is reconnected ( = = ) and a ICL3XX RECEIVER INPUTS } REGION TRANSMITTER INPUTS TRANSMITTER OUTPUTS t INVH OUTPUT t INVL t AUTOPWDN t WU t AUTOPWDN t WU READY OUTPUT V 0 V- FIGURE 8. ENHANCED AUTOMATIC POWERDOWN, AND READY TIMING DIAGRAMS FN87.0

12 transition occurs on a receiver or transmitter input (see Figure 7). For immediate power up when the cable is reattached, connect to through a network similar to that shown in Figure. Ready Output (ICL3 and ICL3 only) The Ready output indicates that the ICL3X is ready to transmit. Ready switches low whenever the device enters powerdown, and switches back high during power-up when V- reaches -V or lower. Capacitor Selection The charge pumps require capacitors for 3.3V operation. For other supply voltages refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of ) reduces ripple on the transmitter outputs and slightly reduces power consumption. C, C 3, and C can be increased without increasing C s value, however, do not increase C without also increasing C, C 3, and C to maintain the proper ratios (C to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V and V-. TABLE 3. REQUIRED CAPACITOR VALUES (Note 8) (V) C (µf) C, C 3, C (µf) 3.0 to 3. (3.3V ±0%) 0. (0.) 0. (0.) 3. to 3. (3.3V ±%) (0.) (0.). to to. 0. (0.) 0.7 (.0) NOTE: 7. Parenthesized values apply only to the ICL338 Power Supply Decoupling In most circumstances a bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple to ground with a capacitor of the same value as the charge-pump capacitor C. Connect the bypass capacitor as close as possible to the IC. Transmitter Outputs when Exiting Powerdown Figure 0 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS-3 levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 00pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately 3V. Operation Down to.7v ICL3XX transmitter outputs meet RS- levels (±3.7V), at the full data rate, with as low as.7v. RS- levels typically ensure interoperability with RS-3 devices. Mouse Driveability The ICL3 is specifically designed to power a serial mouse while operating from low voltage supplies. Figure shows the transmitter output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least ±V during worst case conditions (ma for paralleled V transmitters, 7.3mA for single V- transmitter). V/DIV V/DIV V/DIV High Data Rates READY TIME (µs/div.) The ICL3XX maintain the RS-3 ±V minimum transmitter output voltages even at high data rates. Figure details a transmitter loopback test circuit, and Figure 3 illustrates the loopback test result at kbps. For this test, all transmitters were simultaneously driving RS-3 loads in parallel with T = 3.3V C - C = FIGURE 0. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN TRANSMITTER OUTPUT VOLTAGE (V) V OUT 3 = 3.0V T 0 V OUT - T - ICL3-3 - T3 V OUT - V OUT LOAD CURRENT PER TRANSMITTER (ma) FIGURE. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL V OUT CURRENT) T FN87.0

13 000pF, at kbps. Figure shows the loopback results for a single transmitter driving 000pF and an RS-3 load at 0kbps. The static transmitters were also loaded with an RS-3 receiver. V/DIV. T IN V C CC V C C 3 C- ICL3XX C V- C C C- T OUT R OUT = 3.3V C - C = T IN T OUT µs/div. R OUT R IN 000pF FIGURE. LOOPBACK TEST AT 0kbps K FIGURE. TRANSMITTER LOOPBACK TEST CIRCUIT V/DIV. T IN Interconnection with 3V and V Logic The ICL3XX directly interface with V CMOS and TTL logic families. Nevertheless, with the ICL3XX at 3.3V, and the logic supply at V, AC, HC, and CD000 outputs can drive ICL3XX inputs, but ICL3XX outputs do not reach the minimum V IH for these logic families. See Table for more information. TABLE. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES T OUT SYSTEM POWER-SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) COMPATIBILITY R OUT = 3.3V C - C = µs/div. FIGURE 3. LOOPBACK TEST AT kbps Compatible with all CMOS families. Compatible with all TTL and CMOS logic families. 3.3 Compatible with ACT and HCT CMOS, and with TTL. ICL3XX outputs are incompatible with AC, HC, and CD000 CMOS inputs. 3 FN87.0

14 Typical Performance Curves = 3.3V, T A = C TRANSMITTER OUTPUT VOLTAGE (V) ICL3, ICL3, ICL3 TRANSMITTER AT 0kbps OTHER TRANSMITTERS AT 30kbps V OUT V OUT LOAD CAPACITANCE (pf) FIGURE. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE TRANSMITTER OUTPUT VOLTAGE (V) ICL338 TRANSMITTER AT 0kbps OTHER TRANSMITTERS AT 30kbps V OUT V OUT LOAD CAPACITANCE (pf) FIGURE. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE SLEW RATE (V/µs) 0 SLEW -SLEW SUPPLY CURRENT (ma) ICL3 0kbps kbps kbps LOAD CAPACITANCE (pf) FIGURE 7. SLEW RATE vs LOAD CAPACITANCE LOAD CAPACITANCE (pf) FIGURE 8. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA 3 30 ICL3 0kbps 0 ICL338 SUPPLY CURRENT (ma) 0 kbps kbps SUPPLY CURRENT (ma) kbps kbps kbps LOAD CAPACITANCE (pf) FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FN87.0

15 Typical Performance Curves = 3.3V, T A = C (Continued) SUPPLY CURRENT (ma) ICL3 0kbps kbps kbps LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA SUPPLY CURRENT (ma) SUPPLY VOLTAGE (V) NO LOAD ALL OUTPUTS STATIC FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR COUNT: ICL3: 937 ICL3: 8 ICL338: 3 ICL3: 09 PROCESS: Si Gate CMOS FN87.0

16 Small Outline Plastic Packages (SSOP) ICL3, ICL3, ICL338, ICL3 N INDEX AREA 3 e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm ( inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.3mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α GAUGE PLANE A M L C M.9 (JEDEC MO-0-AC ISSUE B) LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N 7 α Rev. 3 /0 FN87.0

17 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA 3 e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm ( inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.3mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. A α GAUGE PLANE 0.0(0.00) A M L C M.9 (JEDEC MO-0-AE ISSUE B) LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC H L N 7 α 0 deg. 8 deg. 0 deg. 8 deg. Rev. 3 /0 7 FN87.0

18 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA 3 e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm ( inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.3mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α GAUGE PLANE A M L C M8.9 (JEDEC MO-0-AH ISSUE B) 8 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N α Rev. /0 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 8 FN87.0