Features TABLE 1. SUMMARY OF FEATURES. DATA RATE (kbps)

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1 DATASHEET ICL, ICL, ICL, ICL, ICL, ICL One Microamp Supply-Current, V to.v, 0kbps, RS- Transmitters/Receivers FN80 Rev.00 The Intersil ICLXX devices are.0v to.v powered RS- transmitters/receivers which meet ElA/TIA- and V.8/V. specifications, even at =.0V. Targeted applications are PDAs, Palmtops, and notebook and laptop computers where the low operational, and even lower standby, power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic powerdown functions (except for the ICL), reduce the standby supply current to a A trickle. Small footprint packaging, and the use of small, low value capacitors ensure board space savings as well. Data rates greater than 0kbps are guaranteed at worst case load conditions. This family is fully compatible with.v only systems, mixed.v and.0v systems, and.0v only systems. The ICLX are -driver, -receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting alwaysactive receivers for wake-up capability. The ICL, ICL and ICL, feature an automatic powerdown function which powers down the on-chip power-supply and driver circuits. This occurs when an attached peripheral device is shut off or the RS- cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS- voltage is applied to any receiver input. Table summarizes the features of the devices represented by this data sheet, while Application Note AN8 summarizes the features of each device comprising the ICLXX V family. Features Pb-Free Plus Anneal Available as an Option (RoHS Compliant) (See Ordering Info) kv ESD Protected (Human Body Model) Drop in Replacements for MAX, MAX, MAX, MAX, MAX, MAX, SP ICL is Low Power, Pin Compatible Upgrade for V MAX ICL is Low Power, Pin Compatible Upgrade for V MAX, and SPA ICL is Low Power Upgrade for HIN/ICL and Pin Compatible Competitor Devices RS- Compatible with =.7V Meets EIA/TIA- and V.8/V. Specifications at V Latch-Up Free On-Chip Voltage Converters Require Only Four External Capacitors Manual and Automatic Powerdown Features (Except ICL) Guaranteed Mouse Driveability (ICLX Only) Receiver Hysteresis For Improved Noise Immunity Guaranteed Minimum Data Rate kbps Guaranteed Minimum Slew Rate V/ s Wide Power Supply Range Single V to.v Low Supply Current in Powerdown State A Applications Any System Requiring RS- Communication Ports - Battery Powered, Hand-Held, and Portable Equipment - Laptop Computers, Notebooks, Palmtops - Modems, Printers and other Peripherals - Digital Cameras - Cellular/Mobile Phones TABLE. SUMMARY OF FEATURES PART NUMBER NO. OF Tx. NO. OF Rx. NO. OF MONITOR Rx. (R OUTB ) DATA RATE (kbps) Rx. ENABLE FUNCTION? READY OUTPUT? MANUAL POWER- DOWN? AUTOMATIC POWERDOWN FUNCTION? ICL 0 0 Yes No Yes Yes ICL 0 0 Yes No Yes No ICL 0 0 Yes No Yes Yes ICL 0 0 No No No No ICL 0 Yes No Yes No ICL 0 No No Yes Yes FN80 Rev.00 Page of 8

2 Ordering Information PART NUMBER (NOTE ) PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # ICLCAZ (Note ) ICLCAZ 0 to 70 Ld SSOP (Pb-free) M.0 ICLCVZ (Note ) CVZ 0 to 70 Ld TSSOP (Pb-free) M.7 ICLIAZ (Note ) ICLIAZ -0 to 8 Ld SSOP (Pb-free) M.0 ICLCAZ (Note ) ICLCAZ 0 to 70 0 Ld SSOP (Pb-free) M0.0 ICLCBZ (Note ) CBZ 0 to 70 8 Ld SOIC (Pb-free) M8. ICLCPZ (Note ) (No longer available or supported) ICLCPZ 0 to 70 8 Ld PDIP* (Pb-free) E8. ICLCVZ (Note ) ICLCVZ 0 to 70 0 Ld TSSOP (Pb-free) M0.7 ICLIAZ (Note ) ICLIAZ -0 to 8 0 Ld SSOP (Pb-free) M0.0 ICLIVZ (Note ) ICLIVZ -0 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLCAZ (Note ) ICLCAZ 0 to 70 0 Ld SSOP (Pb-free) M0.0 ICLCPZ (Note ) (No longer available, recommended replacement:iclecvz) ICLCPZ 0 to 70 0 Ld PDIP* (Pb-free) E0. ICLIAZ (Note ) ICLIAZ -0 to 8 0 Ld SSOP (Pb-free) M0.0 ICLIVZ (Note ) ICLIVZ -0 to 8 0 Ld TSSOP (Pb-free) M0.7 ICLCAZ (Note ) CAZ 0 to 70 Ld SSOP (Pb-free) M.0 ICLCBZ (Note ) CBZ 0 to 70 Ld SOIC (Pb-free) M. ICLCBNZ (Note ) CBNZ 0 to 70 Ld SOIC (N) (Pb-free) M. ICLCPZ (Note ) ICLCPZ 0 to 70 Ld PDIP* (Pb-free) E. ICLCVZ (Note ) CVZ 0 to 70 Ld TSSOP (Pb-free) M.7 ICLIAZ (Note ) IAZ -0 to 8 Ld SSOP (Pb-free) M.0 ICLIBZ (Note ) IBZ -0 to 8 Ld SOIC (Pb-free) M. ICLIBNZ (Note ) IBNZ -0 to 8 Ld SOIC (N) (Pb-free) M. ICLIVZ (Note ) IVZ -0 to 8 Ld TSSOP (Pb-free) M.7 ICLCAZ (Note ) ICLCAZ 0 to 70 8 Ld SSOP (Pb-free) M8.0 ICLCBZ (Note ) (No longer available, recommended replacement:icleivz) ICLCBZ 0 to 70 8 Ld SOIC (Pb-free) M8. ICLCVZ (Note ) ICLCVZ 0 to 70 8 Ld TSSOP (Pb-free) M8.7 ICLIAZ (Note ) ICLIAZ -0 to 8 8 Ld SSOP (Pb-free) M8.0 ICLIBZ (Note ) (No longer available, recommended replacement:icleivz ICLIBZ -0 to 8 8 Ld SOIC (Pb-free) M8. ICLCAZ (Note ) ICLCAZ 0 to 70 8 Ld SSOP (Pb-free) M8.0 ICLCBZ (Note ) ICLCBZ 0 to 70 8 Ld SOIC (Pb-free) M8. ICLCVZ (Note ) ICLCVZ 0 to 70 8 Ld TSSOP (Pb-free) M8.7 ICLIAZ (Note ) ICLIAZ -0 to 8 8 Ld SSOP (Pb-free) M8.0 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTES:. Most surface mount devices are available on tape and reel; add -T to suffix.. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 0% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-00. FN80 Rev.00 Page of 8

3 Pinouts ICL (SSOP, TSSOP) TOP VIEW ICL (PDIP, SOIC) TOP VIEW 7 8 FORCEOFF T OUT FORCEON T IN INVALID R OUT EN C V C- C C- R IN EN C V C- C C- T OUT R IN SHDN T OUT R IN R OUT T IN T IN R OUT ICL (SSOP, TSSOP) TOP VIEW ICL (PDIP, SSOP, TSSOP) TOP VIEW EN 0 SHDN EN 0 FORCEOFF C C V 8 V 8 C- 7 T OUT C- 7 T OUT C R IN C R IN C- R OUT C- R OUT 7 NC 7 FORCEON T OUT 8 T IN T OUT 8 T IN R IN T IN R IN T IN R OUT NC R OUT INVALID ICL (PDIP, SOIC, SSOP, TSSOP) TOP VIEW ICL (SOIC, SSOP, TSSOP) TOP VIEW 7 8 T OUT R IN R OUT T IN T IN R OUT C V C- C C- T OUT R IN C C- R IN R IN R IN R IN R IN T OUT C V C- EN SHDN R OUTB R OUTB T OUT R OUT T OUT 8 R OUT T IN 7 R OUT T IN R OUT T IN R OUT FN80 Rev.00 Page of 8

4 Pinouts (Continued) ICL (SOIC, SSOP, TSSOP) TOP VIEW C 8 C C- 7 V R IN R IN C- R IN FORCEON R IN 7 FORCEOFF R IN 8 INVALID T OUT 0 R OUTB T OUT R OUT T OUT 8 R OUT T IN 7 R OUT T IN R OUT T IN R OUT Pin Descriptions PIN FUNCTION System power supply input (.0V to.v). V Internally generated positive transmitter supply (.V). Internally generated negative transmitter supply (-.V). Ground connection. C External capacitor (voltage doubler) is connected to this lead. C- External capacitor (voltage doubler) is connected to this lead. C External capacitor (voltage inverter) is connected to this lead. C- External capacitor (voltage inverter) is connected to this lead. T IN T OUT R IN R OUT R OUTB INVALID EN SHDN TTL/CMOS compatible transmitter Inputs. RS- level (nominally.v) transmitter outputs. RS- compatible receiver inputs. TTL/CMOS level receiver outputs. TTL/CMOS level, noninverting, always enabled receiver outputs. Active low output that indicates if no valid RS- levels are present on any receiver input. Active low receiver enable control; doesn t disable R OUTB outputs. Active low input to shut down transmitters and on-board power supply, to place device in low power mode. FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (See Table ). FORCEON Active high input to override automatic powerdown circuitry thereby keeping transmitters active. (FORCEOFF must be high). FN80 Rev.00 Page of 8

5 Typical Operating Circuits ICL ICL C (OPTIONAL CONNECTION, NOTE) C (OPTIONAL CONNECTION, NOTE) TTL/CMOS LOGIC LEVELS.V C C C V T TIN R OUT EN R FORCEON k FORCEOFF INVALID 7 8 NOTE: The negative terminal of C can be connected to either or C C T OUT R IN RS- LEVELS TO POWER CONTROL LOGIC TTL/CMOS LOGIC LEVELS.V C C T IN T IN R OUT R OUT C- C C- C C- C C- EN 7 R R T T V k k SHDN C C T OUT T OUT R IN R IN RS- LEVELS NOTE: The negative terminal of C can be connected to either or ICL ICL TTL/CMOS LOGIC LEVELS.V C C T IN T IN R OUT R OUT EN V T T R k R k FORCEOFF C C T OUT T OUT R IN R IN RS- LEVELS TTL/CMOS LOGIC LEVELS.V C C T IN T IN R OUT R OUT C C C- C C- C- C C- C (OPTIONAL CONNECTION, NOTE) R R T T V k k 7 8 C C T OUT T OUT R IN R IN RS- LEVELS FORCEON INVALID 8 TO POWER CONTROL LOGIC NOTE: The negative terminal of C can be connected to either or FN80 Rev.00 Page of 8

6 Typical Operating Circuits (Continued) ICL ICL.V C C T IN T V 7 C C T OUT.V C C T IN 8 C C- C C- 8 C C- C C- T V 7 C C T OUT T IN T IN T T T OUT T OUT RS- LEVELS T IN T IN T T T OUT T OUT RS- LEVELS TTL/CMOS LOGIC LEVELS R OUTB 0 R OUTB R OUT 8 R OUT R R k k R IN R IN TTL/CMOS LOGIC LEVELS R OUTB R OUT R OUT 0 8 R R k k R IN R IN R OUT R OUT R OUT 7 EN SHDN R R R k k k 7 8 R IN R IN R IN RS- LEVELS TO POWER CONTROL LOGIC R OUT R OUT R OUT 7 R R R FORCEON FORCEOFF INVALID k k k 7 8 R IN R IN R IN RS- LEVELS FN80 Rev.00 Page of 8

7 Absolute Maximum Ratings to Ground V to V V to Ground V to 7V to Ground V to -7V V to V Input Voltages T IN, FORCEOFF, FORCEON, EN, SHDN V to V R IN V Output Voltages T OUT V R OUT, INVALID V to 0.V Short Circuit Duration T OUT Continuous ESD Rating See Specification Table Operating Conditions Temperature Range ICLXXCX C to 70 C ICLXXIX C to 8 C Thermal Information Thermal Resistance (Typical, Note ) JA ( C/W) Ld PDIP Package* Ld PDIP Package* Ld PDIP Package* Ld Wide SOIC Package Ld Narrow SOIC Package Ld SOIC Package Ld SOIC Package Ld SSOP Package Ld SSOP Package Ld TSSOP Package Ld TSSOP Package Ld SSOP and TSSOP Packages Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to 0 C Maximum Lead Temperature (Soldering s) C (SOIC, SSOP, TSSOP - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB7 for details. Electrical Specifications Test Conditions: VCC = V to.v, C - C = ; Unless Otherwise Specified. Typicals are at TA = C PARAMETER DC CHARACTERISTICS Supply Current, Automatic Powerdown TEST CONDITIONS All R IN Open, FORCEON =, FORCEOFF = (ICL, ICL, ICL Only) TEMP ( C) MIN TYP MAX UNITS -.0 A Supply Current, Powerdown FORCEOFF = SHDN = (Except ICL) -.0 A Supply Current, Automatic Powerdown Disabled All Outputs Unloaded, FORCEON = FORCEOFF = SHDN = VCC =.V, ICL ma VCC =.0V, ICL ma LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low T IN, FORCEON, FORCEOFF, EN, SHDN Full V Input Logic Threshold High T IN, FORCEON, FORCEOFF, EN, SHDN =.V Full V =.0V Full. - - V Input Leakage Current T IN, FORCEON, FORCEOFF, EN, SHDN Full A Output Leakage Current (Except ICL) FORCEOFF = or EN= Full A Output Voltage Low I OUT =.ma Full V Output Voltage High I OUT = -.0mA Full V AUTOMATIC POWERDOWN (ICL, ICL, ICL Only, FORCEON =, FORCEOFF = VCC) Receiver Input Thresholds to Enable Transmitters Receiver Input Thresholds to Disable Transmitters ICLXX Powers Up (See Figure ) Full V ICLXX Powers Down (See Figure ) Full V INVALID Output Voltage Low I OUT =.ma Full V INVALID Output Voltage High I OUT = -.0mA Full V FN80 Rev.00 Page 7 of 8

8 Electrical Specifications Test Conditions: VCC = V to.v, C - C = ; Unless Otherwise Specified. Typicals are at TA = C (Continued) PARAMETER Receiver Threshold to Transmitters Enabled Delay (t WU ) Receiver Positive or Negative Threshold to INVALID High Delay (t INVH ) Receiver Positive or Negative Threshold to INVALID Low Delay (t INVL ) s - - s s RECEIVER INPUTS Input Voltage Range Full - - V Input Threshold Low =.V V =.0V V Input Threshold High =.V -.. V =.0V -.8. V Input Hysteresis V Input Resistance 7 k TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with k to Ground Full.0. - V Output Resistance = V = = 0V, Transmitter Output = V Full 00 M - Output Short-Circuit Current Full - 0 ma Output Leakage Current V OUT = V, = 0V or V to.v Automatic Powerdown or FORCEOFF = SHDN = Full - - A MOUSE DRIVEABILITY (ICLX Only) Transmitter Output Voltage (See Figure ) TEST CONDITIONS T IN =T IN =, T IN =, T OUT Loaded with k to, T OUT and T OUT Loaded with.ma Each TEMP ( C) MIN TYP MAX UNITS Full - - V TIMING CHARACTERISTICS Maximum Data Rate R L =k C L = 00pF, One Transmitter Switching Full kbps Receiver Propagation Delay Receiver Input to Receiver t PHL s Output, C L = 0pF t PLH s Receiver Output Enable Time Normal Operation (Except ICL) ns Receiver Output Disable Time Normal Operation (Except ICL) ns Transmitter Skew t PHL - t PLH Full ns Receiver Skew t PHL - t PLH Full ns Transition Region Slew Rate =.V, C L = 00pF to 00pF V/ s R L =k to 7k Measured From V to -V or -V to V C L = 00pF to 00pF - 0 V/ s ESD PERFORMANCE RS- Pins (T OUT, R IN ) Human Body Model ICL - ICL - - kv IEC00-- Contact Discharge ICL - ICL kv IEC00-- Air Gap Discharge ICL - ICL kv ICL - ICL - - kv All Other Pins Human Body Model ICL - ICL - - kv FN80 Rev.00 Page 8 of 8

9 Detailed Description ICLXX interface ICs operate from a single V to.v supply, guarantee a 0kbps minimum data rate, require only four small external capacitors, feature low power consumption, and meet all ElA RS-C and V.8 specifications. The circuit is divided into three sections: charge pump, transmitters and receivers. Charge-Pump Intersil s new ICLXX family utilizes regulated on-chip dual charge pumps as voltage doublers, and voltage inverters to generate.v transmitter supplies from a supply as low as.0v. This allows these devices to maintain RS- compliant output levels over the % tolerance range of.v powered systems. The efficient on-chip power supplies require only four small, external capacitors for the voltage doubler and inverter functions at =.V. See the Capacitor Selection section, and Table for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (i.e., they turn off as soon as the V and supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA- output levels. Coupled with the on-chip.v supplies, these transmitters deliver true RS- levels over a wide range of single supply system voltages. Except for the ICL, all transmitter outputs disable and assume a high impedance state when the device enters the powerdown mode (See Table ). These outputs may be driven to V when disabled. All devices guarantee a 0kbps data rate for full load conditions (k and 00pF),.0V, with one transmitter operating at full speed. Under more typical conditions of.v, R L =k, and C L = 0pF, one transmitter easily operates at 00kbps. Transmitter inputs float if left unconnected, and may cause I CC increases. Connect unused inputs to for the best performance. Receivers All the ICLXX devices contain standard inverting receivers that three-state (except for the ICL) via the EN or FORCEOFF control lines. Additionally, the two ICLX products include noninverting (monitor) receivers (denoted by the R OUTB label) that are always active, regardless of the state of any control lines. All the receivers convert RS- signals to CMOS output levels and accept inputs up to V while presenting the required k to 7k input impedance (See Figure ) even if the power is off ( = 0V). The receivers Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. The ICL/// inverting receivers disable only when EN is driven high. ICL receivers disable during forced (manual) powerdown, but not during automatic powerdown (See Table ). ICLX monitor receivers remain active even during manual powerdown and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral s protection diodes (See Figures and ). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task as shown in Figure. R XIN -V V RIN V k Low Power Operation R XOUT V ROUT FIGURE. INVERTING RECEIVER CONNECTIONS These V devices require a nominal supply current of 0.mA, even at =.V, during normal operation (not in powerdown mode). This is considerably less than the ma to ma current required by comparable V RS- devices, allowing users to reduce system power simply by switching to this new family. Pin Compatible Replacements For V Devices The ICL// are pin compatible with existing V RS- transceivers - see the Features section on the front page for details. This pin compatibility coupled with the low Icc and wide operating supply range, make the ICLXX potential lower power, higher performance drop-in replacements for existing V applications. As long as the V RS- output swings are acceptable, and transmitter input pull-up resistors aren t required, the ICLXX should work in most V applications. When replacing a device in an existing V application, it is acceptable to terminate C to as shown on the Typical Operating Circuit. Nevertheless, terminate C to if possible, as slightly better performance results from this configuration. Powerdown Functionality (Except ICL) The already low current requirement drops significantly when the device enters powerdown mode. In powerdown, supply current drops to A, because the on-chip charge pump turns off (V collapses to, collapses to ), and the transmitter outputs three-state. Inverting receiver outputs may or may not disable in powerdown; refer to Table for details. This micro-power mode makes these devices ideal for battery powered and portable applications. FN80 Rev.00 Page of 8

10 Software Controlled (Manual) Powerdown Most devices in the ICLXX family provide pins that allow the user to force the IC into the low power, standby state. On the ICL and ICL, the powerdown control is via a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its powerdown state. Connect SHDN to if the powerdown function isn t needed. Note that all the receiver outputs remain enabled during shutdown (See Table ). For the lowest power consumption during powerdown, the receivers should also be disabled by driving the EN input high (See next section, and Figures and ). The ICL, ICL, and ICL utilize a two pin approach where the FORCEON and FORCEOFF inputs determine the IC s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To switch between active and powerdown modes, under logic or software control, only the FORCEOFF input need be driven. The FORCEON state isn t critical, as FORCEOFF dominates over FORCEON. Nevertheless, if strictly manual control over powerdown is desired, the user must strap FORCEON high to disable the automatic powerdown circuitry. ICL inverting (standard) receiver outputs also disable when the device is in manual powerdown, thereby eliminating the possible current path through a shutdown peripheral s input protection diode (See Figures and ). TABLE. POWERDOWN AND ENABLE LOGIC TRUTH TABLE RS- SIGNAL PRESENT AT RECEIVER INPUT? FORCEOFF OR SHDN INPUT FORCEON INPUT EN INPUT TRANSMITTER OUTPUTS RECEIVER OUTPUTS (NOTE ) R OUTB OUTPUTS INVALID OUTPUT MODE OF OPERATION ICL, ICL N.A. L N.A. L High-Z Active Active N.A. Manual Powerdown N.A. L N.A. H High-Z High-Z Active N.A. Manual Powerdown w/rcvr. Disabled N.A. H N.A. L Active Active Active N.A. Normal Operation N.A. H N.A. H Active High-Z Active N.A. Normal Operation w/rcvr. Disabled ICL, ICL No H H L Active Active N.A. L Normal Operation No H H H Active High-Z N.A. L (Auto Powerdown Disabled) Yes H L L Active Active N.A. H Normal Operation Yes H L H Active High-Z N.A. H (Auto Powerdown Enabled) ICL No H L L High-Z Active N.A. L Powerdown Due to Auto Powerdown No H L H High-Z High-Z N.A. L Logic Yes L X L High-Z Active N.A. H Manual Powerdown Yes L X H High-Z High-Z N.A. H Manual Powerdown w/rcvr. Disabled No L X L High-Z Active N.A. L Manual Powerdown No L X H High-Z High-Z N.A. L Manual Powerdown w/rcvr. Disabled No H H N.A. Active Active Active L Normal Operation (Auto Powerdown Disabled) Yes H L N.A. Active Active Active H Normal Operation (Auto Powerdown Enabled) No H L N.A. High-Z Active Active L Powerdown Due to Auto Powerdown Logic Yes L X N.A. High-Z High-Z Active H Manual Powerdown No L X N.A. High-Z High-Z Active L Manual Powerdown NOTE:. Applies only to the ICL and ICL. FN80 Rev.00 Page of 8

11 The INVALID output always indicates whether or not a valid RS- signal is present at any of the receiver inputs (See Table ), giving the user an easy way to determine when the interface block should power down. In the case of a disconnected interface cable where all the receiver inputs are floating (but pulled to by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID can also be used to indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating, or driven to (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the automatic powerdown feature, enabling them to function as a manual SHUTDOWN input (See Figure ). POWERED DOWN UART Rx Tx V OUT = SHDN = CURRENT FLOW OLD RS- CHIP PWR MGT LOGIC CPU FIGURE. CONNECTIONS FOR MANUAL POWERDOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT With any of the above control schemes, the time required to exit powerdown, and resume transmission is only 0 s. A mouse, or other application, may need more time to wake up from shutdown. If automatic powerdown is being utilized, the RS- device will reenter powerdown if valid receiver levels aren t reestablished within 0 s of the ICLXX powering up. Figure illustrates a circuit that keeps the ICLXX from initiating automatic powerdown for 0ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS- output levels. POWER MANAGEMENT UNIT I/O UART FORCEOFF FORCEON INVALID ICL// MASTER POWERDOWN LINE M FIGURE. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL FORCEOFF FORCEON TO WAKE-UP LOGIC POWERED DOWN UART R X T X TRANSITION DETECTOR R OUTB V OUT = HI-Z R OUT T IN FORCEOFF = OR SHDN =, EN = ICLX R IN T OUT FIGURE. DISABLED RECEIVERS PREVENT POWER DRAIN ICL// FIGURE. CIRCUIT TO PREVENT AUTO POWERDOWN FOR 0ms AFTER FORCED POWERUP Automatic Powerdown (ICL// Only) Even greater power savings is available by using the devices which feature an automatic powerdown function. When no valid RS- voltages (See Figure ) are sensed on any receiver input for 0 s, the charge pump and transmitters powerdown, thereby reducing supply current to A. Invalid receiver levels occur whenever the driving peripheral s outputs are shut off (powered down) or when the RS- interface cable is disconnected. The ICLXX powers back up whenever it detects a valid RS- voltage level on any receiver input. This automatic powerdown feature provides additional system power savings without changes to the existing operating system. FN80 Rev.00 Page of 8

12 .7V 0.V -0.V -.7V FIGURE. DEFINITION OF VALID RS- RECEIVER LEVELS Automatic powerdown operates when the FORCEON input is low, and the FORCEOFF input is high. Tying FORCEON high disables automatic powerdown, but manual powerdown is always available via the overriding FORCEOFF input. Table summarizes the automatic powerdown functionality. Devices with the automatic powerdown feature include an INVALID output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 0 s (See Figure 7). INVALID switches high s after detecting a valid RS- level on a receiver input. INVALID operates in all modes (forced or automatic powerdown, or forced on), so it is also useful for systems employing manual powerdown circuitry. When automatic powerdown is utilized, INVALID = 0 indicates that the ICLXX is in powerdown mode. RECEIVER INPUTS TRANSMITTER OUTPUTS INVALID OUTPUT VALID RS- LEVEL - ICLXX IS ACTIVE INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR INVALID LEVEL - POWERDOWN OCCURS AFTER 0ms INDETERMINATE - POWERDOWN MAY OR MAY NOT OCCUR VALID RS- LEVEL - ICLXX IS ACTIVE 0 V 0 t INVL AUTOPWDN t INVH FIGURE 7. AUTOMATIC POWERDOWN AND INVALID TIMING DIAGRAMS INVALID } REGION PWR UP The time to recover from automatic powerdown mode is typically 0 s. Receiver ENABLE Control (ICL/// Only) Several devices also feature an EN input to control the receiver outputs. Driving EN high disables all the inverting (standard) receiver outputs placing them in a high impedance state. This is useful to eliminate supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down ( = ) peripheral (See Figure ). The enable input has no effect on transmitter nor monitor (R OUTB ) outputs. Capacitor Selection The charge pumps require capacitors for.v operation. For other supply voltages refer to Table for capacitor values. Do not use values smaller than those listed in Table. Increasing the capacitor values (by a factor of ) reduces ripple on the transmitter outputs and slightly reduces power consumption. C, C, and C can be increased without increasing C s value, however, do not increase C without also increasing C, C, and C to maintain the proper ratios (C to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor s equivalent series resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V and. TABLE. REQUIRED CAPACITOR VALUES (V) C ( F) Power Supply Decoupling In most circumstances a bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple to ground with a capacitor of the same value as the charge-pump capacitor C. Connect the bypass capacitor as close as possible to the IC. Operation Down to.7v ICLXX transmitter outputs meet RS- levels (.7V), at full data rate, with as low as.7v. RS- levels typically ensure interoperability with RS- devices. Transmitter Outputs when Exiting Powerdown C, C, C ( F).0 to to to Figure 8 shows the response of two transmitter outputs when exiting powerdown mode. As they activate, the two transmitter outputs properly go to opposite RS- levels, with no glitching, ringing, nor undesirable transients. Each transmitter is loaded with k in parallel with 00pF. Note that the transmitters enable only when the magnitude of the supplies exceed approximately V. FN80 Rev.00 Page of 8

13 V/DIV FORCEOFF T for a single transmitter driving 00pF and an RS- load at 0kbps. The static transmitters were also loaded with an RS- receiver. V/DIV =.V C - C = Mouse Driveability TIME (0 s/div) FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWERDOWN The ICLX have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure shows the transmitter output voltages under increasing load current. The on-chip switching regulator ensures the transmitters will supply at least V during worst case conditions (ma for paralleled V transmitters, 7.mA for single transmitter). The Automatic Powerdown feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to. T V C CC V C C C- ICLXX C C C C- T IN T OUT R OUT R IN 00pF EN K SHDN OR FORCEOFF FIGURE. TRANSMITTER LOOPBACK TEST CIRCUIT V/DIV T IN TRANSMITTER OUTPUT VOLTAGE (V) V OUT =.0V T 0 V OUT - T - ICL/ - - T V OUT - V OUT LOAD CURRENT PER TRANSMITTER (ma) FIGURE. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, i.e., DOUBLE CURRENT AXIS FOR TOTAL V OUT CURRENT) High Data Rates The ICLXX maintain the RS- V minimum transmitter output voltages even at high data rates. Figure details a transmitter loopback test circuit, and Figure illustrates the loopback test result at kbps. For this test, all transmitters were simultaneously driving RS- loads in parallel with 00pF, at kbps. Figure shows the loopback results T OUT R OUT V/DIV. T IN T OUT R OUT =.V C - C = s/div FIGURE. LOOPBACK TEST AT kbps =.V C - C = s/div. FIGURE. LOOPBACK TEST AT 0kbps FN80 Rev.00 Page of 8

14 Interconnection with V and V Logic The ICLXX directly interface with V CMOS and TTL logic families. Nevertheless, with the ICLXX at.v, and the logic supply at V, AC, HC, and CD000 outputs can drive ICLXX inputs, but ICLXX outputs do not reach the minimum V IH for these logic families. See Table for more information. TABLE. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES SYSTEM POWER-SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) COMPATIBILITY.. Compatible with all CMOS families. Compatible with all TTL and CMOS logic families.. Compatible with ACT and HCT CMOS, and with TTL. ICLXX outputs are incompatible with AC, HC, and CD000 CMOS inputs. Typical Performance Curves VCC =.V, TA = C TRANSMITTER OUTPUT VOLTAGE (V) V OUT TRANSMITTER AT 0kbps OR TRANSMITTERS AT 0kbps V OUT - SLEW RATE (V/ s) 0 SLEW -SLEW LOAD CAPACITANCE (pf) LOAD CAPACITANCE (pf) FIGURE. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE FIGURE. SLEW RATE vs LOAD CAPACITANCE SUPPLY CURRENT (ma) ICL 0kbps kbps 0kbps SUPPLY CURRENT (ma) ICL - ICL 0kbps kbps 0kbps LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FN80 Rev.00 Page of 8

15 Typical Performance Curves VCC =.V, TA = C (Continued) SUPPLY CURRENT (ma) ICLX 0kbps 0 0 kbps 0 0kbps LOAD CAPACITANCE (pf) SUPPLY CURRENT (ma) ICLX ICL - ICL SUPPLY VOLTAGE (V) NO LOAD ALL OUTPUTS STATIC ICLX FIGURE 7. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR COUNT: ICL: 8 ICL: 8 ICL: 7 ICL: ICLX: PROCESS: Si Gate CMOS FN80 Rev.00 Page of 8

16 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN80. - Ordering Information Table on page. - Added Revision History. - Added About Intersil Verbiage. - Updated POD M.7 to latest revision changes are as follow: Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. - Updated POD M0.7 to most current version changes are as follow: Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. - Updated POD M8.7 to most current version changes are as follow: Convert to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. -Updated POD M8. to most current version change is as follows: Added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN80 Rev.00 Page of 8

17 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-8.. Symbols are defined in the MO Series Symbol List in Section. of Publication No... Dimensions A, A and L are measured with the package seated in JE- DEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.0 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.0 inch (0.mm).. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E8., E., E8., E8., E. will have a B dimension of inch (0.7 -.mm). -B- A 0.0 (0.) M C A A L B S A e C E C L e A C e B E. (JEDEC MS-00-BB ISSUE D) LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e 0.0 BSC. BSC - e A 0.00 BSC 7. BSC e B L N Rev. 0 / FN80 Rev.00 Page 7 of 8

18 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N N/ B D e D E NOTES:. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y.M-8.. Symbols are defined in the MO Series Symbol List in Section. of Publication No... Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.0 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.0 inch (0.mm).. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ ) for E8., E., E8., E8. may have a B dimension of inch (0.7 -.mm). -B- A 0.0 (0.) M C A A L B S A e C E C L e A C e B E8. (JEDEC MS-00-BC ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e 0.0 BSC. BSC - e A 0.00 BSC 7. BSC e B L N 8 8 Rev. /0 FN80 Rev.00 Page 8 of 8

19 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x C M. (JEDEC MS-0-AC ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 FN80 Rev.00 Page of 8

20 Package Outline Drawing M.7 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, / A.00 ±0. SEE DETAIL "X".0.0 ±0. PIN # I.D. MARK 0.0 C B A 8 0. B TOP VIEW END VIEW H REF C SEATING PLANE 0. C SIDE VIEW.0 MAX / M C B A / MIN 0. MAX DETAIL "X" GAUGE PLANE ±0. 0. (.) NOTES: (.) (0. TYP) (0. TYP) TYPICAL RECOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0. per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y.M-. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-. FN80 Rev.00 Page 0 of 8

21 Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition.. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. GAUGE PLANE A M L C M.0 (JEDEC MO-0-AC ISSUE B) LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N Rev. /0 FN80 Rev.00 Page of 8

22 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x C M. (JEDEC MS-0-AA ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 FN80 Rev.00 Page of 8

23 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x C M8. (JEDEC MS-0-AB ISSUE C) 8 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 FN80 Rev.00 Page of 8

24 Package Outline Drawing M0.7 0 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, /.0 ±0. A 0 SEE DETAIL "X".0.0 ±0. PIN # I.D. MARK 0.0 C B A 0. B TOP VIEW END VIEW H REF C SEATING PLANE 0. C / M C B A SIDE VIEW.0 MAX / MIN 0. MAX DETAIL "X" GAUGE PLANE ±0. 0. (.) NOTES: (.) (0. TYP) (0. TYP) TYPICAL RECOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0. per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y.M-. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-. FN80 Rev.00 Page of 8

25 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition.. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. A GAUGE PLANE 0.(0.00) A M L C M0.0 (JEDEC MO-0-AE ISSUE B) 0 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC H L N deg. 8 deg. 0 deg. 8 deg. Rev. /0 FN80 Rev.00 Page of 8

26 Package Outline Drawing M8.7 8 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, / A 8.70± 0. SEE DETAIL "X".0.0 ± 0. PIN # I.D. MARK 0.0 C B A 0. B TOP VIEW END VIEW.00 REF C SEATING PLANE 0. C H MAX M C B A MIN 0. MAX GAUGE PLANE ±0. 0. SIDE VIEW DETAIL "X" (.) NOTES:. Dimension does not include mold flash, protrusions or gate burrs. (.) Mold flash, protrusions or gate burrs shall not exceed 0. per side.. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side.. Dimensions are measured at datum plane H.. Dimensioning and tolerancing per ASME Y.M-.. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0. TYP) TYPICAL RECOMMENDED LAND PATTERN (0. TYP). 7. is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-. FN80 Rev.00 Page of 8

27 Shrink Small Outline Plastic Packages (SSOP) N INDEX AREA e D B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A 0.(0.00) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.mm (0.00 inch) total in excess of B dimension at maximum material condition.. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. GAUGE PLANE A M L C M8.0 (JEDEC MO-0-AH ISSUE B) 8 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N Rev. /0 FN80 Rev.00 Page 7 of 8

28 Small Outline Plastic Packages (SOIC) N INDEX AREA D e B 0.(0.0) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.0) M B A a 0.(0.00) L M h x o C M8. (JEDEC MS-0-AE ISSUE C) 8 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.0 BSC.7 BSC - H h L N o 8 o 0 o 8 o - Rev., / TYPICAL RECOMMENDED LAND PATTERN (.0mm) (.8mm) (.7mm TYP) (0.mm TYP) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number.. Dimensioning and tolerancing per ANSI Y.M-8.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.0 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only.. The lead width B, as measured 0.mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.0 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. Copyright Intersil Americas LLC -0. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO00 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN80 Rev.00 Page 8 of 8