DATASHEET ISL83204A. Features. Applications. Ordering Information. Pinout. 60V/2.5A Peak, High Frequency Full Bridge FET Driver

Transcription

1 DATASHEET ISL8324A V/2.5A Peak, High Frequency Full Bridge FET Driver FN6397 Rev.2. The ISL8324A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 2 lead plastic SOIC and DIP packages. The ISL8324A includes an input comparator used to facilitate the hysteresis and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the ISL8324A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies. ISL8324A can also drive medium voltage brush motors, and two ISL8324As can be used to drive high performance stepper motors, since the short minimum on-time can provide fine micro-stepping capability. Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load. Ordering Information PART NUMBER ISL8324AIPZ (Note) ISL8324AIBZ* (Note) PART MARKING TEMP RANGE ( C) PACKAGE ISL8324AIPZ -4 to Ld PDIP (Pb-Free) ISL8324AIBZ -4 to Ld SOIC (Pb-Free) PKG. DWG. # E2.3 M2.3 *Add -T suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. Features Drives N-Channel FET Full Bridge Including High Side Chop Capability Bootstrap Supply Max Voltage to 75VDC Drives pf Load at 1MHz in Free Air at + C with Rise and Fall Times of Typically ns User-Programmable Dead Time Charge-Pump and Bootstrap Maintain Upper Bias Supplies DIS (Disable) Pin Pulls Gates Low Input Logic Thresholds Compatible with 5V to 15V Logic Levels Very Low Power Consumption Undervoltage Protection Pb-Free Plus Anneal Available (RoHS Compliant) Applications Medium/Large Voice Coil Motors Full Bridge Power Supplies Switching Power Amplifiers Uninterruptible Power Supplies High Performance Motor Controls Noise Cancellation Systems Battery Powered Vehicles Pinout ISL8324A (2 LD PDIP, 2 LD SOIC) TOP VIEW BHB 1 2 BHO HEN 2 19 BHS DIS 3 18 BLO V SS OUT IN+ IN- HDEL LDEL AHB BLS 16 V DD 15 V CC 14 ALS 13 ALO 12 AHS 11 AHO FN6397 Rev.2. Page 1 of 15

2 Application Block Diagram V 12V BHO BHS HEN BLO DIS ISL8324A LOAD IN+ IN- ALO AHS AHO GND GND Functional Block Diagram (1/2 ISL8324A) AHB HIGH VOLTAGE BUS VDC UNDER- VOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER 11 AHO C BS V DD AHS HEN 2 TURN-ON DELAY DIS 3 15 V CC D BS TO V DD (PIN 16) OUT IN+ IN _ TURN-ON DELAY DRIVER ALO ALS C BF +12VDC BIAS SUPPLY HDEL 8 LDEL 9 V SS 4 FN6397 Rev.2. Page 2 of 15

3 Typical Application (Hysteresis Mode Switching) V 12V DIS 1 BHB 2 HEN 3 DIS BHO BHS BLO LOAD 6V IN V SS OUT IN+ IN- ISL8324A BLS V DD V CC ALS HDEL ALO V 9 LDEL AHS 12 AHB AHO 11 GND - + 6V GND FN6397 Rev.2. Page 3 of 15

4 Absolute Maximum Ratings Supply Voltage, V DD and V CC V to 16V Logic I/O Voltages V to V DD +.3V Voltage on AHS, BHS. -6.V (Transient) to 7V (+25 C to +125 C) Voltage on AHS, BHS.. -6.V (Transient) to 7V (-55 C to +125 C) Voltage on ALS, BLS V (Transient) to +2.V (Transient) Voltage on AHB, BHB V AHS, BHS -.3V to V AHS, BHS +V DD Voltage on ALO, BLO V ALS, BLS -.3V to V CC +.3V Voltage on AHO, BHO V AHS, BHS -.3V to V AHB, BHB +.3V Input Current, HDEL and LDEL mA to ma Phase Slew Rate V/ns All Voltages relative to V SS, unless otherwise specified. Thermal Information Thermal Resistance (Typical, Note 1) JA ( C/W) SOIC Package PDIP Package Maximum Power Dissipation at +85 C SOIC Package mW PDIP Package mW Storage Temperature Range C to +1 C Operating Max. Junction Temperature C Lead Temperature (Soldering s) C (For SOIC - Lead Tips Only) Operating Conditions Supply Voltage, V DD and V CC V to +15V Voltage on ALS, BLS V to +1.V Voltage on AHB, BHB V AHS, BHS +5V to V AHS, BHS +15V Voltage on AHs, BHS V Input Current, HDEL and LDEL A to - A Operating Ambient Temperature Range C to +85 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = k, and T A = +25 C, Unless Otherwise Specified T J = +25 C T J = -4 C to +125 C PARAMETERS SYMBOL TEST CONDITIONS SUPPLY CURRENTS AND CHARGE PUMPS MIN TYP MAX MIN MAX UNITS V DD Quiescent Current I DD IN- = 2.5V, Other Inputs = V ma V DD Operating Current I DDO Outputs switching f = khz, No Load V CC Quiescent Current I CC IN- = 2.5V, Other Inputs = V, I ALO = I BLO = ma A V CC Operating Current I CCO f = khz, No Load ma AHB, BHB Quiescent Current -Qpump Output Current I AHB, I BHB IN- = 2.5V, Other Inputs = V, I AHO =I BHO =, V DD = V CC =V AHB = V BHB = V A AHB, BHB Operating Current I AHBO, f = khz, No Load ma I BHBO AHS, BHS, AHB, BHB Leakage Current I HLK V BHS = V AHS = V, V AHB = V BHB = 75V A AHB-AHS, BHB-BHS Qpump Output Voltage V AHB - V AHS I AHB = I AHB =, No Load V V BHB - V BHS INPUT COMPARATOR PINS: IN+, IN-, OUT Offset Voltage V OS Over Common Mode Voltage Range mv Input Bias Current I IB A Input Offset Current I OS A Input Common Mode Voltage Range CMVR 1 - V DD V DD -1.5 V FN6397 Rev.2. Page 4 of 15

5 Electrical Specifications V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = k, and T A = +25 C, Unless Otherwise Specified (Continued) T J = +25 C T J = -4 C to +125 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Voltage Gain AVOL V/mV OUT High Level Output Voltage OUT Low Level Output Voltage V OH IN+ >IN-, I OH = -2 A V DD V DD V V OL IN+ <IN-, I OL = +2 A V Low Level Output Current I OL V OUT = 6V ma High Level Output Current I OH V OUT = 6V ma INPUT PINS: DIS Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = V, Full Operating Conditions A High Level Input Current I IH V IN = 5V, Full Operating Conditions A INPUT PINS: HEN Low Level Input Voltage V IL Full Operating Conditions V High Level Input Voltage V IH Full Operating Conditions V Input Voltage Hysteresis mv Low Level Input Current I IL V IN = V, Full Operating Conditions A High Level Input Current I IH V IN = 5V, Full Operating Conditions A TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V HDEL, V I HDEL = I LDEL = - A V GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage V OL I OUT = ma V High Level Output Voltage V CC - V OH I OUT = -ma V Peak Pullup Current I O + V OUT = V A Peak Pulldown Current I O - V OUT = 12V A Under Voltage, Rising Threshold Under Voltage, Falling Threshold UV V UV V Under Voltage, Hysteresis HYS V FN6397 Rev.2. Page 5 of 15

6 Switching Specifications V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = k, C L = pf, and T A = +25 C, Unless Otherwise Specified T J = +25 C T J = - 4 C to +125 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) t LPHL ns Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) t HPHL ns Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) t LPLH ns Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) t HPLH ns Rise Time t R ns Fall Time t F ns Turn-on Input Pulse Width t PWIN-ON ns Turn-off Input Pulse Width t PWIN-OFF ns Disable Turn-off Propagation Delay (DIS - Lower Outputs) Disable Turn-off Propagation Delay (DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) t DISLOW ns t DISHIGH ns t DLPLH ns Refresh Pulse Width (ALO and BLO) t REF-PW ns Disable to Upper Enable (DIS - AHO and BHO) t UEN ns HEN-AHO, BHO Turn-off, Propagation Delay t HEN-PHL R HDEL = R LDEL = k ns HEN-AHO, BHO Turn-on, Propagation Delay t HEN-PLH R HDEL = R LDEL = k ns TRUTH TABLE INPUT OUTPUT IN+ >IN- HEN U/V DIS ALO AHO BLO BHO X X X X X 1 X FN6397 Rev.2. Page 6 of 15

7 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 3 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers (Pins 11 and 2) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of V to 15V (no greater than V DD ). 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of V to 15V (no greater than V DD ). 4 V SS Chip negative supply, generally will be ground. 5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis. 6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9). 7 IN- Inverting input of control comparator. See IN+ (Pin 6) description. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V SS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 3 A out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 V CC Positive supply to gate drivers. Must be same potential as V DD (Pin 16). Connect to anodes of two bootstrap diodes. 16 V DD Positive supply to lower gate drivers. Must be same potential as V CC (Pin 15). De-couple this pin to V SS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 2 BHO B High-side Output. Connect to gate of B High-side power MOSFET. FN6397 Rev.2. Page 7 of 15

8 Timing Diagrams t DT U/V = DIS HEN 1 t HPHL t LPLH IN+ > IN- ALO AHO BLO BHO t t HPLH LPHL t t R t DT F (% - 9%) (9% - %) FIGURE 1. BI-STATE MODE t HEN-PHL t HEN-PLH U/V = DIS HEN IN+ > IN- ALO AHO BLO BHO FIGURE 2. HIGH SIDE CHOP MODE t DLPLH t DIS t REF-PW U/V or DIS HEN IN+ > IN- ALO AHO BLO BHO t UEN FIGURE 3. DISABLE FUNCTION FN6397 Rev.2. Page 8 of 15

9 Typical Performance Curves V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = k, and T A = +25 C, Unless Otherwise Specified I DD SUPPLY CURRENT (ma) I DD SUPPLY CURRENT (ma) V DD SUPPLY VOLTAGE (V). 2k 4k k 8k 1M SWITCHING FREQUENCY (Hz) FIGURE 4. QUIESCENT I DD SUPPLY CURRENT vs V DD SUPPLY VOLTAGE FIGURE 5. I DDO NO-LOAD I DD SUPPLY CURRENT vs FREQUENCY (Hz) C FLOATING SUPPLY BIAS CURRENT (ma) k 2k 3k 4k k k 7k 8k 9k 1M I CC SUPPLY CURRENT (ma) C +25 C C -4 C k 2k 3k 4k k k 7k 8k 9k 1M SWITCHING FREQUENCY (Hz) SWITCHING FREQUENCY (Hz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = pf) FIGURE 7. I CCO, NO-LOAD I CC SUPPLY CURRENT vs FREQUENCY (Hz) TEMPERATURE FLOATING SUPPLY BIAS CURRENT (ma) COMPARATOR INPUT CURRENT ( A) k 4k k 8k 1M SWITCHING FREQUENCY (Hz) FIGURE 8. I AHB, I BHB NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY FIGURE 9. COMPARATOR INPUT CURRENT I L vs TEMPERATURE AT V CM = 5V FN6397 Rev.2. Page 9 of 15

10 Typical Performance Curves V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = k, and T A = +25 C, Unless Otherwise Specified. (Continued) LOW LEVEL INPUT CURRENT ( A) - -1 LOW LEVEL INPUT CURRENT ( A) FIGURE. DIS LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE FIGURE 11. HEN LOW LEVEL INPUT CURRENT I IL vs TEMPERATURE FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION DELAY t DISHIGH vs TEMPERATURE FIGURE 14. DISABLE TO UPPER ENABLE t UEN PROPAGATION DELAY vs TEMPERATURE FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION DELAY t DISLOW vs TEMPERATURE FN6397 Rev.2. Page of 15

11 Typical Performance Curves V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = k, and T A = +25 C, Unless Otherwise Specified. (Continued) 4 8 REFRESH PULSE WIDTH (ns) FIGURE 16. tt REF-PW REFRESH PULSE WIDTH vs TEMPERATURE 2 FIGURE 17. DISABLE TO LOWER ENABLE t DLPLH PROPAGATION DELAY vs TEMPERATURE FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY t HPHL vs TEMPERATURE FIGURE 19. UPPER TURN-ON PROPAGATION DELAY t HPLH vs TEMPERATURE FIGURE 2. LOWER TURN-OFF PROPAGATION DELAY t LPHL vs TEMPERATURE FIGURE 21. LOWER TURN-ON PROPAGATION DELAY t LPLH vs TEMPERATURE FN6397 Rev.2. Page 11 of 15

12 Typical Performance Curves V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = K, and T A = +25 C, Unless Otherwise Specified GATE DRIVE FALL TIME (ns) TURN-ON RISE TIME (ns) FIGURE 22. GATE DRIVE FALL TIME t F vs TEMPERATURE 8.5 FIGURE 23. GATE DRIVE RISE TIME t R vs TEMPERATURE 6. HDEL, LDEL INPUT VOLTAGE (V) V CC - V OH (mv) C C +25 C +75 C 4. FIGURE 24. V LDEL, V HDEL VOLTAGE vs TEMPERATURE +125 C BIAS SUPPLY VOLTAGE (V) FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, V CC - V OH vs BIAS SUPPLY AND TEMPERATURE AT A 3.5 V OL (mv) C C +25 C +75 C GATE DRIVE SINK CURRENT (A) C BIAS SUPPLY VOLTAGE (V) V CC, V DD, V AHG, V BHB (V) FIGURE 26. LOW LEVEL OUTPUT VOLTAGE V OL vs BIAS SUPPLY AND TEMPERATURE AT A FIGURE 27. PEAK PULLDOWN CURRENT I O- BIAS SUPPLY VOLTAGE FN6397 Rev.2. Page 12 of 15

13 Typical Performance Curves V DD = V CC = V AHB = V BHB = 12V, V SS = V ALS = V BLS = V AHS = V BHS = V, R HDEL = R LDEL = K, and T A = +25 C, Unless Otherwise Specified. (Continued) GATE DRIVE SINK CURRENT (A) V CC, V DD, V ABH, V BHB (V) FIGURE 28. PEAK PULLUP CURRENT I O+ vs SUPPLY VOLTAGE LOW VOLTAGE BIAS CURRENT (ma) , 3, 1, 1k 2k 5k k 2k k k 2k k 1M SWITCHING FREQUENCY (Hz) FIGURE 29. LOW VOLTAGE BIAS CURRENT I DD AND I CC (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 9. LEVEL-SHIFT CURRENT ( A) 2 2 BIAS SUPPLY VOLTAGE, V DD (V) UV+ UV- k 2k k k 2k k 1M SWITCHING FREQUENCY (Hz) FIGURE 3. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE TEMPERATURE ( C) FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE 1 12 DEAD-TIME (ns) HDEL/LDEL RESISTANCE (k ) FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE FN6397 Rev.2. Page 13 of 15

14 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 -C- -A- N N/2 B D e D1 E1 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.25mm). 9. N is the maximum number of terminal positions.. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of inch ( mm). -B- A1. (.25) M C A A2 L B S A e C E C L e A C e B E2.3 (JEDEC MS-1-AD ISSUE D) 2 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e. BSC 2.54 BSC - e A.3 BSC 7.62 BSC 6 e B L N Rev. 12/93 FN6397 Rev.2. Page 14 of 15

15 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B.25(.) M C A M E -B- -A- -C- SEATING PLANE A B S H.25(.) M B NOTES: 1. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y14.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (. inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch). Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. A1.(.4) L M h x 45 C M2.3 (JEDEC MS-13-AC ISSUE C) 2 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e. BSC 1.27 BSC - H h L N Rev. 2 6/5 Copyright Intersil Americas LLC 27. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN6397 Rev.2. Page 15 of 15