DATASHEET HIP2101. Features. Ordering Information. Applications. 100V/2A Peak, Low Cost, High Frequency Half Bridge Driver

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1 DATASHEET P20 00V/2A Peak, Low Cost, High Frequency Half Bridge Driver FN9025 Rev 9.00 The P20 is a high frequency, 00V Half Bridge N-Channel power MOSFET driver IC. It is equivalent to the P200 with the added advantage of full TTL/CMOS compatible logic input pins. The low-side and high-side gate drivers are independently controlled and matched to 3ns. This gives users total control over dead-time for specific power circuit topologies. Undervoltage protection on both the low-side and high-side supplies force the outputs low. An on-chip diode eliminates the discrete diode required with other driver ICs. A new level-shifter topology yields the lowpower benefits of pulsed operation with the safety of DC operation. Unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. Ordering Information PART NUMBER P20IB (No longer available, recommended replacement: P20IBZ) TEMP. RANGE ( C) PACKAGE PKG. DWG. # -40 to 25 8 Ld SOIC M8.5 P20IBZ (Note ) -40 to 25 8 Ld SOIC (Pb-free) M8.5 P20EIB (No longer available, recommended replacement: P20EIBZ) P20EIBZ (Note ) -40 to 25 8 Ld EPSOIC M8.5C -40 to 25 8 Ld EPSOIC (Pb-free) P20IRZ (Note ) -40 to 25 6 Ld 5x5 QFN (Pb-free) P20IR4Z (Note ) -40 to 25 2 Ld 4x4 DFN (Pb-free) M8.5C L6.5x5 L2.4x4A NOTES:. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2. Add T suffix for Tape and Reel packing option. Features Drives N-Channel MOSFET Half Bridge SOIC, EPSOIC, QFN and DFN Package Options SOIC, EPSOIC and DFN Packages Compliant with 00V Conductor Spacing Guidelines of IPC-222 Pb-free Product Available (RoHS Compliant) Bootstrap Supply Max Voltage to 4VDC On-Chip Bootstrap Diode Fast Propagation Times for Multi-MHz Circuits Drives 000pF Load with Rise and Fall Times Typ. 0ns TTL/CMOS Input Thresholds Increase Flexibility Independent Inputs for Non-Half Bridge Topologies No Start-Up Problems Outputs Unaffected by Supply Glitches, HS Ringing Below Ground, or HS Slewing at High dv/dt Low Power Consumption Wide Supply Range Supply Undervoltage Protection 3 Output Driver Resistance QFN/DFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile Applications Telecom Half Bridge Power Supplies Avionics DC-DC Converters Two-Switch Forward Converters Active Clamp Forward Converters FN9025 Rev 9.00 Page of 3

2 Pinouts P20 (SOIC, EPSOIC) TOP VIEW P20IR4 (DFN) TOP VIEW P20 (QFN) TOP VIEW V DD HB HS EPAD V SS V DD HB EPAD V SS HB 2 3 V DD EPAD 2 0 V SS HS NOTE: EPAD = Exposed PAD. HS Application Block Diagram +2V +00V V DD HB SECONDARY CIRCUIT PWM CONTROLLER CONTROL DRIVE DRIVE HS P20 V SS REFEREE AND ISOLATION FN9025 Rev 9.00 Page 2 of 3

3 Functional Block Diagram HB V DD UNDER VOLTAGE LEVEL SFT DRIVER HS UNDER VOLTAGE DRIVER V SS EPAD (EPSOIC, QFN and DFN PACKAGES ONLY) *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. +48V +2V PWM P 20 SECONDARY CIRCUIT ISOLATION FIGURE. TWO-SWITCH FORWARD CONVERTER +48V +2V SECONDARY CIRCUIT PWM P 20 ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP FN9025 Rev 9.00 Page 3 of 3

4 Absolute Maximum Ratings Supply Voltage, V DD, V HB -V HS (Notes 3, 4) V to 8V and Voltages (Note 4) V to 7.0V Voltage on (Note 4) V to V DD +0.3V Voltage on (Note 4) V HS -0.3V to V HB +0.3V Voltage on HS (Continuous) (Note 4) V to 0V Voltage on HB (Note 4) V Average Current in V DD to HB diode mA ESD Classification Class (kv) Maximum Recommended Operating Conditions Supply Voltage, V DD V to 4.0VDC Voltage on HS V to 00V Voltage on HS (Repetitive Transient) -5V to 05V Voltage on HB.. V HS +8V to V HS +4.0V and V DD -V to V DD +00V HS Slew Rate <50V/ns Thermal Information Thermal Resistance (Typical) JA ( C/W) JC ( C/W) SOIC (Note 5) N/A EPSOIC (Note 6) QFN (Note 6) DFN (Note 6) Max Power Dissipation at 25 o C in Free Air (SOIC, Note 5).....3W Max Power Dissipation at 25 o C in Free Air (EPSOIC, Note 6).. 3.W Max Power Dissipation at 25 o C in Free Air (QFN, Note 6) W Storage Temperature Range C to 50 C Junction Temperature Range C to 50 C Lead Temperature (Soldering 0s - SOIC Lead Tips Only) C For Recommended soldering conditions see Tech Brief TB389. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied. NOTES: 3. The P20 is capable of derated operation at supply voltages exceeding 4V. Figure 6 shows the high-side voltage derating curve for this mode of operation. 4. All voltages referenced to V SS unless otherwise specified. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. JC, the case temp is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications V DD = V HB = 2V, V SS = V HS = 0V, No Load on or, Unless Otherwise Specified T J = 25 C T J = -40 C TO 25 C SUPPLY CURRENTS PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS V DD Quiescent Current I DD = = 0V ma V DD Operating Current I DDO f = 500kHz ma Total HB Quiescent Current I HB = = 0V ma Total HB Operating Current I HBO f = 500kHz ma HB to V SS Current, Quiescent I HBS V HS = V HB = 4V A HB to V SS Current, Operating I HBSO f = 500kHz ma INPUT PINS Low Level Input Voltage Threshold V IL V High Level Input Voltage Threshold V IH V Input Pulldown Resistance R I k UNDER VOLTAGE PROTECTION V DD Rising Threshold V DDR V V DD Threshold Hysteresis V DDH V HB Rising Threshold V HBR V HB Threshold Hysteresis V HBH V FN9025 Rev 9.00 Page 4 of 3

5 Electrical Specifications V DD = V HB = 2V, V SS = V HS = 0V, No Load on or, Unless Otherwise Specified (Continued) T J = 25 C T J = -40 C TO 25 C BOOT STRAP DIODE PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Low-Current Forward Voltage V DL I VDD-HB = 00 A V High-Current Forward Voltage V DH I VDD-HB = 00mA V Dynamic Resistance R D I VDD-HB = 00mA GATE DRIVER Low Level Output Voltage V OLL I = 00mA V High Level Output Voltage V OHL I = -00mA, V OHL = V DD -V V Peak Pullup Current I OHL V = 0V A Peak Pulldown Current I OLL V = 2V A GATE DRIVER Low Level Output Voltage V OLH I = 00mA V High Level Output Voltage V OHH I = -00mA, V OHH = V HB -V V Peak Pullup Current I OHH V = 0V A Peak Pulldown Current I OLH V = 2V A Switching Specifications V DD = V HB = 2V, V SS = V HS = 0V, No Load on or, Unless Otherwise Specified PARAMETERS SYMBOL TEST CONDITIONS T J = 25 C T J = -40 C TO 25 C MIN TYP MAX MIN MAX UNITS Lower Turn-Off Propagation Delay ( Falling to Falling) t LPHL ns Upper Turn-Off Propagation Delay ( Falling to Falling) t HPHL ns Lower Turn-On Propagation Delay ( Rising to Rising) t LPLH ns Upper Turn-On Propagation Delay ( Rising to Rising) t HPLH ns Delay Matching: Lower Turn-On and Upper Turn-Off t MON ns Delay Matching: Lower Turn-Off and Upper Turn-On t MOFF ns Either Output Rise/Fall Time t RC, t FC C L = 000pF ns Either Output Rise/Fall Time (3V to 9V) t R, t F C L = 0. F us Either Output Rise Time Driving DMOS t RD C L = IRFR ns Either Output Fall Time Driving DMOS t FD C L = IRFR ns Minimum Input Pulse Width that Changes the Output t PW ns Bootstrap Diode Turn-On or Turn-Off Time t BS ns FN9025 Rev 9.00 Page 5 of 3

6 Pin Descriptions SYMBOL V DD HB HS V SS EPAD DESCRIPTION Positive Supply to lower gate drivers. De-couple this pin to V SS. Bootstrap diode connected to HB. High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-Side Output. Connect to gate of High-Side power MOSFET. High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-Side input. Low-Side input. Chip negative supply, generally will be ground. Low-Side Output. Connect to gate of Low-Side power MOSFET. Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. Timing Diagrams, t HPLH, t LPLH t HPHL, t LPHL, t MON t MOFF FIGURE 3. FIGURE 4. Typical Performance Curves I DDO (ma) C C C C FREQUEY (khz) C, 25 C 25 C C FREQUEY (khz) FIGURE 5A. FIGURE 5B. FIGURE 5. OPERATING CURRENT vs FREQUEY I HBO (ma) FN9025 Rev 9.00 Page 6 of 3

7 Typical Performance Curves (Continued) V HB = V DD = 9V I HBSO (ma) 0. T = 50 C T = -40 C T = 25 C T = 25 C V OHL, V OHH (mv) V HB = V DD = 2V V HB = V DD = 4V FREQUEY (khz) FIGURE 6. HB TO VSS OPERATING CURRENT vs FREQUEY TEMPERATURE ( C) FIGURE 7. GH LEVEL OUTPUT VOLTAGE vs TEMPERATURE V OLL, V OLH (mv) V HB = V DD = 9V V HB = V DD = 2V V HB = V DD = 4V V HBR, V DDR (V) V DDR V HBR TEMPERATURE ( C) FIGURE 8. W LEVEL OUTPUT VOLTAGE vs TEMPERATURE TEMPERATURE ( C) FIGURE 9. UNDERVOLTAGE CKOUT THRESLD vs TEMPERATURE V HBH, V DDH (mv) V HBH V DDH t LPLH, t LPHL, t HPLH, t HPHL (ns) t HPHL t HPLH t LPHL t LPLH TEMPERATURE ( C) FIGURE 0. UNDERVOLTAGE CKOUT HYSTERESIS vs TEMPERATURE TEMPERATURE ( C) FIGURE. PROPAGATION DELAYS vs TEMPERATURE FN9025 Rev 9.00 Page 7 of 3

8 Typical Performance Curves (Continued) I, I (A).5.0 I, I (A) V, V (V) FIGURE 2. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE V, V (V) FIGURE 3. PEAK PULLDOWN CURRENT vs OUTPUT VOLTAGE FORWARD CURRENT (A) I DD, I HB ( A) I HB vs V HB I DD vs V DD FORWARD VOLTAGE (V) V DD, V HB (V) FIGURE 4. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 5. QUIESCENT CURRENT vs VOLTAGE VHS TO V SS VOLTAGE (V) V DD TO V SS VOLTAGE (V) FIGURE 6. VHS VOLTAGE vs V DD VOLTAGE FN9025 Rev 9.00 Page 8 of 3

9 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN Updated Ordering Information Table on page. - Added Revision History. - Added About Intersil Verbiage. - Updated POD L2.4X4A to latest revision changes are as follow: Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing. Added Typical Recommended Land Pattern. Bottom View changed "3.2 REF" TO "2.5 REF" Typical Recommended Land Pattern changed "3.80" to "3.75" From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). - Updated POD M8.5 to latest revision changes are as follow: Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern. Changed in Typical Recommended Land Pattern the following: 2.4(0.095) to 2.20(0.087) 0.76 (0.030) to 0.60(0.023) to 5.20(0.205) Changed Note "982" to "994" - Updated POD M8.5C to most current version. Removed "u" symbol from drawing (overlaps the "a" on Side View). About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN9025 Rev 9.00 Page 9 of 3

10 Package Outline Drawing L2.4x4A 2 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 3/5 A 4.00 PIN # INDEX AREA REF 0X 0.50 BSC B 6 2X PIN INDEX AREA TOP VIEW 0.5 (4X) M C A B 0.05 M C 4 2 X 0.25 BOTTOM VIEW ( 2.80 ) ( 2 X 0.65 ).00 MAX SEE DETAIL "X" 0.0 C BASE PLANE C ( 3.75) (.58) SIDE VIEW SEATING PLANE 0.08 C C 0. 2 REF ( 0X 0. 5 ) TYPICAL RECOMMENDED LAND PATTERN ( 2X 0. 25) DETAIL "X" MIN MAX. NOTES: Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y4.5m-994. Unless otherwise specified, tolerance : Decimal ± 0.05 Lead width applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. FN9025 Rev 9.00 Page 0 of 3

11 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L6.5x5 6 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPANT TO JEDEC MO-220VHHB ISSUE C) MILMETERS SYMBOL MIN NOMINAL MAX NOTES A A A A REF 9 b , 8 D 5.00 BSC - D 4.75 BSC 9 D , 8 E 5.00 BSC - E 4.75 BSC 9 E , 8 e 0.80 BSC - k L L N 6 2 Nd 4 3 Ne P Rev. 2 0/02 NOTES:. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. 6. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB Features and dimensions A2, A3, D, E, P & are present when Anvil singulation method is used and not present for saw singulation. 0. Depending on the method of lead termination at the edge of the package, a maximum 0.5mm pull back (L) maybe present. L minus L to be equal to or greater than 0.3mm. FN9025 Rev 9.00 Page of 3

12 Package Outline Drawing M8.5 8 LEAD NARROW BODY SMALL OUTNE PLASTIC PACKAGE Rev 4, /2 DETAIL "A".27 (0.050) 0.40 (0.06) INDEX AREA 4.00 (0.57) 3.80 (0.50) 6.20 (0.244) 5.80 (0.228) 0.50 (0.20) 0.25 (0.0) x TOP VIEW 8 0 SIDE VIEW B 0.25 (0.00) 0.9 (0.008) 2.20 (0.087) SEATING PLANE (0.97) 4.80 (0.89).75 (0.069).35 (0.053) (0.023).27 (0.050) 3 6 -C-.27 (0.050) 0.5(0.020) 0.33(0.03) 0.25(0.00) 0.0(0.004) (0.205) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y4.5M Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.00 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.024 inch). 7. Controlling dimension: MILMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-02-AA ISSUE C. FN9025 Rev 9.00 Page 2 of 3

13 Small Outline Exposed Pad Plastic Packages (EPSOIC) N INDEX AREA 2 3 e D B 0.25(0.00) M C A 2 3 N TOP VIEW SIDE VIEW P BOTTOM VIEW M E -B- -A- -C- SEATING PLANE P A B S H 0.25(0.00) M B A 0.0(0.004) L M h x 45 C M8.5C 8 LEAD NARROW BODY SMALL OUTNE EXPOSED PAD PLASTIC PACKAGE IHES MILMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e BSC.27 BSC - H h L N P P Rev. 6/05 NOTES:. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y4.5M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.006 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.00 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.36mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.6mm (0.024 inch). 0. Controlling dimension: MILMETER. Converted inch dimensions are not necessarily exact.. Dimensions P and P are thermal and/or electrical enhanced variations. Values shown are maximum size of exposed pad within lead count and body size. FN9025 Rev 9.00 Page 3 of 3