+5 V Powered RS-232/RS-422 Transceiver AD7306

Transcription

1 a FEATURES RS-3 and RS- on One Chip Single + V Supply. F Capacitors Short Circuit Protection Excellent Noise Immunity Low Power BiCMOS Technology High Speed, Low Skew RS- Operation C to + C Operations APPLICATIONS DTE-DCE Interface Packet Switching Local Area Networks Data Concentration Data Multiplexers Integrated Services Digital Network (ISDN) GENERAL DESCRIPTION The AD73 line driver/receiver is a V monolithic product which provides an interface between TTL signal levels and dual standard EIA RS-3/RS- signal levels. The part contains two RS-3 drivers, one RS- driver, one RS-3 receiver, and one receiver path which can be configured either as RS-3 or as RS-. An internal charge pump voltage converter facilitates operation from a single + V power supply. The internal charge pump generates ± V levels allowing RS-3 output levels to be developed without the need for external bipolar power supplies. A highly efficient charge pump design allows operation using non polarized, miniature. µf capacitors. This gives a considerable saving in printed circuit board space over conventional products which can use up to µf capacitors. The charge pump output voltages may also be used to power external circuitry which requires dual supplies. + V Powered RS-3/RS- Transceiver AD73 FUTIONAL BLOCK DIAGRAM V+ C+ C R IN T OUT T OUT V CC R IN (B) R IN /R IN (A) AD73 SOIC TOP VIEW (Not to Scale) = NO CONNECT The RS-3 channels are suitable for communications rates up to khz and the RS- channels are suitable for high speed communications up to MHz. The RS- transmitter complementary outputs are closely matched and feature low timing skew between the complementary outputs. This is often an essential requirement to meet tight system timing specifications. All inputs feature ESD protection, all driver outputs feature high source and sink current capability and are internally protected against short circuits on the outputs. An epitaxial layer is used to guard against latch-up. The part is available in a -lead SOIC and -pin plastic DIP package V C C+ R OUT T IN T IN R OUT 3/ SEL Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 AD73 SPECIFICATIONS (V CC = + V %, C = C = C3 = C =. F. All specifications T MIN to T MAX unless otherwise noted.) Parameter Min Typ Max Units Test Conditions/Comments RS-3 DRIVER TTL Input Logic Low, V INL. V TTL Input Logic High, V INH. V Input Logic Current. ± µa V IN = V to V CC RS-3 High Level Output Voltage. 7.3 V R L = 3 kω RS-3 Low Level Output Voltage.. V R L = 3 kω Output Short Circuit Current ± ± ma V OUT = V, T A = C to +7 C Slew Rate 3 V/µs C L = pf, R L = 3 kω V/µs C L = pf, R L = 3 kω Output Resistance (Powered Down) 3 M Ω V CC = V, V OUT = ±3 V RS-3 RECEIVER Input Voltage Range + V RS-3 Input Threshold Low..3 V RS-3 Input Threshold High.7. V RS-3 Input Hysteresis... V RS-3 Input Resistance 3 7 kω TTL Output Voltage Low, V OL.. V I OUT = + ma TTL Output Voltage High, V OH 3.. V I OUT = ma RS- DRIVER TTL Input Logic Low, V INL. V TTL Input Logic High, V INH. V Logic Input Current. ± µa V IN = V to V CC Differential Output Voltage. V V CC = V, R L Diff = ; Figure 3 V R L Diff = Ω; Figure 3 Common-Mode Output Voltage 3 V V OUT for Complementary O/P States. V R L Diff = Ω Output Short Circuit Current 3 ma V V CMR +7 V RS- RECEIVER Common-Mode Voltage Range ±7 V Typical RS- Input Voltage < V Differential Input Threshold Voltage. +. V Input Voltage Hysteresis 7 mv V CM = V Input Resistance 3 7 kω TTL Output Voltage Low, V OL.. V I OUT = +. ma TTL Output Voltage High, V OH 3.. V I OUT =. ma 3/ SEL Input Input Logic Low, V INL. V Input Logic High, V INH. V Logic Input Current. ± µa V IN = V to V CC POWER SUPPLY CURRENT I CC ma Outputs Unloaded CHARGE PUMP VOLTAGE GENERATOR V+ Output Voltage 9 V RS-3 Output Unloaded; See Typical Performance Curves V Output Voltage 9 V RS-3 Outputs Unloaded; See Typical Performance Curves Generator Rise Time µs Specifications subject to change without notice. REV. C

3 AD73 TIMING SPECIFICATIONS (V CC = + V %, C = C = C3 = C =. F. All specifications T MIN to T MAX unless otherwise noted.) Parameter Typ Max Units Test Conditions/Comments RS- Driver Propagation Delay Input to Output T PLH, T PHL 3 ns R L Diff = Ω. C L = C L = pf, Figures & RS- O/P to O/P T SKEW ns R L Diff = Ω. C L = C L = pf, Figures & Driver Rise/Fall Time T R, T F ns R L Diff = Ω. C L = C L = pf, Figures & RS- Receiver Propagation Delay Input to Output T PLH, T PHL 7 ns C L = pf. Figure RS-3/RS- Enable RS-3 Disable to RS- Enable T EN 7 ns Figure RS- Disable to RS-3 Enable T EN 7 ns Figure Transmission Rate (RS-) MHz RS-3 Receiver Propagation Delay Input to Output ns Transmission Rate (RS-3) khz C L = pf khz C L =. nf ABSOLUTE MAXIMUM RATINGS* (T A = + C unless otherwise noted) V CC V V (V CC.3 V) to +3. V V V to 3. V Inputs T IN, T IN V to V V to V+ R IN A/B, R IN V to + V 3/ SEL V to V+ Outputs T OUT, T OUT V to + V, (B) V to +7 V R OUT, R OUT V to (V CC +.3 V) Short Circuit Duration T OUT Continuous Power Dissipation Small Outline mw DIP mw Operating Temperature Range Commercial (J Version) C to +7 C Industrial (A Version) C to + C Storage Temperature Range C to + C Lead Temperature (Soldering, secs) C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods of time may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD73 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. C 3

4 AD73 SOIC DIP Pin Pin Mnemonic Function 9 V+, 3, C+, C 3 R IN T OUT T OUT 7 V CC 3 R IN (B) 9 R IN /R IN (A), 3,, 7, 3/ SEL 9 7 R OUT 9 T IN 3 T IN R OUT, 3, 7 C+, C V PIN FUTION DESCRIPTION Internally Generated Positive Supply (+9 V nominal). A. µf capacitor must be connected between this pin and. External Capacitor Terminals. A. µf capacitor must be connected between these pins. RS-3 Receiver R Input. This input accepts RS-3 input voltages. RS-3 Transmitter (Driver) T Output (Typically ±7. V). RS-3 Transmitter (Driver) T Output (Typically ±7. V). Power Supply Input ( V ± %). RS- Receiver R, Differential Input B. Receiver R Input. May be configured to accept either single ended RS-3 levels or differential RS- levels. It is configured using the 3/ SEL pin. RS- Transmitter (Driver) T3, Differential Output B. RS- Transmitter (Driver) T3, Differential Output A. No Connect Pins. Ground Pin. Must be connected to V. Select Input. This input configures Receiver R to accept either RS-3 or RS- signal levels. A Logic on this input selects 3 operation while a Logic selects operation. TTL/CMOS Input to the RS- Transmitter T3. TTL/CMOS Output from Receiver R. TTL/CMOS Input to RS-3 Transmitter T. TTL/CMOS Input to RS-3 Transmitter T. TTL/CMOS Output from Receiver R. External Capacitor Terminals. A. µf capacitor must be connected between these pins. Internally Generated Negative Supply ( 9 V nominal). A. µf capacitor must be connected between this pin and. PIN CONFIGURATIONS SOIC DIP V+ V T OUT T OUT C+ 3 C V CC 3 R IN C 3 C+ R IN (B) 3 C R IN R OUT R IN /R IN (A) T OUT T OUT V CC R IN (B) 7 AD73 SOIC TOP VIEW (Not to Scale) 9 7 T IN T IN R OUT 3/ SEL 7 AD73 DIP TOP VIEW (Not to Scale) 9 7 C+ V+ V C R IN /R IN (A) 9 9 3/ SEL R OUT C+ R OUT 3 T IN 3 T IN = NO CONNECT = NO CONNECT REV. C

5 AD73 +V INPUT 3V.V.V 7 V V CC C+ ±V V+ 3 C POWER SUPPLY C+ V 3 GENERATOR C VO / VO t PLH t PHL TTL/CMOS INPUTS TTL/CMOS OUTPUTS T IN T IN R OUT R OUT 3/ SEL T 9 T 7 R T3 AD73 R 9 T OUT T OUT R IN R IN (B) RS-3 OUTPUTS RS-3 INPUT R IN /R IN (A) RS- OUTPUT RS- INPUT RS-3/ RS- INPUT VO V VO 9% POINT % POINT t SKEW t R t SKEW 9% POINT t F % POINT Figure. RS- Driver. Propagation Delay Rise/Fall Timing DIFFERENTIAL INPUT R IN (B) - R IN (A).V.V V t PHL V t PLH V OH Figure. AD73 Application Circuit R OUT V OL Figure. RS- Receiver Timing C L = pf T3 RL DIFF = Ω C L = pf 3/ SEL.V.V Figure. RS- Driver. Propagation Delay Test Circuit t EN V OH t EN V OH R OUT V OL V OL T3 V OD RL DIFF RS-3 RS- RS-3 Figure. RS-3/RS- Receiver Enable Timing Figure 3. RS- Driver. Voltage Measurement Test Circuit REV. C

6 AD73 GENERAL DESCRIPTION The AD73 drivers/receivers provide an interface which is compatible with RS-3/RS- standard interfaces. As both standards are widely accepted it is often necessary to provide an interface which is compatible with both. The AD73 is ideally suited to this type of application as both standards may be met using a single package. This part contains two RS-3 drivers, one RS- driver, one RS-3 receiver, and one receiver path which can be configured as either RS-3 or RS-. This receiver is configured using the 3/ SEL pin. This part also contains an internal charge pump voltage converter which facilitates operation using a single + V power supply. Charge Pump DC-DC Voltage Generator The charge pump voltage generator uses a switched capacitor technique to develop ± V levels from an input + V supply. A highly efficient charge pump design coupled with a high frequency internal oscillator permit operation using four. µf capacitors. +V INPUT SUPPLY V+ ±V V CC POWER SUPPLY GENERATOR V C+ C C+ C C C C3 C Figure 7. Charge Pump Voltage Generator +V OUTPUT V OUTPUT Capacitors C and C act as charge storage capacitors while C3 and C provide output smoothing. For correct operation all four capacitors must be included. Either polarized or nonpolarized capacitors may be used for C C. If a polarized type is used, then the correct polarity should be observed. This may be ignored with nonpolarized type capacitors. The charge pump output voltages, V+ and V, are used internally to power the RS-3 transmitters. This permits RS-3 output levels to be developed on the RS-3 transmitter outputs. The charge pump output voltages may also be used to power external circuitry if the current requirements are small. Please refer to the Typical Performance Characteristics. The generator rise time after power up is µs typical. This time is necessary to completely charge the storage capacitors in the charge pump. Therefore, RS-3 data transmission should not be initiated until this time has elapsed after switch on. This will ensure that valid data is always transmitted. RS-3 Drivers The RS-3 drivers in the AD73 meet the EIA RS-3 specifications. The drivers are inverting level shifters which convert TTL/CMOS levels into RS-3 output levels. The input switching threshold is typically.3 V. With a typical RS-3 load, the output levels are ±7. V. Under worst case load conditions, the drivers are guaranteed to provide ± V which meets the minimum RS-3 requirement. The output slew rate is internally limited to <3 V/µs without the need for an external slew limiting capacitor. Short circuit protection is also provided which prevents damage in the event of output fault conditions. Active current limiting is used which limits the output short circuit current to less than ma in the event of an output fault. This type of current limiting does not degrade the output voltage swing under normal loading conditions as would be the case with conventional passive limiting. The powered-down output impedance is typically MΩ. This is considerably larger than the 3 Ω minimum value required by the RS-3 specification. It provides additional protection under fault conditions where another powered-up transmitter output is inadvertently shorted to the powered-down device. RS-3 Receivers The receivers are inverting level shifters which accept RS-3 input levels (±3 V to ± V) and translates them into V TTL/CMOS levels. The input switching thresholds are. V minimum and. V maximum which are well within the RS-3 requirement of ±3 V. Internal kω pull-down resistors to are provided on the receiver inputs. This ensures that an unconnected input will be interpreted as a low level giving a Logic on the TTL/CMOS output. Excellent noise immunity is achieved by the use of hysteresis and internal filtering circuitry. The filter rejects noise glitches of up to. µs in duration. RS- Driver The RS- driver on the AD73 accepts a TTL/CMOS input and translates it into a differential RS- level signal. The input switching threshold is typically.3 V. The unloaded output differential voltage is typically ± V (see Typical Performance Characteristics). Short circuit protection is provided on the output which limits the current to less than ma. RS- Receiver The RS- receiver on the AD73 accepts a differential input signal and translates it into a TTL/CMOS output level. The input resistance on both differential inputs is kω typical. With the receiver inputs unconnected (floating), internal biasing ensures that the receiver output is a Logic. Excellent noise immunity and high transmission speed is achieved using the differential configuration. REV. C

7 Typical Performance Characteristics AD73 VOLTAGE OUTPUT ± V V+ V- V CC = V T + C OUTPUT CURRENT ± ma 3 RS-3 TRANSMITTER OUTPUT VOLTAGE ±V V CURRENT E +V CURRENT E RS-3 TRANSMITTER OUTPUT CURRENT ma Figure. V+ and V Voltage vs. Current Figure. RS-3 Driver Output Voltage vs. Current SLEW RATE V/µs V E +V E DIFFERENTIAL O/P VOLTAGE V 3 V =.7V CC V =.V CC V =.V CC LOAD CAPACITAE pf 3 DIFFERENTIAL O/P CURRENT ma Figure 9. RS-3 Driver Slew Rate vs. Load Capacitance Figure. RS- Driver Output Current vs. Output Voltage A - 37 V A3 V 9 9 % % V V µs V V ns Figure. RS-3 Driver; R L = kω, C L = pf Figure 3. RS- Driver; R LDIFF = Ω, C L = C L = pf REV. C 7

8 AD73 Single-Ended Data Transmission Single-ended interfaces are used for low speed, short distance communications such as from a computer terminal to a printer. A single line is used to carry the signal. Various standards have been developed to standardize the communication link, the most popular of these being the RS-3. The RS-3 standard was introduced in 9 by the EIA and has been widely used throughout the industry. The standard has been revised several times, and the current revision is known as EIA-3E. The RS-3 standard is suitable for single-ended data transmission at relatively slow data rates over short distances. A typical RS-3 interface is shown in Figure. Differential Data Transmission When transmitting at high data rates, over long distances and through noisy environments, single-ended data transmission is often inadequate. In this type of application, differential data transmission offers superior performance. Differential transmission uses two signal lines to transmit data. It rejects ground shifts and is insensitive to noise signals which appear as common mode voltages on the transmission lines. To accommodate faster data communication, the differential RS- standard was developed. Therefore, it can be used to reliably transmit data at higher speeds and over longer distances than single-ended transmission. A typical RS- interface is shown in Figure. DATA IN TX RS-3 CHANNEL RX DATA OUT DATA IN TX RS- CHANNEL RX DATA OUT Figure. Single-Ended RS-3 Interface Figure. Differential RS- Interface Table I. Comparison of RS-3 and RS- Interface Standards Specification EIA-3E RS- Transmission Type Single-Ended Differential Maximum Data Rate kb/s MB/s Maximum Cable Length Load Dependent ft. Minimum Driver Output Voltage ± V ±. V Slew Rate 3 V/µs max Receiver Input Resistance 3 kω to 7 kω kω min Receiver Input Sensitivity ±3 V ± mv Receiver Input Voltage Range ± V ±7 V No. of Drivers per Line No. of Receivers per Line REV. C

9 Data Sheet AD73 OUTLINE DIMENSIONS. (.). (.9) 3 7. (.99) 7. (.93). (.93). (.3937).3 (.). (.39) COPLANARITY. (.3).3 (.9)..7 (.). (.) SEATING.33 (.3) BSC PLANE.3 (.). (.79).7 (.9). (.9).7 (.). (.7) COMPLIANT TO JEDEC STANDARDS MS-3-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; IH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. -Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-) Dimensions shown in millimeters and (inches) -9--A. (3.). (3.7).3 (3.). (.33) MAX. (3.).3 (3.3). (.9). (.). (.). (.3). (.) BSC.7 (.7). (.). (.) 3. (7.). (.3). (.). (.3) MIN SEATING PLANE. (.3) MIN. (.) MAX. (.3) GAUGE PLANE.3 (.).3 (7.7).3 (7.).3 (.9) MAX.9 (.9).3 (3.3). (.9). (.3). (.). (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN IHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF IH EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 7. -Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N--) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model Temperature Range Package Description Package Option AD73ANZ C to + C -Lead Plastic Dual In-Line Package [PDIP] N-- AD73AR C to + C -Lead Standard Small Outline Package [SOIC_W] RW- AD73ARZ C to + C -Lead Standard Small Outline Package [SOIC_W] RW- AD73JNZ C to +7 C -Lead Plastic Dual In-Line Package [PDIP] N-- AD73JRZ C to +7 C -Lead Standard Small Outline Package [SOIC_W] RW- AD73JRZ-REEL C to + C -Lead Standard Small Outline Package [SOIC_W] RW- 7-A 9

10 AD73 Data Sheet REVISION HISTORY /7 Rev. B to Rev. C Changes to Pin Function Description Table... Updated Outline Dimensions... 9 Moved Ordering Guide... 9 Changes to Ordering Guide Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D--/7(C)