DATASHEET ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E. Features. Applications. Related Literature

Transcription

1 DATASHEET ICL3E, ICL3E, ICL33E, ICL33E, ICL34E, ICL343E ±kv ESD Protected, 3V to.v, µa, 0kbps, RS-3 Transmitters/Receivers FN490 Rev 3.00 The ICL3E, ICL3E, ICL33E, ICL33E, ICL34E, and ICL343E are 3.0V to.v powered RS-3 transmitters/receivers which meet ElA/TIA-3 and V.8/V.4 specifications, even at = 3.0V. Additionally, they provide ±kv ESD protection (IEC Air Gap and Human Body Model) on transmitter outputs and receiver inputs (RS-3 pins). Targeted applications are notebook and laptop computers in which the low operational power consumption and even lower standby power consumption is critical. Efficient on-chip charge pumps, coupled with manual and automatic power-down functions (except for the ICL33E), reduce the standby supply current to a µa trickle. Small footprint packaging and the use of small, low value capacitors ensure board space savings. Data rates greater than 0kbps are ensured at worst case load conditions. This family is fully compatible with 3.3V-only systems, mixed 3.3V and.0v systems, and.0v-only systems. The ICL34XE are 3-driver, -receiver devices that provide a complete serial port suitable for laptop or notebook computers. Both devices also include noninverting always-active receivers for wake-up capability. The ICL3E, ICL33E, and ICL343E feature an automatic power-down function that powers down the on-chip power supply and driver circuits. Power-down occurs when an attached peripheral device is shut off or the RS-3 cable is removed, conserving system power automatically without changes to the hardware or operating system. These devices power up again when a valid RS-3 voltage is applied to any receiver input. Table summarizes the features of the devices represented by this datasheet, and AN983 summarizes the features of each device in the ICL3xxE 3V family. Features ESD protection for RS-3 I/O pins to ±kv (IEC000) Drop-in replacements for the MAX3E, MAX3E, MAX33E, MAX33E, MAX34E, MAX343E, and SP343E The ICL3E is a low-power, pin-compatible upgrade for the V MAXE The ICL3E is a low-power, pin-compatible upgrade for the V MAX4E and SP3E The ICL33E is a low-power upgrade for the HIN3E, ICL3, and pin-compatible competitor devices RS-3 compatible with =.7V Meets EIA/TIA-3 and V.8/V.4 specifications at 3V Latch-up free On-chip voltage converters require only four external capacitors at = 3.3V Manual and automatic power-down features Guaranteed mouse driveability (ICL34xE only) Receiver hysteresis for improved noise immunity Guaranteed minimum data rate: 0kbps Wide power supply range: single 3V to.v Low supply current in power-down state: µa Pb-free available (RoHS compliant) Applications Any system requiring RS-3 communication ports - Battery powered, hand-held, and portable equipment - Laptop computers and notebooks - Modems, printers, and other peripherals - Digital cameras - Cellular/mobile phones Related Literature For a full list of documents, visit our website: ICL3E, ICL3E, ICL33E, ICL33E, ICL34E, and ICL343E product information pages FN490 Rev 3.00 Page of 3

2 TABLE. SUMMARY OF FEATURES PART NUMBER NUMBER OF Tx NUMBER OF Rx NUMBER OF MONITOR RECEIVERS (R OUTB ) DATA RATE (kbps) RECEIVER ENABLE FUNCTION? READY OUTPUT? MANUAL POWER-DOWN? AUTOMATIC POWER-DOWN FUNCTION? ICL3E 0 0 Yes No Yes Yes ICL3E 0 0 Yes No Yes No ICL33E 0 0 Yes No Yes Yes ICL33E 0 0 No No No No ICL34E 3 0 Yes No Yes No ICL343E 3 0 No No Yes Yes FN490 Rev 3.00 Page of 3

3 Contents Typical Operating Circuits Pin Configurations Pin Descriptions Ordering Information Absolute Maximum Ratings Thermal Information Recommended Operating Conditions Electrical Specifications Detailed Description Charge-Pump Transmitters Receivers Low Power Operation Pin-Compatible Replacements for V Devices Power-Down Functionality (Except ICL33E) Software Controlled (Manual) Power-Down Automatic Power-Down (ICL3E, ICL33E, and ICL343E Only) Receiver ENABLE Control (ICL3E, ICL3E, ICL33E, and ICL34E Only) Capacitor Selection Power Supply Decoupling Operation Down to.7v Transmitter Outputs when Exiting Power-Down Mouse Driveability High Data Rates Interconnection with 3V and V Logic ±kv ESD Protection Human Body Model (HBM) Testing IEC Testing Typical Performance Curves Die Characteristics Revision History Package Outline Drawings FN490 Rev 3.00 Page 3 of 3

4 Typical Operating Circuits TTL/CMOS LOGIC LEVELS 3.3V C C 4 C C- C C- ICL3E V T 3 TIN R OUT 9 R V- kω C 3 (OPTIONAL CONNECTION, NOTE) C 3 C 4 T OUT R IN RS-3 LEVELS EN FORCEOFF FORCEON INVALID 0 TO POWER CONTROL LOGIC 4 NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR ICL3E C 3 (OPTIONAL CONNECTION, NOTE) 3.3V C C T IN C 4 C- C C- 7 T V V- 3 7 C 3 C 4 T OUT T IN T 8 T OUT TTL/CMOS LOGIC LEVELS R OUT 3 R kω 4 R IN RS-3 LEVELS R OUT 0 EN R kω 9 R IN SHDN 8 NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR FN490 Rev 3.00 Page 4 of 3

5 Typical Operating Circuits (Continued) ICL33E 3.3V C C T IN 4 3 C C- C C- 9 T V V C 3 C 4 T OUT T IN T 8 T OUT TTL/CMOS LOGIC LEVELS R OUT R kω R IN RS-3 LEVELS R OUT 0 EN R kω FORCEOFF 9 0 R IN 4 FORCEON INVALID 8 TO POWER CONTROL LOGIC ICL33E 3.3V C 3 (OPTIONAL CONNECTION, NOTE) C 3 C 4 T IN C C- C C- T V V- 4 C 3 C 4 T OUT TTL/CMOS LOGIC LEVELS T IN R OUT 0 T 7 3 T OUT R IN RS-3 LEVELS R kω R OUT 9 8 R IN R kω NOTE: THE NEGATIVE TERMINAL OF C3 CAN BE CONNECTED TO EITHER VCC OR FN490 Rev 3.00 Page of 3

6 Typical Operating Circuits (Continued) TTL/CMOS LOGIC LEVELS ICL34E R OUTB R OUT R OUT R3 OUT R4 OUT R OUT EN SHDN R R R 3 R 4 R kω kω kω kω kω 4 R IN R IN R3 IN 7 R4 IN 8 R IN RS-3 LEVELS 3.3V TTL/CMOS LOGIC LEVELS C C T IN T IN T3 IN R OUTB R OUT R OUT R3 OUT R4 OUT R OUT TO POWER CONTROL LOGIC ICL343E C 3.3V 8 7 C C V C 3 4 C- C 3 C V- C 4 C- T 4 9 T IN T OUT T 3 0 T IN RS-3 T OUT LEVELS T 3 T3 IN T3 OUT R OUTB C- C C- T V 7 C 3 C 4 T OUT T 3 0 T OUT T R R R 3 R 4 R FORCEON FORCEOFF INVALID V- kω kω kω kω kω T3 OUT R IN R IN R3 IN R4 IN R IN RS-3 LEVELS RS-3 LEVELS FN490 Rev 3.00 Page of 3

7 Pin Configurations ICL3E ( LD SSOP, TSSOP) TOP VIEW ICL3E (8 LD PDIP, SOIC) TOP VIEW EN FORCEOFF EN 8 SHDN C VCC C 7 VCC V 3 4 V 3 C- 4 3 TOUT C- 4 TOUT C FORCEON C 4 RIN C- TIN C- 3 ROUT V- 7 0 INVALID V- 7 TIN RIN 8 9 ROUT TOUT 8 TIN RIN 9 0 ROUT ICL3E (0 LD SSOP, TSSOP) TOP VIEW ICL33E (0 LD SSOP, TSSOP) TOP VIEW EN 0 SHDN EN 0 FORCEOFF C 9 VCC C 9 VCC V 3 8 V 3 8 C- 4 7 TOUT C- 4 7 TOUT C RIN C RIN C- ROUT C- ROUT V- 7 4 NC V- 7 4 FORCEON TOUT 8 3 TIN TOUT 8 3 TIN RIN ROUT 9 0 TIN NC RIN ROUT 9 0 TIN INVALID ICL33E ( LD SOIC, SSOP, TSSOP-) TOP VIEW ICL33E (0 LD TSSOP-0) TOP VIEW C VCC NC 0 NC V C 9 VCC C- 3 4 TOUT V 3 8 C 4 3 RIN C- 4 7 TOUT C- ROUT C RIN V- TIN C- ROUT TOUT 7 0 TIN V- 7 4 TIN RIN 8 9 ROUT TOUT RIN TIN ROUT NC 0 NC FN490 Rev 3.00 Page 7 of 3

8 Pin Configurations (Continued) ICL34E (8 LD SOIC, SSOP, TSSOP) TOP VIEW ICL343E (8 LD SOIC, SSOP, TSSOP) TOP VIEW C 8 C C 8 C C- 7 V C- 7 V V- 3 VCC V- 3 VCC RIN 4 RIN 4 RIN 4 C- RIN 4 C- R3IN 3 EN R3IN 3 FORCEON R4IN 7 SHDN R4IN 7 FORCEOFF RIN 8 ROUTB RIN 8 INVALID TOUT 9 0 ROUTB TOUT 9 0 ROUTB TOUT 0 9 ROUT TOUT 0 9 ROUT T3OUT 8 ROUT T3OUT 8 ROUT T3IN 7 R3OUT T3IN 7 R3OUT TIN 3 R4OUT TIN 3 R4OUT TIN 4 ROUT TIN 4 ROUT Pin Descriptions PIN FUNCTION VCC System power supply input (3.0V to.v) V Internally generated positive transmitter supply (.V) V- Internally generated negative transmitter supply (-.V) Ground connection C External capacitor (voltage doubler) is connected to this lead C- External capacitor (voltage doubler) is connected to this lead C External capacitor (voltage inverter) is connected to this lead C- External capacitor (voltage inverter) is connected to this lead TIN TOUT RIN ROUT ROUTB INVALID EN SHDN FORCEOFF FORCEON TTL/CMOS compatible transmitter inputs kv ESD protected, RS-3 level (nominally.v) transmitter outputs kv ESD protected, RS-3 compatible receiver inputs TTL/CMOS level receiver outputs TTL/CMOS level, noninverting, always enabled receiver outputs Active low output that indicates no valid RS-3 levels are present on any receiver input Active low receiver enable control; does not disable R OUTB outputs Active low input to shut down transmitters and on-board power supply to place device in low-power mode Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and FORCEON (see Table on page ) Active high input to override automatic power-down circuitry, which keeps transmitters active (FORCEOFF must be high) FN490 Rev 3.00 Page 8 of 3

9 Ordering Information PART NUMBER (Notes, 3) PART MARKING TEMP RANGE ( C) TAPE AND REEL (UNITS) (Note ) PACKAGE PKG. DWG. # ICL3ECAZ ICL3 ECAZ 0 to 70 - Ld SSOP (Pb-free) M.09 ICL3ECAZ-T ICL3 ECAZ 0 to 70 k Ld SSOP (Pb-free) M.09 ICL3ECAZ-T7A ICL3 ECAZ 0 to 70 0 Ld SSOP (Pb-free) M.09 ICL3EIAZ ICL3 EIAZ -40 to 8 - Ld SSOP (Pb-free) M.09 ICL3EIAZ-T ICL3 EIAZ -40 to 8 k Ld SSOP (Pb-free) M.09 ICL3EIAZ-T7A ICL3 EIAZ -40 to 8 0 Ld SSOP (Pb-free) M.09 ICL3EIVZ 3 EIVZ -40 to 8 - Ld TSSOP (Pb-free) M.73 ICL3EIVZ-T 3 EIVZ -40 to 8.k Ld TSSOP (Pb-free) M.73 ICL3EIVZ-T7A 3 EIVZ -40 to 8 0 Ld TSSOP (Pb-free) M.73 ICL3ECAZ ICL3 ECAZ 0 to 70-0 Ld SSOP (Pb-free) M0.09 ICL3ECAZ-T ICL3 ECAZ 0 to 70 k 0 Ld SSOP (Pb-free) M0.09 ICL3ECP (No longer available, no recommended replacement) ICL3ECP 0 to 70-8 Ld PDIP E8.3 ICL3ECVZ ICL3 ECVZ 0 to 70-0 Ld TSSOP (Pb-free) M0.73 ICL3ECVZ-T ICL3 ECVZ 0 to 70.k 0 Ld TSSOP (Pb-free) M0.73 ICL3EIAZ ICL3 EIAZ -40 to 8-0 Ld SSOP (Pb-free) M0.09 ICL3EIAZ-T ICL3 EIAZ -40 to 8 k 0 Ld SSOP (Pb-free) M0.09 ICL3EIBZ 3EIBZ -40 to 8-8 Ld SOIC (Pb-free) M8.3 ICL3EIBZ-T 3EIBZ -40 to 8 k 8 Ld SOIC (Pb-free) M8.3 ICL3EIVZ ICL3 EIVZ -40 to 8-0 Ld TSSOP (Pb-free) M0.73 ICL3EIVZ-T ICL3 EIVZ -40 to 8.k 0 Ld TSSOP (Pb-free) M0.73 ICL33ECAZ ICL3 3ECAZ 0 to 70-0 Ld SSOP (Pb-free) M0.09 ICL33ECAZ-T ICL3 3ECAZ 0 to 70 k 0 Ld SSOP (Pb-free) M0.09 ICL33ECVZ ICL3 3ECVZ 0 to 70-0 Ld TSSOP (Pb-free) M0.73 ICL33ECVZ-T ICL3 3ECVZ 0 to 70.k 0 Ld TSSOP (Pb-free) M0.73 ICL33EIAZ ICL3 3EIAZ -40 to 8-0 Ld SSOP (Pb-free) M0.09 ICL33EIAZ-T ICL3 3EIAZ -40 to 8 k 0 Ld SSOP (Pb-free) M0.09 ICL33EIVZ ICL3 3EIVZ -40 to 8-0 Ld TSSOP (Pb-free) M0.73 ICL33EIVZ-T ICL3 3EIVZ -40 to 8.k 0 Ld TSSOP (Pb-free) M0.73 ICL33ECAZ 33 ECAZ 0 to 70 - Ld SSOP (Pb-free) M.09 ICL33ECAZ-T 33 ECAZ 0 to 70 k Ld SSOP (Pb-free) M.09 ICL33ECAZ-T7A 33 ECAZ 0 to 70 0 Ld SSOP (Pb-free) M.09 ICL33ECBZ 33ECBZ 0 to 70 - Ld SOIC (Pb-free) M.3 ICL33ECBZ-T 33ECBZ 0 to 70 k Ld SOIC (Pb-free) M.3 ICL33ECBNZ 33ECBNZ 0 to 70 - Ld SOIC (Pb-free) M. ICL33ECBNZ-T 33ECBNZ 0 to 70.k Ld SOIC (Pb-free) M. ICL33ECV-Z 33E CV-Z 0 to 70 - Ld TSSOP (Pb-free) M.73 ICL33ECV-Z-T 33E CV-Z 0 to 70.k Ld TSSOP (Pb-free) M.73 FN490 Rev 3.00 Page 9 of 3

10 Ordering Information (Continued) PART NUMBER (Notes, 3) ICL33ECV-0Z (No longer available, recommended replacement: ICL33EIV-Z) ICL33ECV-0Z-T (No longer available, recommended replacement: ICL33EIV-Z-T) ICL33EFV-Z (No longer available, recommended replacement: ICL33EIV-Z) ICL33EFV-Z-T (No longer available, recommended replacement: ICL33EIV-Z-T) ICL33 ECV-0Z 0 to 70-0 Ld TSSOP (Pb-free) M0.73 ICL33 ECV-0Z 0 to 70.k 0 Ld TSSOP (Pb-free) M E FV-Z -40 to - Ld TSSOP (Pb-free) M.73 33E FV-Z -40 to.k Ld TSSOP (Pb-free) M.73 ICL33EIAZ 33 EIAZ -40 to 8 - Ld SSOP (Pb-free) M.09 ICL33EIAZ-T 33 EIAZ -40 to 8 k Ld SSOP (Pb-free) M.09 ICL33EIBZ 33EIBZ -40 to 8 - Ld SOIC (Pb-free) M.3 ICL33EIBZ-T 33EIBZ -40 to 8 k Ld SOIC (Pb-free) M.3 ICL33EIBNZ 33EIBNZ -40 to 8 - Ld SOIC (Pb-free) M. ICL33EIBNZ-T 33EIBNZ -40 to 8.k Ld SOIC (Pb-free) M. ICL33EIV-Z 33E IV-Z -40 to 8 - Ld TSSOP (Pb-free) M.73 ICL33EIV-Z-T 33E IV-Z -40 to 8.k Ld TSSOP (Pb-free) M.73 ICL33EIV-0Z ICL33 EIV-0Z -40 to 8-0 Ld TSSOP (Pb-free) M0.73 ICL33EIV-0Z-T ICL33 EIV-0Z -40 to 8.k 0 Ld TSSOP (Pb-free) M0.73 ICL34ECAZ ICL34 ECAZ 0 to 70-8 Ld SSOP (Pb-free) M8.09 ICL34ECAZ-T ICL34 ECAZ 0 to 70 k 8 Ld SSOP (Pb-free) M8.09 ICL34ECBZ (No longer available, recommended replacement: ICL34EIVZ) ICL34ECBZ-T (No longer available, recommended replacement: ICL34EIVZ) ICL34ECBZ 0 to 70-8 Ld SOIC (Pb-free) M8.3 ICL34ECBZ 0 to 70-8 Ld SOIC (Pb-free) M8.3 ICL34ECVZ ICL34 ECVZ 0 to 70-8 Ld TSSOP (Pb-free) M8.73 ICL34ECVZ-T ICL34 ECVZ 0 to 70.k 8 Ld TSSOP (Pb-free) M8.73 ICL34EIAZ ICL34 EIAZ -40 to 8-8 Ld SSOP (Pb-free) M8.09 ICL34EIAZ-T ICL34 EIAZ -40 to 8 k 8 Ld SSOP (Pb-free) M8.09 ICL34EIBZ (No longer available, recommended replacement: ICL34EIVZ) ICL34EIBZ-T (No longer available, recommended replacement: ICL34EIVZ) PART MARKING TEMP RANGE ( C) TAPE AND REEL (UNITS) (Note ) PACKAGE ICL34EIBZ -40 to 8-8 Ld SOIC (Pb-free) M8.3 ICL34EIBZ -40 to 8-8 Ld SOIC (Pb-free) M8.3 ICL34EIVZ ICL34 EIVZ -40 to 8-8 Ld TSSOP (Pb-free) M8.73 ICL34EIVZ-T ICL34 EIVZ -40 to 8.k 8 Ld TSSOP (Pb-free) M8.73 ICL343ECAZ ICL3 43ECAZ 0 to 70-8 Ld SSOP (Pb-free) M8.09 ICL343ECAZ-T ICL3 43ECAZ 0 to 70 k 8 Ld SSOP (Pb-free) M8.09 ICL343ECBZ ICL343ECBZ 0 to 70-8 Ld SOIC (Pb-free) M8.3 PKG. DWG. # FN490 Rev 3.00 Page 0 of 3

11 Ordering Information (Continued) PART NUMBER (Notes, 3) PART MARKING TEMP RANGE ( C) TAPE AND REEL (UNITS) (Note ) PACKAGE ICL343ECBZ-T ICL343ECBZ 0 to 70 k 8 Ld SOIC (Pb-free) M8.3 PKG. DWG. # ICL343ECVZ ICL343 ECVZ 0 to 70-8 Ld TSSOP (Pb-free) M8.73 ICL343ECVZ-T ICL343 ECVZ 0 to 70.k 8 Ld TSSOP (Pb-free) M8.73 ICL343EIAZ ICL3 43EIAZ -40 to 8-8 Ld SSOP (Pb-free) M8.09 ICL343EIAZ-T ICL3 43EIAZ -40 to 8 k 8 Ld SSOP (Pb-free) M8.09 ICL343EIVZ ICL343 EIVZ -40 to 8-8 Ld TSSOP (Pb-free) M8.73 ICL343EIVZ-T ICL343 EIVZ -40 to 8.k 8 Ld TSSOP (Pb-free) M8.73 ICL343EIVZ-T7A ICL343 EIVZ -40 to Ld TSSOP (Pb-free) M8.73 NOTES:. Refer to TB347 for details about reel specifications.. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 00% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD For Moisture Sensitivity Level (MSL), refer to the ICL3E, ICL3E, ICL33E, ICL33E, ICL34E, ICL343E product information pages. For more information about MSL, refer to TB33. FN490 Rev 3.00 Page of 3

12 Absolute Maximum Ratings to V to V V to V to 7V V- to V to -7V V to V V Input Voltages T IN, FORCEOFF, FORCEON, EN, SHDN V to V R IN ±8V Output Voltages T OUT ±3.V R OUT, INVALID V to 0.3V Short Circuit Duration T OUT Continuous ESD Rating See Electrical Specifications on page Recommended Operating Conditions Temperature Range ICL3xxECX C to 70 C ICL3xxEFX C to C ICL3xxEIX C to 8 C Supply Voltage ( ) V or V Rx Input Voltage V to V Thermal Information Thermal Resistance (Typical, Note 4) Θ JA ( C/W) 8 Ld PDIP Package Ld Wide SOIC Package Ld Narrow SOIC Package Ld SOIC Package Ld SOIC Package Ld SSOP Package Ld SSOP Package Ld TSSOP Package Ld TSSOP Package Ld SSOP and TSSOP Packages Maximum Junction Temperature (Plastic Package). 0 C Maximum Storage Temperature Range... - C to 0 C Pb-Free Reflow Profile see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. NOTE: 4. JA is measured with the component mounted on a low-effective thermal conductivity test board in free air. See TB379 for details. Electrical Specifications Test Conditions: = 3.0V to.v, C - C 4 = ; unless otherwise specified. Typicals are at T A = C. Boldface limits apply across the operating temperature range. PARAMETER DC CHARACTERISTICS TEST CONDITIONS TEMP ( C) MIN (Note ) TYP MAX (Note ) UNITS Supply Current, Automatic Power-Down All R IN Open, FORCEON =, FORCEOFF = (ICL3E, ICL33E, ICL343E Only) µa Supply Current, Power-Down Supply Current, Automatic Power-Down Disabled FORCEOFF = SHDN = (Except ICL33E) µa All Outputs Unloaded, FORCEON = FORCEOFF = SHDN = = 3.0V, ICL34, ICL ma = 3.0V, ICL ma = 3.V, ICL3, ICL3, ICL33, ICL ma LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS Input Logic Threshold Low T IN, FORCEON, FORCEOFF, EN, SHDN Full V Input Logic Threshold High Input Leakage Current T IN, FORCEON, FORCEOFF, EN, SHDN T IN, FORCEON, FORCEOFF, EN, SHDN = 3.3V Full V =.0V Full V All but ICL33EF Full µa ICL33EF Full µa Output Leakage Current (Except ICL33E) FORCEOFF = or EN = Full µa Output Voltage Low I OUT =.ma Full V Output Voltage High I OUT = -.0mA All but ICL33EF Full V ICL33EF Full V FN490 Rev 3.00 Page of 3

13 Electrical Specifications Test Conditions: = 3.0V to.v, C - C 4 = ; unless otherwise specified. Typicals are at T A = C. Boldface limits apply across the operating temperature range. (Continued) PARAMETER AUTOMATIC POWER-DOWN (ICL3E, ICL33E, ICL343E Only, FORCEON =, FORCEOFF = ) Receiver Input Thresholds to Enable Transmitters ICL3xxE Powers Up (see Figure on page 7) Full V Receiver Input Thresholds to Disable Transmitters INVALID Output Voltage Low INVALID Output Voltage High Receiver Threshold to Transmitters Enabled Delay (t WU ) Receiver Positive or Negative Threshold to INVALID High Delay (t INVH) Receiver Positive or Negative Threshold to INVALID Low Delay (t INVL) ICL3xxE Powers Down (see Figure on page 7) Full V I OUT =.ma Full V I OUT = -.0mA Full V µs - - µs µs RECEIVER INPUTS Input Voltage Range - - V Input Threshold Low = 3.3V V =.0V V Input Threshold High = 3.3V -..4 V =.0V V Input Hysteresis V Input Resistance 3 7 kω TRANSMITTER OUTPUTS Output Voltage Swing All Transmitter Outputs Loaded with 3kΩ to Ground Full V Output Resistance = V = V- = 0V, Transmitter Output = V Full 300 0M - Ω Output Short-Circuit Current Full ma Output Leakage Current MOUSE DRIVEABILITY (ICL34XE Only) Transmitter Output Voltage (see Figure 9 on page 9) V OUT = V, = 0V or 3V to.v, Automatic Power-Down or FORCEOFF = SHDN = T IN = T IN =, T3 IN =, T3 OUT Loaded with 3kΩ to, T OUT and T OUT Loaded with.ma Each TIMING CHARACTERISTICS Maximum Data Rate R L = 3kΩ, C L = 000pF, One Transmitter Switching Receiver Propagation Delay Receiver Output Enable Time Receiver Input to Receiver Output, C L = 0pF TEST CONDITIONS TEMP ( C) MIN (Note ) Full - - µa Full - - V Full kbps t PHL µs t PLH µs Normal Operation (Except ICL33E) ns TYP MAX (Note ) UNITS FN490 Rev 3.00 Page 3 of 3

14 Electrical Specifications Test Conditions: = 3.0V to.v, C - C 4 = ; unless otherwise specified. Typicals are at T A = C. Boldface limits apply across the operating temperature range. (Continued) PARAMETER Receiver Output Disable Time TEST CONDITIONS Normal Operation (Except ICL33E) ns Transmitter Skew t PHL to t PLH (Note ) ns Receiver Skew t PHL to t PLH ns Transition Region Slew Rate = 3.3V, C L = 0pF to 00pF 4-30 V/µs R L = 3kΩ to 7kΩ Measured from 3V to -3V or -3V to 3V C L = 0pF to 000pF - 30 V/µs ESD PERFORMANCE RS-3 Pins (TOUT, RIN) Human Body Model - - kv IEC Contact Discharge kv IEC Air Gap Discharge - - kv All Other Pins Human Body Model - - kv NOTES:. Transmitter skew is measured at the transmitter zero crossing points.. Parameters with MIN and/or MAX limits are 00% tested at C, unless otherwise specified. Temperature limits established by characterization and are not production tested. TEMP ( C) MIN (Note ) TYP MAX (Note ) UNITS Detailed Description The ICL3xxE interface ICs operate from a single 3V to.v supply, guarantee a 0kbps minimum data rate, require only four small external capacitors, feature low power consumption, and meet all ElA RS-3C and V.8 specifications. The circuit consists of three sections: the charge-pump, transmitters, and receivers. Charge-Pump The ICL3xxE family uses regulated on-chip dual charge-pumps as voltage doublers, and voltage inverters to generate ±.V transmitter supplies from a supply as low as 3.0V. This allows these devices to maintain RS-3 compliant output levels over the ±0% tolerance range of 3.3V powered systems. The efficient on-chip power supplies require only four small external capacitors for the voltage doubler and inverter functions at = 3.3V. See Capacitor Selection on page 8 and Table 3 on page 8 for capacitor recommendations for other operating conditions. The charge pumps operate discontinuously (they turn off as soon as the V and V- supplies are pumped up to the nominal values), resulting in significant power savings. Transmitters The transmitters are proprietary, low dropout, inverting drivers that translate TTL/CMOS inputs to EIA/TIA-3 output levels. Coupled with the on-chip ±.V supplies, these transmitters deliver true RS-3 levels across a wide range of single supply system voltages. Except for the ICL33E, all transmitter outputs disable and assume a high impedance state when the device enters the power-down mode (see Table on page ). These outputs can be driven to ±V when disabled. All devices operate at a 0kbps data rate for full load conditions (3kΩ and 000pF), 3.0V, with one transmitter operating at full speed. Under more typical conditions of 3.3V, R L = 3kΩ, and C L = 0pF, one transmitter easily operates at 900kbps. The transmitter inputs float if left unconnected, and can increase I CC. Connect unused inputs to for the best performance. Receivers All the ICL3xxE devices contain standard inverting receivers that three-state (except for the ICL33E) from the EN or FORCEOFF control lines. The two ICL34XE devices include noninverting (monitor) receivers (denoted by the ROUTB label) that are always active, regardless of the state of any control lines. All the receivers convert RS-3 signals to CMOS output levels and accept inputs up to ±V while presenting the required 3kΩ to 7kΩ input impedance (see Figure on page ) even if the power is off (VCC = 0V). The receivers Schmitt trigger input stage uses hysteresis to increase noise immunity and decrease errors due to slow input signal transitions. The ICL3E, ICL3E, ICL33E, and ICL34E inverting receivers disable only when EN is driven high. The ICL343E receiver disables during forced (manual) power-down, but not during automatic power-down (see Table ). FN490 Rev 3.00 Page 4 of 3

15 The ICL34E and ICL343E monitor receivers remain active even during manual power-down and forced receiver disable, making them extremely useful for Ring Indicator monitoring. Standard receivers driving powered down peripherals must be disabled to prevent current flow through the peripheral s protection diodes (see Figures and 3). This renders them useless for wake up functions, but the corresponding monitor receiver can be dedicated to this task, as shown in Figure 3. R XIN -V V RIN V kω R XOUT V ROUT FIGURE. INVERTING RECEIVER CONNECTIONS POWERED DOWN UART OLD RS-3 CHIP FIGURE. POWER DRAIN THROUGH POWERED DOWN PERIPHERAL POWERED DOWN UART TO WAKE-UP LOGIC R X T X Rx Tx TRANSITION DETECTOR V OUT = SHDN = R OUTB V OUT = HI-Z R OUT T IN FORCEOFF = OR SHDN =, EN = CURRENT FLOW ICL34XE R IN T OUT FIGURE 3. DISABLED RECEIVERS PREVENT POWER DRAIN Low Power Operation These 3V devices require a nominal supply current of 0.3mA, even at =.V, during normal operation (not in power-down mode). This is considerably less than the ma to ma current required by comparable V RS- 3 devices, allowing users to reduce system power simply by switching to this family. Pin-Compatible Replacements for V Devices The ICL3E, ICL3E, ICL33E are pin-compatible with existing V RS-3 transceivers. See Features on page for more information. The pin compatibility coupled with the low I CC and wide operating supply range make the ICL3xxE potential lower power, higher performance drop-in replacements for existing V applications. As long as the V RS-3 output swings are acceptable, and transmitter input pull-up resistors are not required, the ICL3xxE works in most V applications. When replacing a device in an existing V application, you can terminate C 3 to as shown in the Typical Operating Circuits on page 4. If possible, terminate C 3 to for slightly better performance. Power-Down Functionality (Except ICL33E) The already low current requirement drops significantly when the device enters power-down mode. In powerdown, supply current drops to µa because the on-chip charge pump turns off (V collapses to and V- collapses to ), and the transmitter outputs threestate. Inverting receiver outputs may or may not disable in power-down; refer to Table for details. This micro-power mode makes these devices ideal for battery powered and portable applications. Software Controlled (Manual) Power-Down Most devices in the ICL3xxE family provide pins that allow the user to force the IC into the low power, standby state. On the ICL3E and ICL34E, the power-down control is a simple shutdown (SHDN) pin. Driving this pin high enables normal operation, while driving it low forces the IC into its power-down state. Connect SHDN to if the power-down function is not needed. Note that all the receiver outputs remain enabled during shutdown (see Table ). For the lowest power consumption during power-down, the receivers should also be disabled by driving the EN input high (see Receiver ENABLE Control (ICL3E, ICL3E, ICL33E, and ICL34E Only) on page 8, and Figures and 3). The ICL3E, ICL33E, and ICL343E use a two pin approach in which the FORCEON and FORCEOFF inputs determine the IC s mode. For always enabled operation, FORCEON and FORCEOFF are both strapped high. To switch between active and power-down modes, under logic or software control, only the FORCEOFF input needs FN490 Rev 3.00 Page of 3

16 to be driven. The FORCEON state is not critical, as FORCEOFF overrides FORCEON. However, if strictly manual control over power-down is desired, the user must strap FORCEON high to disable the automatic power-down circuitry. The ICL343E inverting (standard) receiver outputs also disable when the device is in manual power-down, eliminating the possible current path through a shutdown peripheral s input protection diode (see Figures and 3). RS-3 SIGNAL PRESENT AT RECEIVER INPUT? FORCEOFF OR SHDN INPUT TABLE. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE FORCEON INPUT EN INPUT TRANSMITTER OUTPUTS RECEIVER OUTPUTS R OUTB OUTPUTS (Note 7) INVALID OUTPUT MODE OF OPERATION ICL3E, ICL34E N/A L N/A L High-Z Active Active N/A Manual Power-Down N/A L N/A H High-Z High-Z Active N/A Manual Power-Down with Receiver Disabled N/A H N/A L Active Active Active N/A Normal Operation N/A H N/A H Active High-Z Active N/A Normal Operation with Receiver Disabled ICL3E, ICL33E No H H L Active Active N/A L Normal Operation No H H H Active High-Z N/A L (Auto Power-Down Disabled) Yes H L L Active Active N/A H Normal Operation Yes H L H Active High-Z N/A H (Auto Power-Down Enabled) No H L L High-Z Active N/A L Power-Down Due to No H L H High-Z High-Z N/A L Auto Power-Down Logic Yes L X L High-Z Active N/A H Manual Power-Down Yes L X H High-Z High-Z N/A H Manual Power-Down with Receiver Disabled No L X L High-Z Active N/A L Manual Power-Down No L X H High-Z High-Z N/A L Manual Power-Down with Receiver Disabled ICL343E No H H N/A Active Active Active L Normal Operation (Auto Power-Down Disabled) Yes H L N/A Active Active Active H Normal Operation (Auto Power-Down Enabled) No H L N/A High-Z Active Active L Power-Down Due to Auto Power-Down Logic Yes L X N/A High-Z High-Z Active H Manual Power-Down No L X N/A High-Z High-Z Active L Manual Power-Down NOTE: 7. Applies only to the ICL34E and ICL343E. The INVALID output always indicates whether a valid RS- 3 signal is present at any of the receiver inputs (see Table ), providing an easy way to determine when the interface block should power down. If an interface cable is disconnected and all the receiver inputs are floating (but pulled to by the internal receiver pull down resistors), the INVALID logic detects the invalid levels and drives the output low. The power management logic then uses this indicator to power down the interface block. Reconnecting the cable restores valid levels at the receiver inputs, INVALID switches high, and the power management logic wakes up the interface block. INVALID can also indicate the DTR or RING INDICATOR signal, as long as the other receiver inputs are floating or driven to FN490 Rev 3.00 Page of 3

17 (as in the case of a powered down driver). Connecting FORCEOFF and FORCEON together disables the automatic power-down feature, enabling them to function as a manual SHUTDOWN input (see Figure 4). PWR MGT LOGIC CPU I/O UART FORCEOFF FORCEON INVALID ICL3E, ICL33E, ICL343E Automatic Power-Down (ICL3E, ICL33E, and ICL343E Only) Even greater power savings are available by using the devices that feature an automatic power-down function. When no valid RS-3 voltages are sensed on any receiver input for 30µs (see Figure ), the charge pump and transmitters power down, reducing supply current to µa. Invalid receiver levels occur whenever the driving peripheral s outputs are shut off (powered down) or when the RS-3 interface cable is disconnected. The ICL3xxE powers back up whenever it detects a valid RS-3 voltage level on any receiver input. This automatic power-down feature provides additional system power savings without changes to the existing operating system..7v VALID RS-3 LEVEL - ICL3xxE IS ACTIVE FIGURE 4. CONNECTIONS FOR MANUAL POWER-DOWN WHEN NO VALID RECEIVER SIGNALS ARE PRESENT 0.3V -0.3V INDETERMINATE - POWER-DOWN MAY OR MAY NOT OCCUR INVALID LEVEL - POWER-DOWN OCCURS AFTER 30µs With any of the control schemes, the time required to exit power-down and resume transmission is 00µs. A mouse or other application may need more time to wake up from shutdown. If automatic power-down is used, the RS-3 device reenters power-down if valid receiver levels are not reestablished within 30µs of the ICL3xxE powering up. Figure illustrates a circuit that keeps the ICL3xxE from initiating automatic power-down for 00ms after powering up. This gives the slow-to-wake peripheral circuit time to reestablish valid RS-3 output levels. POWER MANAGEMENT UNIT MASTER POWER-DOWN LINE MΩ -.7V INDETERMINATE - POWER-DOWN MAY OR MAY NOT OCCUR VALID RS-3 LEVEL - ICL3xxE IS ACTIVE FIGURE. DEFINITION OF VALID RS-3 RECEIVER LEVELS Automatic power-down operates when the FORCEON input is low and the FORCEOFF input is high. Tying FORCEON high disables automatic power-down, but manual power-down is always available with the overriding FORCEOFF input. Table on page summarizes the automatic power-down functionality. FORCEOFF FORCEON ICL3E, ICL33E, ICL343E FIGURE. CIRCUIT TO PREVENT AUTO POWER-DOWN FOR 00ms AFTER FORCED POWER-UP FN490 Rev 3.00 Page 7 of 3

18 Devices with the automatic power-down feature include an INVALID output signal, which switches low to indicate that invalid levels have persisted on all of the receiver inputs for more than 30µs (see Figure 7). INVALID switches high µs after detecting a valid RS-3 level on a receiver input. INVALID operates in all modes (forced or automatic power-down, or forced on), so it is also useful for systems employing manual power-down circuitry. When automatic power-down is utilized, INVALID = 0 indicates that the ICL3xxE is in power-down mode. The time to recover from automatic power-down mode is typically 00µs. RECEIVER INPUTS TRANSMITTER OUTPUTS INVALID OUTPUT 0 V 0 V- t INVL AUTOPWDN t INVH FIGURE 7. AUTOMATIC POWER-DOWN AND INVALID TIMING DIAGRAMS INVALID } REGION PWR UP Receiver ENABLE Control (ICL3E, ICL3E, ICL33E, and ICL34E Only) The ICL3E, ICL3E, ICL33E, and ICL34E also feature an EN input to control the receiver outputs. Driving EN high disables all the inverting (standard) receiver outputs, placing them in a high impedance state. This is useful for eliminating supply current, due to a receiver output forward biasing the protection diode, when driving the input of a powered down ( = ) peripheral (see Figure on page ). The enable input has no effect on transmitter or monitor (R OUTB ) outputs. Capacitor Selection The charge pumps require capacitors for 3.3V operation. For other supply voltages, refer to Table 3 for capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (by a factor of ) reduces ripple on the transmitter outputs and slightly reduces power consumption. C, C 3, and C 4 can be increased without increasing C s value; however, do not increase C without also increasing C, C 3, and C 4 to maintain the proper ratios (C to the other capacitors). When using minimum required capacitor values, make sure that capacitor values do not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor s Equivalent Series Resistance (ESR) usually rises at low temperatures and it influences the amount of ripple on V and V-. Power Supply Decoupling In most circumstances, a bypass capacitor is adequate. In applications that are particularly sensitive to power supply noise, decouple to ground with a capacitor of the same value as the charge-pump capacitor C. Connect the bypass capacitor as close as possible to the IC. Operation Down to.7v The ICL3xxE transmitter outputs meet RS- levels (±3.7V) at full data rate, with as low as.7v. RS- levels typically ensure interoperability with RS-3 devices. Transmitter Outputs when Exiting Power-Down Figure 8 shows the response of two transmitter outputs when exiting power-down mode. As they activate, the two transmitter outputs properly go to opposite RS-3 levels, with no glitching, ringing, or undesirable transients. Each transmitter is loaded with 3kΩ in parallel with 00pF. Note that the transmitters enable only when the magnitude of the supplies exceeds approximately 3V. V/DIV V/DIV TABLE 3. REQUIRED CAPACITOR VALUES (V) C (µf) C, C 3, C 4 (µf) 3.0 to to to FORCEOFF = 3.3V C - C 4 = TIME (0µs/DIV) FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING POWER-DOWN Mouse Driveability The ICL34E and ICL343E have been specifically designed to power a serial mouse while operating from low voltage supplies. Figure 9 on page 9 shows the transmitter output voltages under increasing load T T FN490 Rev 3.00 Page 8 of 3

19 current. The on-chip switching regulator ensures the transmitters supply at least V during worst case conditions (ma for paralleled V transmitters, 7.3mA for a single V- transmitter). The Automatic Power-Down feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to. TRANSMITTER OUTPUT VOLTAGE (V) 4 V OUT 3 = 3.0V T 0 V OUT - T - ICL34E, ICL343E -3-4 T3 V OUT - V OUT LOAD CURRENT PER TRANSMITTER (ma) FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD CURRENT (PER TRANSMITTER, DOUBLE CURRENT AXIS FOR TOTAL V OUT CURRENT) High Data Rates The ICL3xxE devices maintain the RS-3 V minimum transmitter output voltages even at high data rates. Figure 0 details a transmitter loopback test circuit, and Figure illustrates the loopback test result at 0kbps. For this test, all transmitters were simultaneously driving RS-3 loads in parallel with 000pF at 0kbps. Figure shows the loopback results for a single transmitter driving 000pF and an RS-3 load at 0kbps. The static transmitters were also loaded with an RS-3 receiver. C C SHDN OR FORCEOFF ICL3xxE C 3 C- C V- C C 4 C- T IN R OUT EN T OUT 000pF FIGURE 0. TRANSMITTER LOOPBACK TEST CIRCUIT V R IN K V/DIV T IN T OUT R OUT V/DIV T IN T OUT R OUT = 3.3V C - C 4 = FIGURE. LOOPBACK TEST AT 0kbps = 3.3V C - C 4 = FIGURE. LOOPBACK TEST AT 0kbps Interconnection with 3V and V Logic The ICL3XX devices directly interface with V CMOS and TTL logic families. The AC, HC, and CD4000 outputs can drive ICL3XX inputs with the ICL3XX at 3.3V and the logic supply at V, but ICL3XX outputs do not reach the minimum V IH for these logic families. See Table 4. TABLE 4. LOGIC FAMILY COMPATIBILITY WITH VARIOUS SUPPLY VOLTAGES SYSTEM POWER-SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) µs/div µs/div COMPATIBILITY Compatible with all CMOS families Compatible with all TTL and CMOS logic families 3.3 Compatible with ACT and HCT CMOS, and with TTL. ICL3XX outputs are incompatible with AC, HC, and CD4000 CMOS inputs FN490 Rev 3.00 Page 9 of 3

20 ±kv ESD Protection All pins on ICL3XX devices include ESD protection structures, but the ICL3xxE family incorporates advanced structures that allow the RS-3 pins (transmitter outputs and receiver inputs) to survive ESD events up to ±kv. The RS-3 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. The ESD structures protect the device whether or not it is powered up, protect without allowing any latch-up mechanism to activate, and do not interfere with RS-3 signals as large as ±V. Human Body Model (HBM) Testing This test method emulates the ESD event delivered to an IC during human handling. The tester delivers the charge through a.kω current limiting resistor, making the test less severe than the IEC000 test which utilizes a 330Ω limiting resistor. The HBM method determines an IC s ability to withstand the ESD transients typically present during handling and manufacturing. Due to the random nature of these events, each pin is tested with respect to all other pins. The RS-3 pins on E family devices can withstand HBM ESD events to ±kv. IEC Testing The IEC000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-3 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device s RS-3 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-3 port. AIR-GAP DISCHARGE TEST METHOD For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The E device RS-3 pins withstand ±kv air-gap discharges. CONTACT DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than ±8kV. All E family devices survive ±8kV contact discharges on the RS-3 pins. FN490 Rev 3.00 Page 0 of 3

21 Typical Performance Curves = 3.3V, T A = C. TRANSMITTER OUTPUT VOLTAGE (V) TRANSMITTER AT 0kbps OR TRANSMITTERS AT 30kbps V OUT V OUT LOAD CAPACITANCE (pf) FIGURE 3. TRANSMITTER OUTPUT VOLTAGE vs LOAD CAPACITANCE SLEW RATE (V/µs) 0 0 SLEW -SLEW LOAD CAPACITANCE (pf) FIGURE 4. SLEW RATE vs LOAD CAPACITANCE SUPPLY CURRENT (ma) ICL3E 0kbps 0kbps 0kbps SUPPLY CURRENT (ma) ICL3E, ICL33E, ICL33E 0kbps 0kbps 0kbps LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA LOAD CAPACITANCE (pf) FIGURE. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA SUPPLY CURRENT (ma) ICL34XE 0kbps 0kbps 0kbps LOAD CAPACITANCE (pf) FIGURE 7. SUPPLY CURRENT vs LOAD CAPACITANCE WHEN TRANSMITTING DATA SUPPLY CURRENT (ma) ICL34XE SUPPLY VOLTAGE (V) NO LOAD ALL OUTPUTS STATIC ICL3E, ICL3E, ICL33E, ICL33E ICL34XE FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE FN490 Rev 3.00 Page of 3

22 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR COUNT: ICL3E: 8 ICL3E: 338 ICL33E: 37 ICL33E: 9 ICL34XE: 44 PROCESS: Si Gate CMOS FN490 Rev 3.00 Page of 3

23 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest Rev. DATE REVISION CHANGE 9/4/8 FN Updated on-chip voltage converter conditions from.7v to 3.3V on page -Added product information page links to Related Literature section on page -Updated Ordering Information table on page 8: -Added Tape and Reel (Units) column -Removed the following retired parts: -ICL3ECA, ICL3ECA-T -ICL3ECAZA, ICL3ECAZA-T -ICL3ECV, ICL3ECV-T -ICL3EIA, ICL3EIA-T -ICL3ECA, ICL3ECA-T -ICL3ECV, ICL3ECV-T -ICL3EIAZ, ICL3EIAZ-T -ICL3EIB, ICL3EIB-T -ICL33ECA, ICL33ECA-T -ICL33ECV, ICL33ECV-T -ICL33EIAZ, ICL33EIAZ-T -Added retirement notifications and replacement recommendations for the following parts: -ICL33ECV-0Z -ICL33ECV-0Z-T -ICL33EFV-Z -ICL33EFV-Z -Updated R IN from ±V to ±8V in the Absolute Maximum Ratings on page -Updated Package Outline Drawing M. from Rev. to Rev. on page -Updated graphics to new standard layout and removed the dimensions table -Removed About Intersil section -Added Renesas disclaimer /9/ FN490. -Updated Ordering Information table starting on page 8 -Updated Products section to About Intersil -POD E8.3 updated from rev to rev 3. Changes since rev : ) Removed the dimension chart and replaced with new standard format values for each dimension letter. ) Updated D dimension (in side view; length of package) from 0.84(min) : 0.880(max) to 0.880(33.7)(min) : 0.90(34.)(max) 3) Change JEDEC reference from MS-00-BC issue D to MS-00-AC issue D -POD M.73 updated from rev to rev. Changes since rev : Converted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. -POD M0.73 updated from rev to rev. Changes since rev : Converted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. -POD M8.73 udpated from rev 0 to rev. Changes since rev : Converted to new POD format by moving dimensions from table onto drawing and adding land pattern. No dimension changes. -POD M8.3 updated from rev 0 to rev. Changes since rev : Added land pattern //0 FN490. Revision history begins with this revision. -Converted to new Intersil template. -Added new temp grade (F = extended industrial) to ICL33. Updated ordering info table, Operating Conditions, and added C specs for input lkg currents, and rcvr output high voltage. -Pages 8-0: Removed all withdrawn devices from Ordering Information table. -Pages -4: Added "Boldface limits apply over the operating temperature range." to common conditions of Electrical Specs table. Replaced Note "Parts are 00% tested at C. Full temp limits are guaranteed by bench and tester characterization." with "Parameters with MIN and/or MAX limits are 00% tested at C, unless otherwise specified. Temperature limits established by characterization and are not production tested." FN490 Rev 3.00 Page 3 of 3

24 Package Outline Drawings E8.3 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE Rev. 3, / For the most recent package outline drawing, see E INDEX AREA 3 TOP VIEW 0.80 (7.) 0.40 (.0) 0.3 (8.) (7.) C L SEATING PLANE X 0.00 (0.3) MIN 0.90 (34.) (33.7) 0.9 (4.9) 0. (.93) -C- 0.0 (0.39) MIN (.33) MAX (3.8) 0. (.93) (7.) BSC 0.04 (0.3) (0.04) (0.9) MAX (.77) 0.04 (.) 0.0 (0.8) 0.04 (0.3) 0.00 (.4) BSC SIDE VIEW NOTES:. Controlling Dimensions: INCH (Metric dimensions in parentheses).. Dimensioning and tolerancing per ANSI Y4.M Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions are measured with the package seated in JEDEC seating plane gauge GS-3.. Dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm).. Dimensions are measured with the leads constrained to be perpendicular to datum -C-. 7. Dimension measured at the lead tips with the leads unconstrained. 8. Maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. Package outline compliant to JEDEC MS-00-AC ISSUE D. FN490 Rev 3.00 Page 4 of 3

25 Small Outline Plastic Packages (SOIC) For the most recent package outline drawing, see M.. M. (JEDEC MS-0-AC ISSUE C) LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, /7 FN490 Rev 3.00 Page of 3

26 M.73 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev, /0 For the most recent package outline drawing, see M.73. A 3.00 ±0.0 9 SEE DETAIL "X" ±0.0 3 PIN # I.D. MARK 0.0 C B A 8 0. B TOP VIEW END VIEW H REF C SEATING PLANE 0.0 C SIDE VIEW.0 MAX / M C B A / MIN 0. MAX DETAIL "X" GAUGE PLANE ±0. 0. (.4) NOTES: (.) (0. TYP) (0.3 TYP) TYPICAL RECOMMENDED LAND PATTERN Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0. per side. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0. per side. Dimensions are measured at datum plane H. Dimensioning and tolerancing per ASME Y4.M-994. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. Dimension in ( ) are for reference only. Conforms to JEDEC MO-3. FN490 Rev 3.00 Page of 3

27 Small Outline Plastic Packages (SSOP) For the most recent package outline drawing, see M.09. N INDEX AREA 3 e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.0mm ( inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.0mm ( inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension B does not include dambar protrusion. Allowable dambar protrusion shall be 0.3mm (0.00 inch) total in excess of B dimension at maximum material condition. 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. GAUGE PLANE A M L C M.09 (JEDEC MO-0-AC ISSUE B) LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B C D E e 0.0 BSC 0. BSC - H L N Rev. 3 /0 FN490 Rev 3.00 Page 7 of 3

28 Small Outline Plastic Packages (SOIC) For the most recent package outline drawing, see M.3. N INDEX AREA 3 e D B 0.(0.00) M C A M E -B- -A- -C- SEATING PLANE A B S H 0.(0.00) M B A 0.0(0.004) NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.3mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch) 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. L M h x 4 C M.3 (JEDEC MS-03-AA ISSUE C) LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e 0.00 BSC.7 BSC - H h L N Rev. /0 FN490 Rev 3.00 Page 8 of 3