DATASHEET. Features. Applications. Pin Configurations EL8176. Micropower Single Supply Rail-to-Rail Input/Output Precision Op Amp

Transcription

1 DATASHEET EL876 Micropower Single Supply Rail-to-Rail Input/Output Precision Op Amp FN76 Rev 9. January 6, 5 The EL876 is a precision low power, operational amplifier. The device is optimized for single supply operation between.v to 5.5V. The EL876 draws minimal supply current while meeting excellent DC-accuracy noise and output drive specifications. Competing devices seriously degrade these parameters to achieve micropower supply current. The EL876 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The output swings to both rails. Features 55µA supply current µv max offset voltage (8 Ld SO) na input bias current khz gain-bandwidth product Single supply operation down to.v Rail-to-rail input and output Output sources ma and sinks 6mA load current Pb-free (RoHS compliant) Applications Battery- or solar-powered systems ma to ma current loops Handheld consumer products Medical devices Thermocouple amplifiers Photodiode pre amps ph probe amplifiers Pin Configurations EL876 (6 LD SOT-) TOP VIEW EL876 (8 LD SO) TOP VIEW OUT 6 V + NC 8 EN V - IN EN IN- IN- IN V + OUT V - 5 NC FN76 Rev 9. Page of 6 January 6, 5

2 Pin Descriptions SO PIN NUMBER SOT- PIN NUMBER PIN NAME Equivalent Circuit DESCRIPTION, 5 NC No internal connection IN- Circuit Amplifier s inverting input IN+ Circuit Amplifier s non-inverting input V- Circuit Negative power supply 6 OUT Circuit Amplifier s output 7 6 V+ Circuit Positive power supply 8 5 EN Circuit Amplifier s enable pin with internal pull-down; Logic selects the disabled state; Logic selects the enabled state. V+ V + V + V + IN- IN+ V- EN V- OUT V- V - CAPACITIVELY COUPLED ESD CLAMP CIRCUIT CIRCUIT CIRCUIT CIRCUIT Ordering Information PART NUMBER (Notes, ) PART MARKING PACKAGE (RoHS Compliant) PKG. DWG. # EL876FSZ 876FSZ 8 Ld SO M8.5E EL876FSZ-T7 (Note ) 876FSZ 8 Ld SO M8.5E EL876FWZ-T7 (Note, ) BBVA 6 Ld SOT- P6.6A EL876FWZ-T7A (Note, ) BBVA 6 Ld SOT- P6.6A NOTES:. Please refer to TB7 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), please see product information page for EL876. For more information on MSL, please see tech brief TB6.. The part marking is located on the bottom of the parts. FN76 Rev 9. Page of 6 January 6, 5

3 Absolute Maximum Ratings (T A = +5 C) Supply Voltage (V S ) and Power-up Ramp Rate V, V/µs Differential Input Voltage V Current into IN+, IN-, and EN mA Input Voltage V- -.5V to V+ +.5V ESD Tolerance Human Body Model kv Machine Model V Thermal Information Thermal Resistance (Typical, Note 5) JA ( C/W) 6 Ld SOT- Package Ld SO Package Ambient Operating Temperature Range C to +5 C Storage Temperature Range C to +5 C Operating Junction Temperature C Pb-Free Reflow Profile see TB9 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB79 for details. Electrical Specifications, V - = V, V CM = V, R L = Open, V EN = V, T A = +5 C, unless otherwise specified. Boldface limits apply across the operating temperature range, - C to +5 C. Temperature data established by characterization. PARAMETER DESCRIPTION TEST CONDITIONS (Note 6) TYP (Note 6) UNITS DC SPECIFICATIONS V OS Input Offset Voltage 8 Ld SO - ±5 µv - µv 6 Ld SOT- -5 ±8 5 µv -5 5 µv V OS Long Term Input Offset Voltage Stability. µv/mo Time V OS T I OS Input Offset Drift vs Temperature.7 µv/ C Input Offset Current - ±. na - na - ±.5 na I B Input Bias Current -5 5 na CMIR Input Voltage Range Guaranteed by CMRR test 5 V CMRR Common-mode Rejection Ratio PSRR Power Supply Rejection Ratio V S =.V to 5.5V A VOL V OUT Large Signal Voltage Gain Maximum Output Voltage Swing I S, ON Supply Current, Enabled V EN = 5V I S, OFF Supply Current, Disabled V EN = V V CM = V to 5V 9 db 9 db 9 db 9 db 5 V/mV V O =.5V to.5v, R L = kω V/mV V O =.5V to.5v, R L = kω 5 V/mV VOL; Output low, R L = kω 8 mv mv VOL; Output low, R L = kω VOH; Output high, R L = kω VOH; Output high, R L = kω mv mv V.99 V V.7 V µa 9 µa µa µa FN76 Rev 9. Page of 6 January 6, 5

4 Electrical Specifications, V - = V, V CM = V, R L = Open, V EN = V, T A = +5 C, unless otherwise specified. Boldface limits apply across the operating temperature range, - C to +5 C. Temperature data established by characterization. (Continued) khz PARAMETER DESCRIPTION TEST CONDITIONS (Note 6) TYP (Note 6) UNITS I O + Short Circuit Output Sourcing Current R L = Ω 8 ma 8 ma I O - Short Circuit Output Sinking Current R L = Ω 7 6 ma 5 ma V S Supply Voltage Guaranteed by PSRR test. 5.5 V. 5.5 V V INH Enable Pin High Level V V INL Enable Pin Low Level.8 V I ENH Enable Pin Input Current V EN = 5V.5.7. µa µa I ENL Enable Pin Input Current V EN = V µa - + µa AC SPECIFICATIONS GBW Gain Bandwidth Product A V =, R f = kω R L = kω R g =kω to V CM Unity Gain Bandwidth -db Bandwidth A V =, R f = Ω R L = kω to V CM MHz V OUT = mv P-P Input Noise Voltage Peak-to-Peak f =.Hz to Hz, R L = kω to V CM.5 µv P-P e N Input Noise Voltage Density f O = khz 8 nv/ Hz i N Input Noise Current Density f O = khz.6 pa/ Hz ISO Off-State Input to Output Isolation V EN = 5V, f O = khz, A V = +, V IN = V P-P -7 db CMRR Input Common Mode Rejection Ratio f O = Hz; V CM = V P-P -7 db PSRR+ Power Supply Rejection Ratio (V + ) f O = Hz; V +, V - = ±V, V SOURCE =V P-P -9 db PSRR- Power Supply Rejection Ratio (V - ) f O = Hz; V +, V - = ±V, V SOURCE =V P-P -7 db TRANSIENT RESPONSE SR Slew Rate ±.65 ±. ±. V/µs t r, t f, Large Signal t r, t f, Small Signal t EN Rise Time, % to 9%, V OUT Fall Time, 9% to %, V OUT A V = +, V OUT = V P-P, R g = R f = R L = kω to 8 µs V CM A V = +, V OUT = V P-P, R g = R f = R L = kω to 9 µs V CM Rise Time, % to 9%, V OUT A V = +, V OUT = mv P-P, R g = R f = R L = kω to V CM. µs Fall Time, 9% to %, V OUT A V = +, V OUT = mv P-P, R g = R f = R L = kω to V CM. µs Enable to Output Turn-on Delay Time, % EN to % V OUT V EN = 5V to V, A V = +, µs R g = R f = R L = kω to V CM Enable to Output Turn-off Delay Time, % V EN = V to 5V, A V = +,. µs EN to % V OUT R g = R f = R L = kω to V CM NOTE: 6. Parameters with and/or limits are % tested at +5 C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN76 Rev 9. Page of 6 January 6, 5

5 Typical Performance Curves 8 GAIN (db) 8 6 GAIN PHASE 5 5 PHASE ( ) -5 - GAIN (db) PHASE ( ) - -5 k k M M FIGURE. A VOL vs FREQUENCY AT kω LOAD -8 - k k k M M FIGURE. A VOL vs FREQUENCY AT kω LOAD NORMALIZED GAIN (db) R L = k A V = + V OUT = mv P-P R f = R g = k R f = R g = k R f = R g = k -9 k k k M FIGURE. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES R f /R g NORMALIZED GAIN (db) - V OUT = mv - V OUT = 5mV - V OUT = mv - -5 V OUT = V -6 R L = k -7 A V = + -8 k k k M M FIGURE. GAIN vs FREQUENCY vs V OUT, R L = k NORMALIZED GAIN (db) V OUT = mv V OUT = 5mV - V OUT = mv -5 R L = k V OUT = V -6-7 A V = + -8 k k k M M FIGURE 5. GAIN vs FREQUENCY vs V OUT, R L = k NORMALIZED GAIN (db) R L = k V OUT = mv V OUT = 5mV V OUT = mv V OUT = V -7 A V = + -8 k k k M M FIGURE 6. GAIN vs FREQUENCY vs V OUT, R L = k FN76 Rev 9. Page 5 of 6 January 6, 5

6 Typical Performance Curves (Continued) NORMALIZED GAIN (db) R L = k - - R L = k - - R L = k -5-6 A V = + -7 V OUT = mv P-P -8 k k k M M FIGURE 7. GAIN vs FREQUENCY vs R L GAIN (db) A V = A V = A V = A V = A V =, R g = k, R f = 9.9k A V =, R g = k, R f = M A V =, R g = INF, R f = A V =, R g = k, R f = k k k k M M R L = k V OUT = mv P-P FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 5 GAIN (db) R L = k A V = + V OUT = mv P-P V + = V V + = V GAIN (db) R L = k A V = V OUT = mv P-P R f = kω R g =.kω V + = V V + = V -9 k k k M M FIGURE 9. GAIN vs FREQUENCY vs SUPPLY VOLTAGE k k k M FIGURE. GAIN vs FREQUENCY vs SUPPLY VOLTAGE NORMALIZED GAIN (db) R L = k A V = + V OUT = mv P-P C L = 6.pF C L = 7.pF C L = 5.pF C L = 6.pF k k k M M FIGURE. GAIN vs FREQUENCY vs C L CMRR (db) k k k M R L = OPEN A V = + V CM = V P-P FIGURE. CMRR vs FREQUENCY; V +, V - = ±V FN76 Rev 9. Page 6 of 6 January 6, 5

7 Typical Performance Curves (Continued) PSRR (db) R L = OPEN A V = + V CM = V P-P PSRR- - k k k M PSRR+ FIGURE. PSRR vs FREQUENCY, V +, V - = ±V OFF ISOLATION (db) R L = OPEN A V = + V IN = V P-P - k k k M FIGURE. OFF ISOLATION vs FREQUENCY; V +, V - = ±V M INPUT VOLTAGE NOISE (nv Hz) R L = OPEN A V = + INPUT CURRENT NOISE (pa Hz) R L = OPEN A V = +. k k FIGURE 5. INPUT VOLTAGE NOISE DENSITY vs FREQUENCY.. k k FIGURE 6. INPUT CURRENT NOISE DENSITY vs FREQUENCY INPUT NOISE (µv)..5 R L = OPEN. R g =, R f = k A V = TIME (s) FIGURE 7. INPUT VOLTAGE NOISE.Hz TO Hz LARGE SIGNAL (V) V +, V - = ±V R L = k -.5 R g = k -. R f = k -.5 A V = V OUT = V P-P TIME (µs) FIGURE 8. LARGE SIGNAL STEP RESPONSE FN76 Rev 9. Page 7 of 6 January 6, 5

8 Typical Performance Curves (Continued).. V ENABLE SMALL SIGNAL (mv) 8 6 V +, V - = ±V R L = k R g = R f = k A V = V OUT = mv P-P V- ENABLE (V) V OUT V +, V - = ±V R g = R f = R L = k A V = + V OUT = V P-P OUTPUT (V) TIME (µs) FIGURE 9. SMALL SIGNAL STEP RESPONSE TIME (µs) FIGURE. ENABLE TO OUTPUT RESPONSE V IO (µv) V +, V - = ±V R g = R f = k R L = INF A V = + V OUT = V P-P VCM (V) FIGURE. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE I BIAS (µa) V +, V - = ±V R g = R f = k R L = INF A V = + V OUT = V P-P VCM (V) FIGURE. INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE 6 INPUT OFFSET VOLTAGE (µv) V CM = V DD / A V = - V DD = 5V V DD = V SUPPLY CURRENT (µa) 5-5 OUTPUT VOLTAGE (V) FIGURE. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE SUPPLY VOLTAGE (V) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE FN76 Rev 9. Page 8 of 6 January 6, 5

9 Typical Performance Curves (Continued) SUPPLY CURRENT (µa) DISABLED SUPPLY CURRENT (µa) FIGURE 5. SUPPLY CURRENT vs TEMPERATURE V S = ±V ENABLED. R L = INF FIGURE 6. DISABLED SUPPLY CURRENT vs TEMPERATURE V S = ±V R L = INF.. CURRENT (na).5..5 CURRENT (na) FIGURE 7. I BIAS (+) vs TEMPERATURE V S = ±V FIGURE 8. I BIAS (+) vs TEMPERATURE V S = ±.V.. CURRENT (na).5..5 CURRENT (na) FIGURE 9. I BIAS (-) vs TEMPERATURE V S = ±V FIGURE. I BIAS (-) vs TEMPERATURE V S = ±.V FN76 Rev 9. Page 9 of 6 January 6, 5

10 Typical Performance Curves (Continued).. CURRENT (na).5..5 CURRENT (na) FIGURE. INPUT OFFSET CURRENT vs TEMPERATURE V S = ±V FIGURE. INPUT OFFSET CURRENT vs TEMPERATURE V S = ±.V SO PACKAGE SO PACKAGE 5 5 V OS (µv) 5 V OS (µv) FIGURE. INPUT OFFSET VOLTAGE vs TEMPERATURE V S = ±V FIGURE. INPUT OFFSET VOLTAGE vs TEMPERATURE V S = ±.V V OS (µv) SOT- PACKAGE FIGURE 5. INPUT OFFSET VOLTAGE vs TEMPERATURE V S = ±V V OS (µv) SOT- PACKAGE FIGURE 6. INPUT OFFSET VOLTAGE vs TEMPERATURE V S = ±.V FN76 Rev 9. Page of 6 January 6, 5

11 Typical Performance Curves (Continued) CMRR (db) 5 PSRR (db) FIGURE 7. CMRR vs TEMPERATURE VCM = +V TO -V FIGURE 8. PSRR vs TEMPERATURE V S = ±.V TO ±V V OUT (V) V OUT (mv) FIGURE 9. POSITIVE V OUT vs TEMPERATURE R L = k V S = ±V FIGURE. NEGATIVE V OUT vs TEMPERATURE R L = k V S = ±V V OUT (V) FIGURE. POSITIVE V OUT vs TEMPERATURE R L = k V S = ±V V OUT (mv) FIGURE. NEGATIVE V OUT vs TEMPERATURE R L = k V S = ±V FN76 Rev 9. Page of 6 January 6, 5

12 Typical Performance Curves (Continued) SLEW RATE (V/µs) CURRENT (pa) FIGURE. ±SLEW RATE vs TEMPERATURE V S = ±V INPUT = ±.75V, A V = FIGURE. ±SLEW RATE vs TEMPERATURE V S = ±V INPUT = ±.75V, A V = A VOL (V/mV) FIGURE 5. A VOL, R L = k, V S ±V, V O = ±V Applications Information Introduction The EL876 is a rail-to-rail input and output micro-power precision single supply operational amplifier with an enable feature. The device achieves rail-to-rail input and output operation and eliminates the concerns introduced by a conventional rail-to-rail I/O operational amplifier as discussed below. Rail-to-Rail Input The input common-mode voltage range of the EL876 goes from negative supply to positive supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The EL876 achieves input rail-to-rail without sacrificing important precision specifications and without degrading distortion performance. The EL876's input offset voltage exhibits a smooth behavior throughout the entire common-mode input range. The input bias current versus the common-mode voltage range for the EL876 gives us an undistorted behavior from typically mv above the negative rail all the way up to the positive rail. FN76 Rev 9. Page of 6 January 6, 5

13 Input Bias Current Compensation The input bias currents as low as 5pA are achieved while maintaining an excellent bandwidth for a micro-power operational amplifier. Inside the EL876 is an input bias canceling circuit. The input stage transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. The input bias current compensation/cancellation is stable from - C to +5 C and operates from typically mv to the positive supply rail. Rail-to-Rail Output A pair of complementary MOSFET devices achieves rail-to-rail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The EL876 with a kω load will swing to within mv of the supply rails. Enable/Disable Feature The EL876 offers an EN pin. The active low EN pin disables the device when pulled up to at least.v. When disabled, the output is in a high impedance state and the part consumes typically µa. When disabled, the high impedance output allows multiple parts to be MUXed together. When configured as a MUX, the outputs are tied together in parallel and a channel can be selected by pulling the EN pin to.8v or lower. The EN pin has an internal pull-down. If left open or floating, the EN pin will internally be pulled low, enabling the part by default. Proper Layout Maximizes Performance To achieve the maximum performance of the high input impedance and low offset voltage of the EL876, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 6 shows how the guard ring should be configured and Figure 7 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. FIGURE 7. Typical Applications R R k TYPE THERMOCOUPLE kω kω R kω + V+ EL876 - V- Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability and ability to measure a wide range of temperatures. The EL876 is used to convert the differential thermocouple voltage into single-ended signal with x gain. The EL876's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply. R kω + 5V FIGURE 8. THERMOCOUPLE AMPLIFIER µv/ C HIGH IMPEDANCE INPUT IN V+ 6 EL876 5 FIGURE 6. FN76 Rev 9. Page of 6 January 6, 5

14 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE January 6, 5 FN Updated entire datasheet to Intersil new standard. - Removed WLCSP throughout the document. - Ordering information table on page : Added MSL note. - Added revision history and about Intersil verbiage - Updated 8 Ld SO POD from MDP7 to M8.5E. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC -5. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN76 Rev 9. Page of 6 January 6, 5

15 Package Outline Drawing M8.5E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, 8/9.9 ±. A DETAIL "A". ±. B 6. ±..9 ±. PIN NO. ID MARK 5.7. ±.76 (.5) x 5 ± TOP VIEW.5 MCAB SIDE VIEW B.75.5 ±..75 ±.75 SIDE VIEW A.5 GAUGE PLANE C SEATING PLANE. C.6 ±. (.7) (.6) DETAIL "A" (.5) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (5.) Dimensioning and tolerancing conform to AMSE Y.5m-99. Unless otherwise specified, tolerance : Decimal ±.5 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.5mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDEC MS-. TYPICAL RECOMMENDED LAND PATTERN FN76 Rev 9. Page 5 of 6 January 6, 5

16 Package Outline Drawing P6.6A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev, /.9 A.95 D PIN INDEX AREA C x D. C x (.6) B. ±.5 SEE DETAIL X. M C A-B D TOP VIEW END VIEW C x A-B TYP ( PLCS) H. ±.5 C.5 SIDE VIEW C SEATING PLANE (.5) GAUGE PLANE DETAIL "X".5±. (.6) (.) (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.. Dimensioning and tolerancing conform to ASME Y.5M-99. (.95) Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum H. Package conforms to JEDEC MO-78AA. (.9) TYPICAL RECOMMENDED LAND PATTERN FN76 Rev 9. Page 6 of 6 January 6, 5