Single and Dual Single Supply Ultra-Low Noise, Ultra-Low Distortion, Rail-to-Rail Output, Op Amp

Transcription

1 Single and Dual Single Supply Ultra-Low Noise, Ultra-Low Distortion, Rail-to-Rail Output, Op Amp ISL89, ISL89 The ISL89 and ISL89 are tiny single and dual ultra-low noise, ultra-low distortion operational amplifiers. Fully specified to operated down to +3V single supply. These amplifiers have outputs that swing rail-to-rail, and an input common mode voltage that extends below ground (ground sensing). The ISL89 and ISL89 are unity gain stable with an input referred voltage noise of nv/ Hz. Both parts feature.7% khz. The ISL89 is available in the space-saving 6 Ld UTDFN (.6mmx.6mm) and 6 Ld SOT-3 packages. The ISL89 is available in the Ld UTQFN (.8mmx.mm) and Ld MSOP packages. All devices are guaranteed over - C to +5 C. Ordering Information PART NUMBER (Note 5) ISL89FHZ-T7 (Notes, ) GABH PART MARKING PACKAGE (Pb-free) 6 Ld SOT-3 (Note ) PKG. DWG. # P6.6A ISL89FRUZ-T7 (Notes, 3) M7 6 Ld UTDFN L6..6x.6A ISL89FUZ (Note ) 89Z Ld MSOP M.8A ISL89FUZ-T7 (Note ) 89Z Ld MSOP M.8A ISL89FRUZ-T7 (Notes, 3) E Ld UTQFN L..8x.A ISL89FBZ (Note ) 89 FBZ 8 Ld SOIC M8.5E ISL89FBZ-T7 (Note ) 89 FBZ 8 Ld SOIC M8.5E ISL89EVALZ Evaluation Board ISL89EVALZ Evaluation Board NOTES:. Please refer to TB37 for details on reel specifications.. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. The part marking is located on the bottom of the part. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL89, ISL89. For more information on MSL please see tech brief TB363. Features nv/ Hz input voltage noise khz THD+N typical.7% at V P-P V OUT Harmonic Distortion -87dBc, -9dBc, f o = MHz 7MHz -3dB bandwidth 5V/µs slew rate 7µV maximum offset voltage µa typical input bias current 3dB typical CMRR 3V to 5.5V single supply voltage range Rail-to-rail output Ground sensing Enable pin (not available in the 8 Ld SOIC package option) Pb-free (RoHS compliant) Applications Low noise signal processing Low noise microphones/preamplifiers ADC buffers DAC output amplifiers Digital scales Strain gauges/sensor amplifiers Radio systems Portable equipment Infrared detectors FN67.9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Copyright Intersil Americas Inc. 6-8,. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 ISL89, ISL89 Pin Configurations ISL89 (6 LD SOT-3) ISL89 (6 LD.6x.6x.5 UTDFN) OUT 6 V + OUT 6 V+ V- IN ENABLE IN- IN- IN ENABLE V- ISL89 ( LD MSOP) ISL89 ( LD UTQFN) OUT_A IN-_A IN+_A V- ENABLE_A V OUT_B IN-_B 7 IN+_B ENABLE_B IN-_A IN+_A OUT_A - + V OUT_B IN-_B IN+_B 3 5 V- ENABLE_A ENABLE_B ISL89 (8 LD SOIC) OUT_A 8 V+ IN-_A IN+_A V OUT_B IN-_B IN+_B FN67.9

3 ISL89, ISL89 Pin Descriptions ISL89 (6 Ld SOT-3) ISL89 (6 Ld UTDFN) ISL89 ( Ld MSOP) ISL89 ( Ld UTQFN) ISL89 (8 Ld SOIC) PIN NAME FUNCTION EQUIVALENT CIRCUIT (A) 8 (B) (A) 7 (B) (A) 6 (B) IN- IN-_A IN-_B Inverting input V+ IN- IN+ V- Circuit (A) 7 (B) (A) 6 (B) 3 (A) 5 (B) IN+ IN+_A IN+_B Non-inverting input (See Circuit ) 3 V- Negative supply (A) 9 (B) (A) 8 (B) (A) 7 (B) OUT OUT_A OUT_B Output V+ OUT V- Circuit V+ Positive supply (A) 6 (B) (A) 5 (B) N/A EN EN_A EN_B Enable BAR pin internal pull-down; Logic selects the disabled state; Logic selects the enabled state. EN V+ V- Circuit 3 3 FN67.9

4 ISL89, ISL89 Absolute Maximum Ratings (T A = +5 C) Supply Voltage V Supply Turn On Voltage Slew Rate V/µs Differential Input Current mA Differential Input Voltage V Input Voltage V- -.5V to V+ +.5V ESD Tolerance Human Body Model kV Machine Model V Charged Device Model V Thermal Information Thermal Resistance (typical, Note 6) θ JA ( C/W) 6 Ld SOT-3 Package Ld UTDFN Package Ld MSOP Package Ld UTQFN Package Ld SOIC Package Ambient Operating Temperature Range C to +5 C Storage Temperature Range C to +5 C Operating Junction Temperature C Pb-Free Reflow Profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 6. θ JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V+ = 5.V, V- = GND, R L = Open, R F = kω, A V = - unless otherwise specified. Parameters are per amplifier. Typical values are at V+ = 5V, T A = +5 C. Boldface limits apply over the operating temperature range, - C to +5 C, temperature data established by characterization. PARAMETER DESCRIPTION CONDITIONS (Note 7) TYP (Note 7) UNIT DC SPECIFICATIONS V OS Input Offset Voltage µv ΔV OS ΔT Input Offset Drift vs Temperature See Figure.9 µv/ C I IO Input Offset Current 5 9 na I B Input Bias Current 6 8 µa V CM Common-Mode Voltage Range 3.8 V CMRR Common-Mode Rejection Ratio V CM = V to 3.8V 78 3 db PSRR Power Supply Rejection Ratio V S = 3V to 5V 7 8 db A VOL Large Signal Voltage Gain V O =.5V to V, R L = kω 9 9 db V OUT Maximum Output Voltage Swing Output low, R L = kω 5 8 mv Output high, R L = kω, V+ = 5V V I S,ON Supply Current per Channel, Enabled ma I S,OFF Supply Current, Disabled µa I O + Short-Circuit Output Current R L = Ω 95 9 I O - Short-Circuit Output Current R L = Ω 95 9 ma 35 ma V SUPPLY Supply Operating Range V+ to V V V ENH EN High Level Referred to V- V V ENL EN Low Level Referred to V-.8 V FN67.9

5 Electrical Specifications ISL89, ISL89 V+ = 5.V, V- = GND, R L = Open, R F = kω, A V = - unless otherwise specified. Parameters are per amplifier. Typical values are at V+ = 5V, T A = +5 C. Boldface limits apply over the operating temperature range, - C to +5 C, temperature data established by characterization. (Continued) PARAMETER DESCRIPTION CONDITIONS (Note 7) TYP (Note 7) UNIT I ENH EN Pin Input High Current V EN = V+.8.. I ENL EN Pin Input Low Current V EN = V- 8 µa na AC SPECIFICATIONS GBW -3dB Unity Gain Bandwidth R F = Ω C L = pf, A V =, R L = kω 7 MHz THD+N Total Harmonic Distortion + Noise f = khz, VOUT + V P-P, A V = +, R L = kω. 7 % HD (MHz) nd Harmonic Distortion V OUT = V P-P, A V = -87 dbc 3rd Harmonic Distortion -9 dbc ISO Off-state Isolation f O = khz A V = +; V IN = mv P-P ; R F = Ω, C L = pf, A V =, R L = kω -38 db X-TALK ISL89 Channel-to-Channel Crosstalk f O = khz V S = ±.5V; A V = +; V IN = V P-P, R F = Ω, C L = pf, A V =, R L = kω -5 db PSRR Power Supply Rejection Ratio f O = khz V S = ±.5V; A V = +; V SOURCE = V P-P, R F = Ω, C L = pf, A V =, R L = kω -7 db CMRR Common Mode Rejection Ratio f O = khz V S = ±.5V; A V = +; V CM = V P-P, R F = Ω, C L = pf, A V =, R L = kω -65 db e n Input Referred Voltage Noise f O = khz nv/ Hz i n Input Referred Current Noise f O = khz. pa/ Hz TRANSIENT RESPONSE SR Slew Rate V/µs t pd t r, t f, Small Signal Propagation Delay A V =, V OUT = mv P-P, R F = Ω, C L =.pf. ns % V IN - % V OUT Rise Time, t r % to 9% A V = +, V OUT =.V P-P, R F = Ω, C L =.pf 3.3 ns Fall Time, t f % to 9% 6.3 ns t r, t f Large Signal Rise Time, t r % to 9% A V = +, V OUT = V P-P, R F = R G = 99Ω, R L = kω, ns Fall Time, t f % to 9% C L =.pf 5 ns Rise Time, t r % to 9% A V = +, V OUT =.7V P-P, R F = R G = 99Ω, 9 ns Fall Time, t f % to 9% R L = kω, C L =.pf 87 ns t s Settling Time to.% 9% V OUT to.% V OUT A V =, V OUT = V P-P, R F = Ω, C L =.pf 5 ns t EN ENABLE to Output Turn-on Delay A V =, V OUT = VDC, R L = kω, C L =.pf 33 ns Time; % EN - % V OUT ENABLE to Output Turn-off Delay A V =, V OUT = VDC, R L = kω, C L =.pf 5 ns Time; % EN - % V OUT NOTE: 7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 5 FN67.9

6 ISL89, ISL89 Typical Performance Curves CLOSED LOOP GAIN (db) R L = k R L = R L = k - R L = k -5 V + = 5V -6 A V = + -7 C L = pf V OUT = mv P-P -8 k M M M G CLOSED LOOP GAIN (db) C L = pf C L = 3pF C L = 9pF C L = 57pF C L = pf - V + = 5V C L = pf -6 A V = + -8 R L = kω V OUT = mv P-P - k k M M M G FIGURE. GAIN vs FREQUENCY FOR VARIOUS R LOAD FIGURE. GAIN vs FREQUENCY FOR VARIOUS C LOAD CLOSED LOOP GAIN (db) V OUT = V P-P V OUT = mv P-P - -5 V + = 5V V OUT = mv P-P -6 A V = + -7 R L = kω C L = pf -8 k k M M M G V OUT = mv P-P FIGURE 3. -3dB BANDWIDTH vs V OUT GAIN (db) AV =, R F = 9.9k, R G = 99 3 AV =, R F = 99k, R G = 99 AV =, R F =.k, R G = 99 AV =, R F =, R G = INF V+ = 5V R L = k V OUT = mv P-P - k k M M M FIGURE. FREQUENCY RESPONSE vs CLOSED LOOP GAIN M M INPUT IMPEDANCE (Ω) k k k SOURCE V P-P V+ = 5V, 3V ENABLED AND DISABLED V = V + = 5V, 3V V SOURCE = V P-P k M M M G k M M M G OUTPUT IMPEDANCE (Ω) k k k FIGURE 5. INPUT IMPEDANCE vs FREQUENCY FIGURE 6. DISABLED OUTPUT IMPEDANCE vs FREQUENCY 6 FN67.9

7 ISL89, ISL89 Typical Performance Curves (Continued) OUTPUT IMPEDANCE (Ω). V+ = 5V, 3V. k M M M G FIGURE 7. ENABLED OUTPUT IMPEDANCE vs FREQUENCY CMRR (db) V + = 5V A V = + -9 R L = kω - C L = pf V CM = mv P-P - k k k M M M FIGURE 8. CMRR vs FREQUENCY PSRR (db) V+ = 5V A V = + R L = kω C L = pf V SOURCE = mv P-P PSRR- -9 k k k M M M FIGURE 9. PSRR vs FREQUENCY PSRR+ OFF ISOLATION (db) V P-P = V V P-P = mv -6 V + = 5V A V = + -7 R L = kω V P-P = mv C L = pf -8 k k M M M G FIGURE. OFF ISOLATION vs FREQUENCY CROSSTALK (db) V P-P = V k k M M M G FIGURE. CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY THD + NOISE (%)... V+ = 5V R L = k R F =, AV = V OUT = V P-P Hz TO khz FILTER. k k 6k 8k k k k 6k 8k k FIGURE. THD+N vs FREQUENCY 7 FN67.9

8 ISL89, ISL89 Typical Performance Curves (Continued) THD + NOISE (%)... V+ = 5V R L = k R F =, AV = FREQUENCY= khz Hz TO khz FILTER INPUT VOLTAGE NOISE (nv/ Hz) V OUT (V P-P ) FIGURE 3. khz vs V OUT.. k k k FIGURE. INPUT REFERRED NOISE VOLTAGE vs FREQUENCY CURRENT NOISE (pa/ Hz) VOLTS (V) 5 3 ENABLE EN INPUT DISABLE ENABLE V+ = 5V A V = + R L = kω C L = pf V IN = VDC OUTPUT. k k k - 3 TIME (µs) FIGURE 5. INPUT REFERRED NOISE CURRENT vs FREQUENCY FIGURE 6. ENABLE/DISABLE TIG V OUT SMALL SIGNAL (V) V IN V+ = ±.5V A V = + R L = kω V OUT = mv P-P V OUT TIME (ns) LARGE SIGNAL (V).. V IN -. V+ = ±.5V -. A V = + R F = R G = 99Ω -.6 R L = kω V OUT = V P-P TIME (ns) FIGURE 7. SMALL SIGNAL STEP RESPONSE FIGURE 8. LARGE SIGNAL (V) STEP RESPONSE 8 FN67.9

9 Typical Performance Curves (Continued) ISL89, ISL89 3 V OUT n = 5 LARGE SIGNAL (V) - - V IN V+ = ±.5V A V = + R F = R G = 99Ω R L = kω V OUT =.7V P-P CURRENT (ma) MEDIAN TIME (ns) FIGURE 9. LARGE SIGNAL (.7V) STEP RESPONSE FIGURE. SUPPLY CURRENT vs TEMPERATURE, V S = ±.5V ENABLED, R L = INF V OS (µv) 6 n = MEDIAN FIGURE. V OS vs TEMPERATURE V S = ±.5V I BIAS+ (µa) -9 n = MEDIAN FIGURE. I BIAS+ vs TEMPERATURE V S = ±.5V -9 n = 5 8 n = 5-6 I BIAS- (µa) MEDIAN I IO (na) MEDIAN FIGURE 3. I BIAS- vs TEMPERATURE V S = ±.5V FIGURE. I IO vs TEMPERATURE V S = ±.5V 9 FN67.9

10 ISL89, ISL89 Typical Performance Curves (Continued) 3 n = 5 MEDIAN n = 5 CMRR (db) 9 8 PSRR (db) MEDIAN FIGURE 5. CMRR vs TEMPERATURE, VCM = 3.8V, V S = ±.5V FIGURE 6. PSRR vs TEMPERATURE ±.5V TO ±.5V V OUT (V) MEDIAN n = 5 V OUT (mv) n = 5 MEDIAN FIGURE 7. POSITIVE V OUT vs TEMPERATURE R L = k, V S =±.5V FIGURE 8. NEGATIVE V OUT vs TEMPERATURE R L = k, V S = ±.5V V CM OVERHEAD TO SUPPLY RAILS (V) INPUT VOLTAGE TO THE POSITIVE RAIL (V + - V CM ) INPUT VOLTAGE TO THE NEGATIVE RAIL (V - + V CM ) FIGURE 9. INPUT COMMON MODE VOLTAGE vs TEMPERATURE FN67.9

11 ISL89, ISL89 Applications Information Product Description The ISL89 and ISL89 are voltage feedback operational amplifiers designed for communication and imaging applications requiring low distortion, very low voltage and current noise. Both parts feature high bandwidth while drawing moderately low supply current. The ISL89 and ISL89 use a classical voltage-feedback topology, which allows them to be used in a variety of applications where current-feedback amplifiers are not appropriate because of restrictions placed upon the feedback element used with the amplifier. Enable/Power-Down The ISL89 and ISL89 amplifiers are disabled by applying a voltage greater than V to the EN pin, with respect to the V- pin. In this condition, the output(s) will be in a high impedance state and the amplifier(s) current will be reduced to 3µA/Amp. By disabling the part, multiple parts can be connected together as a MUX. The outputs are tied together in parallel and a channel can be selected by the EN pin. The EN pin also has an internal pull-down. If left open, the EN pin will pull to the negative rail and the device will be enabled by default. Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. Both parts have additional back-to-back diodes across the input terminals (as shown in Figure 3). In pulse applications where the input Slew Rate exceeds the Slew Rate of the amplifier, the possibility exists for the input protection diodes to become forward biased. This can cause excessive input current and distortion at the outputs. If overdriving the inputs is necessary, the external input current must never exceed 5mA. An external series resistor may be used to limit the current, as shown in Figure 3. R FIGURE 3. LIMITING THE INPUT CURRENT TO LESS THAN 5mA - + Using Only One Channel The ISL89 is a Dual channel op amp. If the application only requires one channel when using the ISL89, the user must configure the unused channel to prevent it from oscillating. Oscillation can occur if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 3). Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a.7µf tantalum capacitor in parallel with a.µf capacitor has been shown to work well when placed at each supply pin. For good AC performance, parasitic capacitance should be kept to a minimum, especially at the inverting input. When ground plane construction is used, it should be removed from the area near the inverting input to minimize any stray capacitance at that node. Carbon or Metal-Film resistors are acceptable with the Metal-Film resistors giving slightly less peaking and bandwidth because of additional series inductance. Use of sockets, particularly for the SO package, should be avoided if possible. Sockets add parasitic inductance and capacitance, which will result in additional peaking and overshoot. Current Limiting - + FIGURE 3. PREVENTING OSCILLATIONS IN UNUSED CHANNELS The ISL89 and ISL89 have no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. This is why output short circuit current is specified and tested with R L = Ω. FN67.9

12 Power Dissipation It is possible to exceed the +5 C maximum junction temperatures under certain load and power-supply conditions. It is therefore important to calculate the maximum junction temperature (T J ) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related as follows: T J = T + ( θ JA xpd TOTAL ) (EQ. ) ISL89, ISL89 where: P DTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PD ) PD for each amplifier can be calculated as follows: V OUT PD = *V S I S + ( V S - V OUT ) R L (EQ. ) where T = Maximum ambient temperature θ JA = Thermal resistance of the package PD = Maximum power dissipation of amplifier V S = Supply voltage I = Maximum supply current of amplifier V OUT = Maximum output voltage swing of the application R L = Load resistance For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN67.9

13 Revision History ISL89, ISL89 The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE January 8, FN67.9 Ordering Information on page : Added Eval Board ISL89EVALZ ISL89FHZ-T7 - Pkg. Dwg. # changed from MDP38 TO P6.6A ISL89FUZ - Pkg. Dwg. # changed from MDP3 to M.8A ISL89FBZ - Pkg. Dwg. # changed from MDP7 to M8.5E Changed µtdfn and TQFN to ultra matching package outline drawing descriptions Added MSL Note 5 and SOT-3 Note Thermal Information on page : Ld UTQFN θ JA changed from "8" to "3" 8 LD SOIC θ JA changed from "5" to "" Electrical Specifications table change on page 5: Updated note in Min Max column of spec tables from "Parameters with and/or limits are % tested at +5 C, unless otherwise specified. Temperature limits established by characterization and are not production tested." to "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." Typical Performance Curves change on page : Added Figure 9 INPUT COMMON MODE VOLTAGE vs TEMPERATURE Updated Package Outline Drawings: Page - MDP38 to P6.6A - chgd from multiple pkgs to individual no dimension changes Page 7 - MDP7 to M8.5E - chgd from multiple pkgs to individual no dimension changes Page 8 - MDP3 to M.8A - chgd from multiple pkgs to individual no dimension changes Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL89,ISL89 To report errors or suggestions for this datasheet, please go to: FITs are available from our website at: 3 FN67.9

14 Package Outline Drawing P6.6A 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE Rev, /.9 ISL89, ISL89 A.95 D PIN INDEX AREA C x D 3. C x (.6) B. ±.5 3 SEE DETAIL X. M C A-B D END VIEW C x A-B TYP ( PLCS) H. ±.5 C.5 SIDE VIEW C SEATING PLANE (.5) GAUGE PLANE DETAIL "X".5±. (.6) (.) (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.. Dimensioning and tolerancing conform to ASME Y.5M-99. (.95) Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum H. Package conforms to JEDEC MO-78AA. (.9) TYPICAL RECOMMENDED LAND PATTERN FN67.9

15 ISL89, ISL89 Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) E 6 A B A L6..6x.6A 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS PIN REFERENCE X.5 C X.5 C 3 D A SYMBOL NOAL NOTES A A A3.7 REF - b x D. C.8 C e. REF 6 CO. 3 E BOTTOM VIEW SIDE VIEW DETAIL A A3 L DAP SIZE.3 x.76 b 6X. M C A B C SEATING PLANE D D E E e.5 BSC - L Rev. 6/6 NOTES:. Dimensions are in mm. Angles in degrees.. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed.8mm. 3. Warpage shall not exceed.mm.. Package length/package width are considered as special characteristics. 5. JEDEC Reference MO For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389..7± TERAL THICKNESS A DETAIL A LAND PATTERN 6 5 FN67.9

16 ISL89, ISL89 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN) NX (b) 5 6 INDEX AREA X. C.5 C X SEATING PLANE SECTION "C-C". C A (A) N. C L A (DATUM A) PIN # ID D SIDE VIEW 7 C C e e C L NX L BOTTOM VIEW 5 A C B E NX b 5 X. M C A B.5 M C (DATUM B) L TERAL TIP L..8x.A LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE SYMBOL NOTES: MILLIMETERS NOAL NOTES A A A3.7 REF - b D E e. BSC - L L N Nd 3 Ne 3 3 θ - Rev. 3 6/6. Dimensioning and tolerancing conform to ASME Y N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively.. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between.5mm and.3mm from the terminal tip. 6. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 7. Maximum package warpage is.5mm. 8. Maximum allowable burrs is.76mm in all directions. 9. JEDEC Reference MO-55.. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB LAND PATTERN. 6 FN67.9

17 Package Outline Drawing M8.5E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev, 8/9 ISL89, ISL89.9 ±. A DETAIL "A". ±.3 B 6. ±. 3.9 ±. PIN NO. ID MARK ±.76 (.35) x 5 ±.5 MCAB SIDE VIEW B.75.5 ±..75 ±.75 SIDE VIEW A.5 GAUGE PLANE C SEATING PLANE. C.63 ±.3 (.7) (.6) DETAIL "A" (.5) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (5.) Dimensioning and tolerancing conform to AMSE Y.5m-99. Unless otherwise specified, tolerance : Decimal ±.5 Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.5mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDEC MS-. TYPICAL RECOMMENDED LAND PATTERN 7 FN67.9

18 ISL89, ISL89 Package Outline Drawing M.8A (JEDEC MO-87-BA) LEAD I SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev, 9/9 3. ±. A.5 C A B DETAIL "X". Max 3. ±..9 ±.5 SIDE VIEW.8 ±.5 PIN# ID B.5 BSC.95 BSC Gauge H.86 ±.9 Plane.5 C.3 +.7/ CAB SEATING PLANE. ±.5. C.55 ±.5 DETAIL "X" 3 ±3 SIDE VIEW NOTES:. Dimensions are in millimeters.. Dimensioning and tolerancing conform to AMSE Y.5m Plastic or metal protrusions of.5mm max per side are not included. Plastic interlead protrusions of.5mm max per side are not included. Dimensions D and E are measured at Datum Plane H. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP3 MSOPL. 8 FN67.9