Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # ELIWT-T7 8 7 (3k pcs) Ld TSOT MDP49 ELIWT-T7A 8 7 (2 pcs) Ld TSOT MDP49

Transcription

1 EL, EL2, EL4 Data Sheet FN79.7 6MHz Rail-to-Rail Input-Output Op Amps The EL, EL2, and EL4 are low power, high voltage rail-to-rail input-output amplifiers. The EL represents a single amplifier, the EL2 contains two amplifiers, and the EL4 contains four amplifiers. Operating on supplies ranging from V to V, while consuming only 2.mA per amplifier, the EL, EL2, and EL4 have a bandwidth of 6MHz (-3dB). They also provide common mode input ability beyond the supply rails, as well as rail-to-rail output capability. This enables these amplifiers to offer maximum dynamic range at any supply voltage. The EL, EL2, and EL4 also feature fast slewing and settling times, as well as a high output drive capability of 6mA (sink and source). These features make these amplifiers ideal for high speed filtering and signal conditioning application. Other applications include battery power, portable devices, and anywhere low power consumption is important. The EL is available in Ld TSOT and 8 Ld HMSOP packages. The EL2 is available in the 8 Ld HMSOP package. The EL4 is available in space-saving 4 Ld HTSSOP packages. All feature a standard operational Audio processing amplifier pinout. These amplifiers operate over a temperature range of -4 C to +8 C. Features Pb-free plus anneal available (RoHS compliant) 6MHz (-3dB) bandwidth Supply voltage = 4.V to 6.V Low supply current (per amplifier) = 2.mA High slew rate = 7V/µs Unity-gain stable Beyond the rails input capability Rail-to-rail output swing ±8mA output short current Applications TFT-LCD panels V COM amplifiers Drivers for A/D converters Data acquisition Video processing Active filters Test equipment Battery-powered applications Portable equipment Pinouts EL (8 LD HMSOP) TOP VIEW EL ( LD TSOT) TOP VIEW EL2 (8 LD HMSOP) TOP VIEW EL4 (4 LD HTSSOP) TOP VIEW NC 8 NC VOUT VS+ VOUTA 8 VS+ VOUTA 4 VOUTD VIN VS+ VOUT NC VIN VINA VOUTB VINB+ VINA- VINA+ VS VS- VIN- VS- VIN- VINB- VS- VINA- 3 VIND- 2 VIND+ VS- VINB+ VINB VINC+ 9 VINC- VOUTB 7 8 VOUTC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 24, 27. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # ELIWT-T7 8 7 (3k pcs) Ld TSOT MDP49 ELIWT-T7A 8 7 (2 pcs) Ld TSOT MDP49 ELIWTZ-T7 (Note) BAAG 7 (3k pcs) Ld TSOT (Pb-free) MDP49 ELIWTZ-T7A (Note) BAAG 7 (2 pcs) Ld TSOT (Pb-free) MDP49 ELIYE 7-8 Ld HMSOP (3.mm) MDP ELIYE-T Ld HMSOP (3.mm) MDP ELIYE-T Ld HMSOP (3.mm) MDP ELIYEZ (Note) BAAJA - 8 Ld HMSOP (Pb-free) (3.mm) MDP ELIYEZ-T7 (Note) BAAJA 7 8 Ld HMSOP (Pb-free) (3.mm) MDP ELIYEZ-T3 (Note) BAAJA 3 8 Ld HMSOP (Pb-free) (3.mm) MDP ELAIYEZ (Note) BBLAA - 8 Ld HMSOP (Pb-free) (3.mm) MDP ELAIYEZ-T3 (Note) BBLAA 3 8 Ld HMSOP (Pb-free) (3.mm) MDP ELAIYEZ-T7 (Note) BBLAA 7 8 Ld HMSOP (Pb-free) (3.mm) MDP EL2IYE 9-8 Ld HMSOP (3.mm) MDP EL2IYE-T Ld HMSOP (3.mm) MDP EL2IYE-T Ld HMSOP (3.mm) MDP EL2IYEZ (Note) BAATA - 8 Ld HMSOP (Pb-free) (3.mm) MDP EL2IYEZ-T7 (Note) BAATA 7 8 Ld HMSOP (Pb-free) (3.mm) MDP EL2IYEZ-T3 (Note) BAATA 3 8 Ld HMSOP (Pb-free) (3.mm) MDP EL4IRE 4IRE - 4 Ld HTSSOP (4.4mm) MDP48 EL4IRE-T7 4IRE 7 4 Ld HTSSOP (4.4mm) MDP48 EL4IRE-T3 4IRE 3 4 Ld HTSSOP (4.4mm) MDP48 EL4IREZ (Note) 4IREZ - 4 Ld HTSSOP (Pb-free) (4.4mm) MDP48 EL4IREZ-T7 (Note) 4IREZ 7 4 Ld HTSSOP (Pb-free) (4.4mm) MDP48 EL4IREZ-T3 (Note) 4IREZ 3 4 Ld HTSSOP (Pb-free) (4.4mm) MDP48 EL4IR 4IR - 4 Ld TSSOP (4.4mm) MDP44 EL4IR-T7 4IR 7 4 Ld TSSOP (4.4mm) MDP44 EL4IR-T3 4IR 3 4 Ld TSSOP (4.4mm) MDP44 EL4IRZ (Note) 4IRZ - 4 Ld TSSOP (Pb-free) (4.4mm) M4.73 EL4IRZ-T7 (Note) 4IRZ 7 4 Ld TSSOP (Pb-free) (4.4mm) M4.73 EL4IRZ-T3 (Note) 4IRZ 3 4 Ld TSSOP (Pb-free) (4.4mm) M4.73 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. 2 FN79.7

3 Absolute Maximum Ratings (T A = +2 C) Supply Voltage between V S + and V S V Input Voltage V S - -.V, V S +.V Maximum Continuous Output Current mA Maximum Die Temperature C Thermal Information Storage Temperature C to + C Ambient Operating Temperature C to +8 C Power Dissipation See Curves Pb-free reflow profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +V, V S - = -V, R L = kω to V, T A = +2 C, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = V 3 mv TCV OS Average Offset Voltage Drift (Note ) 7 µv/ C I B Input Bias Current V CM = V 2 6 na R IN Input Impedance GΩ C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio for V IN from -.V to.v 7 db A VOL Open-Loop Gain -4.V V OUT 4.V 62 7 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -ma V V OH Output Swing High I L = ma V I SC Short-Circuit Current ±8 ma I OUT Output Current ±6 ma POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from ±2.2V to ±7.7V 6 8 db I S Supply Current No load (EL) ma No load (EL2) 7. ma No load (EL4) ma DYNAMIC PERFORMANCE SR Slew Rate (Note 2) -4.V V OUT 4.V, 2% to 8% 7 V/µs t S Settling to +.% (A V = +) (A V = +), V O = 2V step 8 ns BW -3dB Bandwidth 6 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin CS Channel Separation f = MHz (EL2 and EL4 only) db d G Differential Gain (Note 3) R F = R G = kω and V OUT =.4V.7 % d P Differential Phase (Note 3) R F = R G = kω and V OUT =.4V.24 NOTES:. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. 3. NTSC signal generator used. 3 FN79.7

4 Electrical Specifications V S + = +V, V S - = V, R L = kω to 2.V, T A = +2 C, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 2.V 3 mv TCV OS Average Offset Voltage Drift (Note 4) 7 µv/ C I B Input Bias Current V CM = 2.V 2 6 na R IN Input Impedance GΩ C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio for V IN from -.V to.v 4 66 db A VOL Open-Loop Gain.V V OUT 4.V 62 7 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -ma 8 mv V OH Output Swing High I L = ma V I SC Short-circuit Current ±8 ma I OUT Output Current ±6 ma POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from 4.V to.v 6 8 db I S Supply Current No load (EL) ma No load (EL2) 7. ma DYNAMIC PERFORMANCE No load (EL4) ma SR Slew Rate (Note ) V V OUT 4V, 2% to 8% 7 V/µs t S Settling to +.% (A V = +) (A V = +), V O = 2V step 8 ns BW -3dB Bandwidth 6 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin CS Channel Separation f = MHz (EL2 and EL4 only) db d G Differential Gain (Note 6) R F = R G = kω and V OUT =.4V.7 % d P Differential Phase (Note 6) R F = R G = kω and V OUT =.4V.24 NOTES: 4. Measured over operating temperature range.. Slew rate is measured on rising and falling edges. 6. NTSC signal generator used. 4 FN79.7

5 Electrical Specifications V S + = +V, V S - = V, R L = kω to 7.V, T A = +2 C, Unless Otherwise Specified PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 7.V 3 mv TCV OS Average Offset Voltage Drift (Note 7) 7 µv/ C I B Input Bias Current V CM = 7.V 2 6 na R IN Input Impedance GΩ C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio for V IN from -.V to.v 3 72 db A VOL Open-Loop Gain.V V OUT 4.V 62 7 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -ma 8 mv V OH Output Swing High I L = ma V I SC Short-circuit Current ±8 ma I OUT Output Current ±6 ma POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from 4.V to.v 6 8 db I S Supply Current No load (EL) ma No load (EL2) 7. ma DYNAMIC PERFORMANCE No load (EL4) ma SR Slew Rate (Note 8) V V OUT 4V, 2% to 8% 7 V/µs t S Settling to +.% (A V = +) (A V = +), V O = 2V step 8 ns BW -3dB Bandwidth 6 MHz GBWP Gain-Bandwidth Product 32 MHz PM Phase Margin CS Channel Separation f = MHz (EL2 and EL4 only) db d G Differential Gain (Note 9) R F = R G = kω and V OUT =.4V.6 % d P Differential Phase (Note 9) R F = R G = kω and V OUT =.4V.22 NOTES: 7. Measured over operating temperature range 8. Slew rate is measured on rising and falling edges 9. NTSC signal generator used FN79.7

6 Typical Performance Curves QUANTITY (AMPLIFIERS) T A = +2 C TYPICAL PRODUCTION DISTRIBUTION QUANTITY (AMPLIFIERS) 2 2 TYPICAL PRODUCTION DISTRIBUTION FIGURE. INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE DRIFT, TCV OS (µv/ C) INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT OFFSET VOLTAGE DRIFT INPUT OFFSET VOLTAGE (mv) INPUT BIAS CURRENT (µa) FIGURE 3. TEMPERATURE ( C) INPUT OFFSET VOLTAGE vs TEMPERATURE FIGURE 4. TEMPERATURE ( C) INPUT BIAS CURRENT vs TEMPERATURE OUTPUT HIGH VOLTAGE (V) I OUT = ma OUTPUT LOW VOLTAGE (V) I OUT = ma TEMPERATURE ( C) FIGURE. OUTPUT HIGH VOLTAGE vs TEMPERATURE TEMPERATURE ( C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE 6 FN79.7

7 Typical Performance Curves (Continued) OPEN-LOOP GAIN (db) R L = kω SLEW RATE (V/µs) FIGURE 7. TEMPERATURE ( C) TEMPERATURE ( C) OPEN-LOOP GAIN vs TEMPERATURE FIGURE 8. SLEW RATE vs TEMPERATURE SUPPLY CURRENT (ma) 2.9 T A = +2 C SUPPLY CURRENT (ma) SUPPLY VOLTAGE (V) FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE TEMPERATURE ( C) FIGURE. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE..3 DIFFERENTIAL GAIN (%) A V = 2 R L = kω DIFFERENTIAL PHASE ( ) FIGURE. IRE DIFFERENTIAL GAIN IRE FIGURE 2. DIFFERENTIAL PHASE 7 FN79.7

8 Typical Performance Curves (Continued) DISTORTION (db) A V = 2 R L = kω FREQ = MHz 2nd HD GAIN (db) PHASE GAIN PHASE ( ) -8 3rd HD k - k k M M M V OP-P (V) FIGURE 3. HARMONIC DISTORTION vs V OP-P FIGURE 4. FREQUENCY (Hz) OPEN LOOP GAIN AND PHASE MAGNITUDE (NORMALIZED) (db) A V = C LOAD = pf kω Ω 6Ω - k M M M MAGNITUDE (NORMALIZED) (db) A V = R L = kω pf pf 47pF pf -2 k M M M FREQUENCY (Hz) FIGURE. FREQUENCY RESPONSE FOR VARIOUS R L FIGURE 6. FREQUENCY (Hz) FREQUENCY RESPONSE FOR VARIOUS C L OUTPUT IMPEDANCE (Ω) k k M M M MAXIMUM OUTPUT SWING (V P-P ) A V = R L = kω DISTORTION <% k k M M M FREQUENCY (Hz) FREQUENCY (khz) FIGURE 7. CLOSED LOOP OUTPUT IMPEDANCE FIGURE 8. MAXIMUM OUTPUT SWING vs FREQUENCY 8 FN79.7

9 Typical Performance Curves (Continued) - -8 PSRR PSRR- CMRR (db) -3-4 PSRR (db) k k k M M M -2 T A = +2 C k k k M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 9. CMRR FIGURE 2. PSRR VOLTAGE NOISE (nv/ Hz) K -2 k k k M M M XTALK (db) DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION -4 R L = kω A V = V IN = mv RMS -6 k k k M M 3M FIGURE 2. FREQUENCY (Hz) INPUT VOLTAGE NOISE SPECTRAL DENSITY FIGURE 22. FREQUENCY (Hz) CHANNEL SEPARATION OVERSHOOT (%) A V = R L = kω V IN = ±mv T A = +2 C STEP SIZE (V) A V = R L = kω.% -3.% k LOAD CAPACITANCE (pf) FIGURE 23. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE SETTLING TIME (ns) FIGURE 24. SETTLING TIME vs STEP SIZE 9 FN79.7

10 Typical Performance Curves (Continued) T A = +2 C A V = R L = kω T A = +2 C A V = R L = kω mv STEP V STEP FIGURE 2. ns/div LARGE SIGNAL TRANSIENT RESPONSE FIGURE 26. ns/div SMALL SIGNAL TRANSIENT RESPONSE Pin Descriptions EL (TSOT-) EL (HMSOP8) EL2 (HMSOP8) EL4 (HTSSOP4) NAME FUNCTION EQUIVALENT CIRCUIT 6 VOUTA Amplifier A output V S+ V S- GND CIRCUIT VINA- Amplifier A inverting input V S+ CIRCUIT 2 V S VINA+ Amplifier A non-inverting input (Reference Circuit 2) VS+ Positive power supply VINB+ Amplifier B non-inverting input (Reference Circuit 2) 6 6 VINB- Amplifier B inverting input (Reference Circuit 2) 7 7 VOUTB Amplifier B output (Reference Circuit ) 8 VOUTC Amplifier C output (Reference Circuit ) 9 VINC- Amplifier C inverting input (Reference Circuit 2) VINC+ Amplifier C non-inverting input (Reference Circuit 2) VS- Negative power supply 2 VIND+ Amplifier D non-inverting input (Reference Circuit 2) 3 VIND- Amplifier D inverting input (Reference Circuit 2) 4 VOUTD Amplifier D output (Reference Circuit ),, 8 NC Not connected FN79.7

11 Applications Information Product Description The EL, EL2, and EL4 voltage feedback amplifiers are fabricated using a high voltage CMOS process. They exhibit rail-to-rail input and output capability, are unity gain stable and have low power consumption (2.mA per amplifier). These features make the EL, EL2, and EL4 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode and driving a load of kω, the EL, EL2, and EL4 have a -3dB bandwidth of 6MHz while maintaining a 7V/µs slew rate. The EL is a single amplifier, the EL2 a dual amplifier, and the EL4 a quad amplifier. Operating Voltage, Input, and Output The EL, EL2, and EL4 are specified with a single nominal supply voltage from V to V or a split supply with its total range from V to V. Correct operation is guaranteed for a supply range of 4.V to 6.V. Most EL, EL2, and EL4 specifications are stable over both the full supply range and operating temperatures of -4 C to +8 C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. Short Circuit Current Limit The EL, EL2, and EL4 will limit the short circuit current to ±8mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±6mA. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The EL, EL2, and EL4 are immune to phase reversal as long as the input voltage is limited from V S - -.V to V S + +.V. Figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than.6v, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. V S = ±2.V, T A = +2 C, A V =, V IN = 6V P-P V µs The input common-mode voltage range of the EL, EL2, and EL4 extends mv beyond the supply rails. The output swings of the EL, EL2, and EL4 typically extend to within mv of positive and negative V supply rails with load currents of ma. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 27 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from ±V supply with a kω load connected to GND. The input is a V P-P sinusoid. The output voltage is approximately 9.8V P-P., T A = +2 C, A V =, V IN = V P-P V µs V OUTPUT INPUT FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL, EL2, and EL4 amplifiers, it is possible to exceed the +2 C 'absolute-maximum junction temperature' under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX T AMAX P DMAX = θ JA (EQ. ) FIGURE 27. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature Θ JA = Thermal resistance of the package P DMAX = Maximum power dissipation in the package FN79.7

12 The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P = DMAX ΣiV [ S I SMAX + ( V S + V OUT i ) I LOAD i ] (EQ. 2) when sourcing, and: P = DMAX ΣiV [ S I SMAX + ( V OUT i V S - ) I LOAD i ] (EQ. 3) when sinking, where: i = to 2 for dual and to 4 for quad V S = Total supply voltage I SMAX = Maximum supply current per amplifier V OUT i = Maximum output voltage of the application I LOAD i = Load current If we set the two P DMAX equations equal to each other, we can solve for R LOAD i to avoid device overheat. Figures 29 through 36 provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if P DMAX exceeds the device's power derating curves. To ensure proper operation, it is important to observe the recommended derating curves shown in Figures 29 through 36. POWER DISSIPATION (W).8 JEDEC JESD-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD mW HTSSOP4 θ JA = +44 C/W AMBIENT TEMPERATURE ( C) FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE EL, EL2, EL4 POWER DISSIPATION (W) JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD - HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD W HTSSOP4 θ JA = +38 C/W AMBIENT TEMPERATURE ( C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.2 TSSOP28. θ JA = +2 C/W TSSOP24 θ JA = +28 C/W.6.42W TSSOP2 977mW θ JA = +4 C/W.4 893mW 84mW θ JA = +48 C/W TSSOP6.2 78mW TSSOP4 θ JA = +6 C/W AMBIENT TEMPERATURE ( C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD TSSOP28 θ JA =+7 C/W TSSOP W θ JA =+8 C/W TSSOP2.8.47W θ JA =+9 C/W W.289W.2W TSSOP6 θ JA =+97 C/W TSSOP4 θ JA =+ C/W AMBIENT TEMPERATURE ( C) FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 2 FN79.7

13 .3 JEDEC JESD-3 LOW EFFECTIVE THERMAL CONDUCTIVITY (SINGLE LAYER) TEST BOARD.6 JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD POWER DISSIPATION (W) mW TSOT θ JA = +34 C/W POWER DISSIPATION (W) mW TSOT θ JA = +27 C/W AMBIENT TEMPERATURE ( C) FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.6 486mW HMSOP8 θ JA = +26 C/W POWER DISSIPATION (W) JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 87mW HMSOP8 θ JA = + C/W AMBIENT TEMPERATURE ( C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 36. AMBIENT TEMPERATURE ( C) PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Power Supply Bypassing and Printed Circuit Board Layout The EL, EL2, and EL4 can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to ground, a.µf ceramic capacitor should be placed from V S + to pin to V S - pin. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. 3 FN79.7

14 Thin Shrink Small Outline Package Family (TSSOP) C E.2 M C A B E B SEATING PLANE. C N LEADS e N D TOP VIEW b SIDE VIEW (N/2)+ (N/2) A PIN # I.D..2 C B A 2X N/2 LEAD TIPS.. M C A B H MDP44 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 4 LD 6 LD 2 LD 24 LD 28 LD TOLERANCE A Max A..... ±. A ±. b /-.6 c /-.6 D ±. E Basic E ±. e Basic L ±. L..... Reference Rev. F 2/7 NOTES:. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.mm per side. 2. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.2mm per side. SEE DETAIL X 3. Dimensions D and E are measured at datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-994. c END VIEW L A A2 A DETAIL X L - 8 GAUGE PLANE.2 4 FN79.7

15 HTSSOP (Heat-Sink TSSOP) Family E C.2 M C A B E B N EXPOSED THERMAL PAD SEATING PLANE. C N LEADS TOP VIEW D (N/2)+ (N/2). A EL, EL2, EL4 PIN # I.D..2 C B A 2X N/2 LEAD TIPS H e b D BOTTOM VIEW SIDE VIEW. M C A B E2 MDP48 HTSSOP (HEAT-SINK TSSOP) FAMILY SYMBOL MILLIMETERS 4 LD 2 LD 24 LD 28 LD 38 LD TOLERANCE A Max A ±.7 A /-. b /-.6 c /-.6 D ±. D Reference E Basic E ±. E Reference e Basic L ±. L..... Reference N Reference Rev. 3 2/7 NOTES:. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.mm per side. 2. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.2mm per side. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-994. SEE DETAIL X END VIEW c L A A2 A DETAIL X L - 8 GAUGE PLANE.2 FN79.7

16 TSOT Package Family 2 3. C D 2X C E SEATING PLANE e N. C A-B 2X A 6 2 e 4 (N/2) E D.2 C 2X N/2 TIPS B ddd M C A-B D b NX. C NX (L) D 3 H A A2 MDP49 TSOT PACKAGE FAMILY SYMBOL MILLIMETERS TSOT TSOT6 TSOT8 TOLERANCE A... Max A... ±. A ±.3 b ±.7 c /-.7 D Basic E Basic E Basic e Basic e Basic L ±. L Reference ddd N 6 8 Reference Rev. B 2/7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included. 2. Plastic interlead protrusions of.mm maximum per side are not included. 3. This dimension is measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M Index area - Pin # I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only). 6. TSOT version has no center lead (shown as a dashed line). A GAUGE PLANE.2 c L 4 ±4 6 FN79.7

17 HMSOP (Heat-Sink MSOP) Package Family E.2 M C A B B E N MDP HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY SYMBOL MILLIMETERS HMSOP8 HMSOP TOLERANCE NOTES D (N/2)+ A.. Max. - A /-. - A ±.9 - (N/2) PIN # I.D. TOP VIEW A b /-.8 - c.. ±. - D ±., 3 EXPOSED THERMAL PAD E2 D.8.8 Reference - E ±. - E ±. 2, 3 D E Reference - e.6. Basic - L.. ±. - L.9.9 Basic - BOTTOM VIEW N 8 Reference - PLANE C SEATING. C N LEADS e b SIDE VIEW H.8 M C A B Rev. 2/7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included. 2. Plastic interlead protrusions of.2mm maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-994. L A c END VIEW SEE DETAIL "X".2 GAUGE PLANE A2 3 ±3 L DETAIL X A 7 FN79.7

18 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA 2 3.(.2) e D.(.4) M C A M E -B- -Ab -C- SEATING PLANE A B S E.2(.) M B A α GAUGE PLANE.(.4).2. NOTES:. These package dimensions are within allowable dimensions of JEDEC MO-3-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y4.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side. A2 M L c 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (.6 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (.3 inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.27 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) M LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c D E e.26 BSC.6 BSC - E L N α o 8 o o 8 o - Rev. 2 4/6 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 8 FN79.7