DATASHEET EL5100, EL5101, EL5300. Features. Applications. 200MHz Slew Enhanced VFA. FN7330 Rev 3.00 Page 1 of 15. May 3, FN7330 Rev 3.

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1 DATASHEET EL, EL, EL MHz Slew Enhanced VFA The EL, EL, and EL represent high-speed voltage feedback amplifiers based on the current feedback amplifier architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. This family is available in single, dual, and triple versions, with MHz, MHz, and 7MHz versions. This family operates on single V or ±V supplies from minimum supply current. The EL and EL also feature an output enable function, which can be used to put the output in to a high-impedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. Features Pb-free plus anneal available (RoHS compliant) Specified for V or ±V applications Power-down to 7µA/amplifier -db bandwidth = MHz ±.db bandwidth = MHz Low supply current =.ma Slew rate = V/µs Low offset voltage = mv max Output current = ma A VOL = Diff gain/phase =.8%/. FN7 Rev. May, 7 Applications Video amplifiers PCMCIA applications A/D drivers Line drivers Portable computers High speed communications RGB applications Broadcast equipment Active filtering FN7 Rev. Page of May, 7

2 EL, EL, EL Ordering Information PART NUMBER PART MARKING TAPE AND REEL PACKAGE PKG. DWG. # ELIS IS - 8 Ld SOIC ( mil) MDP7 ELIS-T7 IS 7 8 Ld SOIC ( mil) MDP7 ELIS-T IS 8 Ld SOIC ( mil) MDP7 ELISZ (Note) ISZ - 8 Ld SOIC ( mil) (Pb-free) MDP7 ELISZ-T7 (Note) ISZ 7 8 Ld SOIC ( mil) (Pb-free) MDP7 ELISZ-T (Note) ISZ 8 Ld SOIC ( mil) (Pb-free) MDP7 ELIW-T7 y 7 (k pcs) 6 Ld SOT- MDP8 ELIW-T7A y 7 ( pcs) 6 Ld SOT- MDP8 ELIW-T7 7 (k pcs) Ld SOT- MDP8 ELIW-T7A 7 ( pcs) Ld SOT- MDP8 ELIU IU - 6 Ld QSOP ( mil) MDP ELIU-T7 IU 7 6 Ld QSOP ( mil) MDP ELIU-T IU 6 Ld QSOP ( mil) MDP ELIUZ (Note) IUZ - 6 Ld QSOP ( mil) (Pb-free) MDP ELIUZ-T7 (Note) IUZ 7 6 Ld QSOP ( mil) (Pb-free) MDP ELIUZ-T (Note) IUZ 6 Ld QSOP ( mil) (Pb-free) MDP NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN7 Rev. Page of May, 7

3 EL, EL, EL Pinouts EL (6 LD SOT-) TOP VIEW EL ( LD SOT-) TOP VIEW OUT 6 VS+ OUT VS+ IN+ + - ENABLE IN+ + - VS- IN- VS- IN- EL (8 LD SOIC) TOP VIEW EL (6 LD QSOP) TOP VIEW ENABLE VS+ OUT NC NC IN- IN+ VS- INA+ CEA VS- CEB 6 INA- OUTA VS+ OUTB INB+ INB- NC CEC INC NC OUTC 8 9 INC- FN7 Rev. Page of May, 7

4 EL, EL, EL Absolute Maximum Ratings (T A = + C) Supply Voltage between V S + and V S V Input Voltage ±V S Differential Input Voltage ±V Maximum Output Current mA Maximum Slewrate from V S + to V S V/µs Thermal Information Storage Temperature Range C to + C Ambient Operating Temperature Range C to +8 C Operating Junction Temperature C Pb-free reflow profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A DC Electrical Specifications V S = ±V, GND = V, T A = + C, V CM = V, V OUT = V, V ENABLE = GND or OPEN, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT V OS Offset Voltage - mv TCV OS Offset Voltage Temperature Coefficient Measured from T MIN to T MAX 8 µv/ C IB Input Bias Current V IN = V -6 6 µa I OS Input Offset Current V IN = V -... µa TCI OS Input Bias Current Temperature Coefficient Measured from T MIN to T MAX 8 na/ C PSRR Power Supply Rejection Ratio 7 9 db CMRR Common Mode Rejection Ratio V CM from -V to +V 6 7 db CMIR Common Mode Input Range Guaranteed by CMRR test - + V R IN Input Resistance V IN = -V to +V.7. M C IN Input Capacitance pf I S,ON Supply Current - Enabled Per amplifier...9 ma I S,OFF Supply Current - Shut Down V S +, per amplifier - µa V S -, per amplifier 7 µa PSOR Power Supply Operating Range. V AVOL Open Loop Gain R L = k to GND, V OUT from -.V to +.V 6 db V OP Positive Output Voltage Swing R L = to GND.. V R L = k to GND.6.8 V V ON Negative Output Voltage Swing R L = to GND V R L = k to GND V I OUT Output Current R L = to V ±6 ± ma V IH-EN ENABLE pin Voltage for Power Up V S + - V V IL-EN ENABLE pin Voltage for Shut Down V S + - V I EN Enable Pin Current Enabled, V EN = V - µa Disabled, V EN = V 7 µa FN7 Rev. Page of May, 7

5 EL, EL, EL Closed Loop AC Electrical SpecificationsV S = ±V, T A = C, V ENABLE = V, A V = +, R F =, R L = to GND, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT BW -db Bandwidth (V OUT = mv P-P ) V S = ±V, A V =, R F = MHz SR Slew Rate R L =, V OUT = -V to +V, A V = + V/µs t R,t F Rise Time, Fall Time ±.V step.8 ns OS Overshoot ±.V step % t PD Propagation Delay ±.V step. ns t S.% Settling Time V S = ±V, R L =, A V =, V OUT = ±.V ns dg Differential Gain A V =, R L =, V INDC = - to +V.8 % dp Differential Phase A V =, R L =, V INDC = - to +V. e N Input Noise Voltage f = khz nv/ Hz i N Input Noise Current f = khz 7 pa/ Hz t DIS Disable Time 8 ns t EN Enable Time 6 ns Typical Performance Curves A V =+ R L = SUPPLY=±.V ±.7 ±. ±. ±. ±. - K M M M G A V =+ R L = C IN -=pf SUPPLY=±.V 8.8pF 6.6pF.pF.pF pf - K M M M G FIGURE. GAIN vs FREQUENCY FOR VARIOUS C L FIGURE. GAIN vs FREQUENCY FOR VARIOUS CL A V =+ R L = C L =.pf R F =8 7.pF.pF.pF.8pF - K M M M 6M A V =+ R F =R G= 8 C L =.pf R L = 6.6pF.pF.pF pf - K M M M 6M FIGURE. GAIN vs FREQUENCY FOR VARIOUS C IN - FIGURE. GAIN vs FREQUENCY FOR VARIOUS C IN - FN7 Rev. Page of May, 7

6 EL, EL, EL Typical Performance Curves (Continued) A V =+ R F= 8 C L =.pf R L =.pf - K M M.pF 7.8pF M A V =+ R L = C L =.pf C IN -=pf SUPPLY=±.V - K M M M G FIGURE. GAIN vs FREQUENCY FOR VARIOUS C IN (-) FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS R L A V =+ R F= 8 C L =.pf R L = -. - K M M 7. M A V =+ C L =.pf K M M M 6M FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS R L FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS R L A V =+ R F =R G =8 C L =.pf R L = 8.k 7 K M M M 6M NOISE VOLRAGE (nv/ Hz) V S =±V K K K FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS R L FIGURE. EQUIVALENT INPUT VOLTAGE NOISE vs FREQUENCY FN7 Rev. Page 6 of May, 7

7 EL, EL, EL Typical Performance Curves (Continued) OPEN LOOP GAIN (db) V S =±V PHASE GAIN 6 K K K M M M M PHASE ( ) Z OUT ( ). V S =±V A V =+. K K M M M FIGURE. OPEN LOOP GAIN AND PHASE vs FREQUENCY FIGURE. Z OUT vs FREQUENCY PSRR (db) A V =+ V S =±V R L = -V S +V S -9 K K K M M M M CMRR (db) A V =+ V S =±V - K K K M M M M FIGURE. PSRR vs FREQUENCY FIGURE. CMRR vs FREQUENCY INPUT CH CH INPUT CH CH RISE.8ns CH OUTPUT CH CH FALL.ns CH OUTPUT CH CH RISE.787ns CH CH FALL.9ns CH=mV/DIV CH=mV/DIV TIME (ns/div) CH=mV/DIV CH=mV/DIV TIME (ns/div) FIGURE. LARGE SIGNAL RISE TIME FIGURE 6. LARGE SIGNAL FALL TIME FN7 Rev. Page 7 of May, 7

8 EL, EL, EL Typical Performance Curves (Continued) CH V CC V EE = V A V = R L = INPUT CH CH A V =+ R L = V S =±V CHANNEL CH CH RISE.77ns OUTPUT CH CH CHANNEL CH RISE.88ns CH=mV/DIV CH=mV/DIV CH=mV CH=mV TIME (ns/div) TIME (ns/div) FIGURE 7. SMALL SIGNAL RISE TIME FIGURE 8. SMALL SIGNAL RISE TIME CH CH INPUT CH OUTPUT CH V CC V EE = V A V = R L = CH FALL.6ns CH FALL.ns CURRENT NOISE (pa) CH=mV/DIV CH=mV/DIV TIME (ns/div) K K K FIGURE 9. SMALL SIGNAL FALL TIME FIGURE. CURRENT NOISE A V =+ R L = pf.pf 7.8pF.pF K M M M 6M R L = C IN -=pf.pf.6 pf 9pF.pF 7.8pF K M M M 6M FIGURE. GAIN vs FREQUENCY FOR VARIOUS C L FIGURE. GAIN vs FREQUENCY FOR VARIOUS C L FN7 Rev. Page 8 of May, 7

9 EL, EL, EL Typical Performance Curves (Continued) A V =+ R F= 8 R L = - K M M pf 8pF pf.pf 7pF M A V =+ R F= 8 R L = C IN =pf pf pf 8pF 6pF 7.8pF - K M M.pF M FIGURE. GAIN vs FREQUENCY FOR VARIOUS C L FIGURE. GAIN vs FREQUENCY FOR VARIOUS C L JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.8 JEDEC JESD- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. POWER DISSIPATION (W) W.6W mw SO8 JA = C/W SOT-/6 JA = C/W QSOP6 JA = C/W POWER DISSIPATION (W) mW 78mW 88mW QSOP6 JA =8 C/W SOT-/6 JA =6 C/W SO8 JA =6 C/W AMBIENT TEMPERATURE ( C) AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 6. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7 Rev. Page 9 of May, 7

10 EL, EL, EL DIFFERENTIAL GAIN (%) IRE FIGURE 7. DIFFERENTIAL GAIN (%) DIFFERENTIAL PHASE ( ) IRE FIGURE 8. DIFFERENTIAL PHASE ( ) FN7 Rev. Page of May, 7

11 EL, EL, EL Application Information Video Amplifier with Reduced Size Output Capacitance If you have a video line driver Z = 7, the DC decoupling capacitor could be relatively large. C = R f f = Hz, R = Z = 7, C = µf By using the circuit below, C could be reduced to C = µf. Vs+ C C n R8 R µf C6 C C R R K K U EL 6 R nf C R µf 7 k R Z = 7 C R7 7.µF R6 FIGURE 9. GAIN (db) Conditions/comments: () C = µf Vs = +V () C =.7µF Vs = +V () C =.7µF Vs = +V -.E+.E+.E+.E+6.E+8.E+.E+.E+.E+7.E+9 FIGURE. VIDEO- By selecting a different value for C, we could reduce the effect, created by C R and get flat response from 6Hz with an / value, price and size output capacitor. There is another, very important issue by using high bandwidth amplifiers. In the past when the bandwidth of the operational amplifier ended at a few hundred khz even at few MHz, the powersupply bypass was not a very critical issue, since a.µf capacitor did the job, but today s amplifiers could have bandwidth, what used to be reserved for microwave circuits not to long time ago. Therefore that high bandwidth amplifiers require the same respect what we reserve for microwave circuits. Particularly the power supply bypass and the pcb-layout could very heavily influence the performance of a modern high bandwidth amplifiers. It could happen above a few MHz, but it will happen above MHz, that the capacitor will behave like an inductor. The test result is shown on Figure. FN7 Rev. Page of May, 7

12 EL, EL, EL The reason for that is the very small but not zero value serial inductance of the capacitor. The impedance of a parallel tank circuit at resonance is dependent from it s Q. High Q high impedance. Z CAPACITIVE INDUCTIVE Ci Li The Q of a parallel tank circuit could be reduced by bypassing it with a resistor, or adding a resistor in serial to one of the reactive components. Since the bypassing would short the DC supply we do have to go to add resistor in serial to the reactive component, we will ad a resistor serial with the inductor. (See Figure.) F C F RES FIGURE. R = Z C L.µF The capacitor will behave as a capacitor up to its resonance frequency, above the resonance frequency it will behave as an inductor. Just nhy inductance serial with nf capacitance will have serial resonance at: F L C R = F RES F R to C = nf, L = nhy, F = 9 MHz And an other nhy is very easy to get together with the inductance of traces on the pcb, and therefore you could encounter resonances from ca MHz and above anywhere. So if the amplifier has a bandwidth of a few hundred MHz, the proper power supply by-pass could become a serious if not difficult task. Intuitively, you would use capacitors value.µf parallel with a few µf tantalum, and to cure the effect of it s serial resonance put a smaller one parallel to it. The result will surprise to you, because you will get even something worse than without the small capacitor. What is happening there? Just look what we get: FIGURE. The final power supply bypass circuit will look: Vs+ C C R n R µf C nf FIGURE. C C C C C C n.µf µf n.µf µf = L < L FIGURE. Above its serial resonance C* the ideal capacitance of C is a short, the Tantalum capacitor for high frequencies is not effective, the left over is C capacitor and L + L inductors, we get a parallel tank circuit, which is at it s resonance a high impedance path and do not carry any high frequency current, it does not work as bypass at all! FN7 Rev. Page of May, 7

13 EL, EL, EL Small Outline Package Family (SO) A D h X N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE.. C. M C A B b A DETAIL X L ± MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (. ) SO SO SO8 SYMBOL SO-8 SO- (. ) (SOL-6) (SOL-) (SOL-) (SOL-8) TOLERANCE NOTES A MAX - A A b c D , E E , e Basic - L L Basic - h Reference - N Reference - Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99 FN7 Rev. Page of May, 7

14 EL, EL, EL SOT- Package Family. C D X C E SEATING PLANE. C NX e N. C A-B X (L) A 6 e B. M C A-B D b NX D H E A D. C X A MDP8 SOT- PACKAGE FAMILY MILLIMETERS SYMBOL SOT- SOT-6 TOLERANCE A.. MAX A.. ±. A.. ±. b.. ±. c.. ±.6 D.9.9 Basic E.8.8 Basic E.6.6 Basic e.9.9 Basic e.9.9 Basic L.. ±. L.6.6 Reference N 6 Reference Rev. F /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. This dimension is measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99.. Index area - Pin # I.D. will be located within the indicated zone (SOT-6 only). 6. SOT- version has no center lead (shown as a dashed line). A GAUGE PLANE. c L + - FN7 Rev. Page of May, 7

15 EL, EL, EL Quarter Size Outline Plastic Packages Family (QSOP) A N D (N/)+ MDP QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP6 QSOP QSOP8 TOLERANCE NOTES E E PIN # I.D. MARK A Max. - A ±. - A ±. - b... ±. - B. C A B (N/) c ±. - D.9..9 ±., E ±.8 - C SEATING PLANE. C e.7 C A B b H E... ±., e... Basic - L... ±.9 - L... Basic - N 6 8 Reference - c L SEE DETAIL "X" A Rev. F /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M-99. A GAUGE PLANE. A DETAIL X L ± Copyright Intersil Americas LLC -7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN7 Rev. Page of May, 7