EL5172, EL MHz Differential Line Receivers. Features. Applications. Ordering Information. Pinouts FN Data Sheet August 3, 2005

Transcription

1 EL57, EL57 Data Sheet FN7.6 5MHz Differential Line Receivers The EL57 and EL57 are single and triple high bandwidth amplifiers designed to extract the difference signal from noisy environments. They are primarily targeted for applications such as receiving signals from twisted-pair lines or any application where common mode noise injection is likely to occur. The EL57 and EL57 are stable for a gain of one and requires two external resistors to set the voltage gain. The output common mode level is set by the reference pin (V REF ), which has a -db bandwidth of over MHz. Generally, this pin is grounded but it can be tied to any voltage reference. The output can deliver a maximum of ±6mA and is short circuit protected to withstand a temporary overload condition. The EL57 is available in the 8-pin SO and 8-pin MSOP packages and the EL57 in a -pin QSOP package. Both are specified for operation over the full - C to +85 C temperature range. Pinouts FB IN+ 7 VS- IN- REF EL57 (8-PIN SO, MSOP) TOP VIEW OUT 6 VS+ 5 EN REF INP INN NC REF INP INN NC REF INP INN NC EL57 (-PIN QSOP) TOP VIEW NC FB OUT NC VSP 9 VSN 8 NC 7 FB 6 OUT 5 EN FB OUT Features Differential input range ±.V 5MHz db bandwidth 8V/µs slew rate 6mA maximum output current Single 5V or dual ±5V supplies Low power - 5mA to 6mA per channel Pb-Free plus anneal available (RoHS compliant) Applications Twisted-pair receivers Differential line receivers VGA over twisted-pair ADSL/HDSL receivers Differential to single-ended amplification Reception of analog signals in a noisy environment Ordering Information PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # EL57IS 8-Pin SO - MDP7 EL57IS-T7 8-Pin SO 7 MDP7 EL57IS-T 8-Pin SO MDP7 EL57ISZ EL57ISZ-T7 EL57ISZ-T 8-Pin SO 8-Pin SO 8-Pin SO - MDP7 7 MDP7 MDP7 EL57IY 8-Pin MSOP - MDP EL57IY-T7 8-Pin MSOP 7 MDP EL57IY-T 8-Pin MSOP MDP EL57IYZ EL57IYZ-T7 EL57IYZ-T 8-Pin MSOP 8-Pin MSOP 8-Pin MSOP - MDP 7 MDP MDP EL57IU -Pin QSOP - MDP EL57IU-T7 -Pin QSOP 7 MDP EL57IU-T -Pin QSOP MDP EL57IUZ EL57IUZ-T7 EL57IUZ-T -Pin QSOP -Pin QSOP -Pin QSOP - MDP 7 MDP MDP NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. -5. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 EL57, EL57 Absolute Maximum Ratings (T A = 5 C) Supply Voltage (V S + to V S -) V Maximum Output Current ±6mA Storage Temperature Range C to +5 C Operating Junction Temperature C Ambient Operating Temperature C to +85 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, T A = 5 C, V IN = V, R L = 5Ω, R F =, R G = OPEN, C L =.7pF, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -db Bandwidth A V =, C L =.7pF 5 MHz A V =, R F = Ω, C L =.7pF 7 MHz A V =, R F = Ω, C L =.7pF MHz BW ±.db Bandwidth A V =, C L =.7pF 5 MHz SR Slew Rate V OUT = V P-P, % to 8%, EL V/µs V OUT = V P-P, % to 8%, EL V/µs T STL Settling Time to.% V OUT = V P-P ns T OVR Output Overdrive Recovery time ns GBWP Gain Bandwidth Product MHz V REF BW (-db) V REF -db Bandwidth A V =, C L =.7pF MHz V REF SR V REF Slew Rate V OUT = V P-P, % to 8% 6 V/µs V N Input Voltage Noise at f = khz 6 nv/ Hz I N Input Current Noise at f = khz pa/ Hz HD Second Harmonic Distortion V OUT = V P-P, 5MHz -66 dbc V OUT = V P-P, 5MHz -6 dbc HD Third Harmonic Distortion V OUT = V P-P, 5MHz -8 dbc V OUT = V P-P, 5MHz -76 dbc dg Differential Gain at.58mhz R L =, A V =. % dθ Differential Phase at.58mhz R L =, A V =. e S Channel Separation at khz EL57 only 9 db INPUT CHARACTERISTICS V OS Input Referred Offset Voltage ±7 ±5 mv I IN Input Bias Current (V IN, V INB, V REF ) µa R IN Differential Input Resistance kω C IN Differential Input Capacitance pf DMIR Differential Input Range ±. ±.8 ±.5 V CMIR Common Mode Input Range at V IN +, V IN V V REFIN Reference Input Voltage Range V IN + = V IN - = V -.6. V FN7.6

3 EL57, EL57 Electrical Specifications V S + = +5V, V S - = -5V, T A = 5 C, V IN = V, R L = 5Ω, R F =, R G = OPEN, C L =.7pF, unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT CMRR Input Common Mode Rejection Ratio V IN = ±.5V db Gain Gain Accuracy V IN = V OUTPUT CHARACTERISTICS V OUT Positive Output Voltage Swing R L = 5Ω to GND..6 V Negative Output Voltage Swing R L = 5Ω to GND V I OUT (Max) Maximum Output Current R L = Ω ±6 ±95 ma R OUT Output Impedance mω SUPPLY V SUPPLY Supply Operating Range V S + to V S -.75 V I S (on) Power Supply Current Per Channel - Enabled ma I S (off) + Positive Power Supply Current - Disabled EN pin tied to.8v, EL57 8 µa EN pin tied to.8v, EL µa I S (off) - Negative Power Supply Current - Disabled µa PSRR Power Supply Rejection Ratio V S from ±.5V to ±5.5V 5 58 db ENABLE t EN Enable Time 5 ns t DS Disable Time. µs V IH EN Pin Voltage for Power-up V S V IL EN Pin Voltage for Shut-down V S V V I IH-EN EN Pin Input Current High Per Channel At V EN = 5V 6 µa I IL-EN EN Pin Input Current Low Per Channel At V EN = V - - µa FN7.6

4 EL57, EL57 Pin Descriptions EL57 EL57 PIN NAME PIN FUNCTION FB Feedback input IN+ Non-inverting input IN- Inverting input REF Sets the common mode output voltage level 5 EN Enabled when this pin is floating or the applied voltage V S VS+ Positive supply voltage 7 VS- Negative supply voltage 8 OUT Output voltage, 5, 9 REF,, Reference input, controls common-mode output voltage, 6, INP,, Non-inverting inputs, 7, INN,, Inverting inputs, 8,, 8,, NC No connect, grounded for best crosstalk performance, 6, OUT,, Non-inverting outputs, 7, FB,, Feedback from outputs 5 EN Enabled when this pin is floating or the applied voltage V S VSN Negative supply VSP Positive supply FN7.6

5 Connection Diagrams R G R F =Ω -5V FB OUT 8 VOUT 5 FN7.6 REF INP INN REF INP INN REF INP INN R SP R SN R SR R SP R SN R SR INP INN REF R S R SP R S R SN R S R SR INP INN REF VSN VSP EN EL57 REF NC INP FB INN OUT NC NC 5 REF VSP 6 INP VSN 9 7 INN NC 8 8 NC FB 7 9 REF OUT 6 INP EN 5 INN FB NC OUT EL57 R G R G +5V R G R F R F R F ENABLE C L.7pF +5V -5V R L 5Ω EN C L.7pF C L.7pF C L.7pF R L 5Ω R L 5Ω R L 5Ω OUT OUT OUT EL57, EL57

6 EL57, EL57 Typical Performance Curves A V =, R L = 5Ω, C L =.7pF A V =, R L = Ω, C L =.7pF MAGNITUDE (db) V S = ±5V MAGNITUDE (db) V S = ±5V - -5 V S = ±.5V - -5 V S = ±.5V -6 M M M G -6 M M M G FIGURE. FREQUENCY RESPONSE vs SUPPLY VOLTAGE FIGURE. FREQUENCY RESPONSE vs SUPPLY VOLTAGE NORMALIZED GAIN (db) V S = ±5V, R L = 5Ω, C L =.7pF - A V = - - A V = A V = 5 - A V = -5-6 M M M G MAGNITUDE (db) V S = ±5V, A V =, R L = 5Ω 5 C L = 56pF C L = pf C L = 5pF - - C L = pf C L =.7pF M M M G FIGURE. FREQUENCY RESPONSE vs VARIOUS GAIN FIGURE. FREQUENCY RESPONSE vs C L V S = ±5V, A V =, R L = 5Ω 5 C L = 56pF V S = ±5V, A V =, R L = 5Ω, C L =.7pF MAGNITUDE (db) C L = pf C L =.7pF C L = pf C L = 5pF NORMALIZED GAIN (db) R F = kω R F = 5Ω R F = Ω M M M G -6 M M M G FIGURE 5. FREQUENCY RESPONSE vs C L FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS R F 6 FN7.6

7 EL57, EL57 Typical Performance Curves (Continued) NORMINALIZED GAIN (db) A V =, R L = 5Ω, C L =.7pF V S = ±5V V S = ±.5V M M M G FIGURE 7. FREQUENCY RESPONSE FOR V REF GAIN (db) K K M M M 5M FIGURE 8. OPEN LOOP GAIN PHASE ( ) - IMPEDENCE (Ω) PSRR (db) PSRR+ -7. K K M M M -8 PSRR- -9 K K K M M M FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY FIGURE. PSRR vs FREQUENCY CMRR (db) K M M M G FIGURE. CMRR vs FREQUENCY VOLTAGE NOISE (nv/ Hz), CURRENT NOISE (pa/ Hz) K E N I N K K K M M FIGURE. VOLTAGE AND CURRENT NOISE vs FREQUENCY 7 FN7.6

8 EL57, EL57 Typical Performance Curves (Continued) GAIN (db) CH <=> CH, CH <=> CH CH <=> CH -9 - K M M M G DISTORTION (db) V S = ±5V, R L = 5Ω, f = 5MHz HD (A V = ) -8 HD (A V = ) HD (A V = ) HD (A V = ) V OP-P (V) FIGURE. CHANNEL ISOLATION vs FREQUENCY FIGURE. HARMONIC DISTORTION vs OUTPUT VOLTAGE DISTORTION (db) V S = ±5V, f = 5MHz, V OP-P = V =, V OP-P = V = HD (A V = ) HD (A V = ) HD (A V = ) HD (A V = ) R LOAD (Ω) DISTORTION (db) V S = ±5V, R L = 5Ω, V OP-P = V for A V =, V OP-P = V for A V = HD (A V = ) HD (A V = ) HD (A V = ) HD (A V = ) FREQUENCY (MHz) FIGURE 5. HARMONIC DISTORTION vs LOAD RESISTANCE FIGURE 6. HARMONIC DISTORTION vs FREQUENCY 5mV/DIV.5V/DIV ns/div ns/div FIGURE 7. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 8. LARGE SIGNAL TRANSIENT RESPONSE 8 FN7.6

9 EL57, EL57 Typical Performance Curves (Continued) M = ns, CH = mv/div, CH = 5V/DIV M = ns, CH = mv/div, CH = 5V/DIV CH CH CH CH ns/div ns/div FIGURE 9. ENABLED RESPONSE FIGURE. DISABLED RESPONSE JEDEC JESD5- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. POWER DISSIPATION (W) mW 65mW 86mW MSOP8 θ JA =6 C/W QSOP θ JA =5 C/W SO8 θ JA =6 C/W POWER DISSIPATION (W) W 99mW 87mW MSOP8/ θ JA =5 C/W QSOP θ JA =88 C/W SO8 θ JA = C/W AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Simplified Schematic V S + I I I I R R R D R D VIN+ Q VIN- Q FBP Q FBN Q Q 7 Q 8 V B Q 9 x V OUT 5 Q 6 V B C C R R V S - 9 FN7.6

10 EL57, EL57 Description of Operation and Application Information Product Description The EL57 and EL57 are wide bandwidth, low power and single/differential ended to single ended output amplifiers. The EL57 is a single channel differential to single ended amplifier. The EL57 is a triple channel differential to single ended amplifier. The EL57 and EL57 are internally compensated for closed loop gain of + of greater. Connected in gain of and driving a 5Ω load, the EL57 and EL57 have a -db bandwidth of 5MHz. Driving a load at gain of, the bandwidth is about 5MHz. The bandwidth at the REF input is about 5MHz. The EL57 and EL57 is available with a power down feature to reduce the power while the amplifier is disabled. Input, Output, and Supply Voltage Range The EL57 and EL57 have been designed to operate with a single supply voltage of 5V to V or a split supplies with its total voltage from 5V to V. The amplifiers have an input common mode voltage range from -.V to.v for ±5V supply. The differential mode input range (DMIR) between the two inputs is about from -.V to +.V. The input voltage range at the REF pin is from -.6V to.v. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. The output of the EL57 and EL57 can swing from -.8V to.6v at 5Ω load at ±5V supply. As the load resistance becomes lower, the output swing is reduced respectively. Over All Gain Settings The gain setting for the EL57 and EL57 is similar to the conventional operational amplifier. The output voltage is equal to the difference of the inputs plus V REF and then times the gain. V O ( VIN + V IN - V R F = + REF) R G Choice of Feedback Resistor and Gain Bandwidth Product For applications that require a gain of +, no feedback resistor is required. Just short the OUT pin to FB pin. For gains greater than +, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, R F has some maximum value that should not be exceeded for optimum performance. If a large value of R F must be used, a small capacitor in the few Pico farad range in parallel with R F can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL57 and EL57 depends on the load and the feedback network. R F and R G appear in parallel with the load for gains other than +. As this combination gets smaller, the bandwidth falls off. Consequently, R F also has a minimum value that should not be exceeded for optimum bandwidth performance. For gain of +, R F = is optimum. For the gains other than +, optimum response is obtained with R F between 5Ω to kω. For A V = and R F = R G = kω, the BW is about 8MHz and the frequency response is very flat. The EL57 and EL57 have a gain bandwidth product of MHz. For gains 5, its bandwidth can be predicted by the following equation: Gain BW = MHz Driving Capacitive Loads and Cables The EL57 and EL57 can drive 56pF capacitance in parallel with 5Ω load to ground with db of peaking at gain of +. If less peaking is desired in applications, a small series resistor (usually between 5Ω to ) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than, the gain resistor R G can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. V IN + V IN - V REF FB EN Σ G/B V O When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. R G R F FIGURE. Disable/Power-Down The EL57 and EL57 can be disabled and placed its outputs in a high impedance state. The turn off time is about.µs and the turn on time is about 5ns. When disabled, the amplifier's supply current is reduced to 8µA for I S + and FN7.6

11 EL57, EL57 µa for I S - typically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard CMOS signal levels at the ENABLE pin. The applied logic signal is relative to V S + pin. Letting the EN pin float or applying a signal that is less than.5v below V S + will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above V S + -.5V. If a TTL signal is used to control the enabled/disabled function, Figure could be used to convert the TTL signal to CMOS signal. CMOS/TTL K K FIGURE. Output Drive Capability The EL57 and EL57 have internal short circuit protection. Its typical short circuit current is ±95mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±6mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL57 and EL57. It is possible to exceed the 5 C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T JMAX T AMAX PD MAX = Θ JA T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature θ JA = Thermal resistance of the package Assume the REF pin is tired to GND for V S = ±5V application, the maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: 5V EN For sourcing: V OUT PD MAX = V S I SMAX + ( V S + V OUT ) i R LOAD For sinking: PD MAX = [ V S I SMAX + ( V OUT V S - ) I LOAD ] i Where: V S = Total supply voltage I SMAX = Maximum quiescent supply current per channel V OUT = Maximum output voltage of the application R LOAD = Load resistance I LOAD = Load current i = Number of channels By setting the two PD MAX equations equal to each other, we can solve the output current and R LOAD to avoid the device overheat. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a.µf ceramic capacitor from V S + to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V S - pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. FN7.6

12 EL57, EL57 Typical Applications Ω EL57/ EL57 or EL57/ EL Z O = Ω V FB V IN V INB V REF EL57/ EL57 V OUT FIGURE 5. TWISTED PAIR CABLE RECEIVER As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. R C R R Gain (db) + R / R Z O = Ω V FB V IN V INB V REF EL57/ EL57 V OUT + R / (R + R ) f A f C f Level Shifter and Signal Summer The EL57 and EL57 contains two pairs of differential pair input stages. It makes the inputs are all high impedance inputs. To take advantage of the two high impedance inputs, the EL57 and EL57 can be used as a signal summer to add two signals together. Like, one signal can be applied to VIN+, the second signal can be applied to REF and V IN - is ground. The output is equal to: FIGURE 6. COMPENSATED LINE RECEIVER V O = ( V IN + + V REF ) Gain Also, the EL57 and EL57 can be used as a level shifter by applying a level control signal to the REF input. FN7.6

13 EL57, EL57 SO Package Outline Drawing FN7.6

14 EL57, EL57 MSOP Package Outline Drawing FN7.6

15 EL57, EL57 QSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 5 FN7.6