EL5150, EL5151, EL5250, EL5251, EL5451

Transcription

1 EL, EL, EL, EL, EL Data Sheet January 6, 8 FN78.7 MHz Amplifiers The EL, EL, EL, EL, and EL are MHz bandwidth db voltage mode feedback amplifiers with DC accuracy of.%, mv offsets and kv/v open loop gains. These amplifiers are ideally suited for applications ranging from precision measurement instrumentation to high speed video and monitor applications. Capable of operating with as little as.ma of current from a single supply ranging from V to V, dual supplies ranging from ±.V to ±.V, these amplifiers are also well suited for handheld, portable and batterypowered equipment. Single amplifiers are offered in SOT packages and duals in a Ld MSOP package for applications where board space is critical. Quad amplifiers are available in a Ld SOIC package. Additionally, singles and duals are available in the industrystandard 8 Ld SOIC package. All parts operate over the industrial temperature range of C to 8 C. Pinouts EL (8 LD SOIC) TOP VIEW EL (6 LD SOT) TOP VIEW Features MHz db bandwidth 67V/µs slew rate Very high open loop gains kv/v Low supply current =.ma Single supplies from V to V Dual supplies from ±.V to ±V Fast disable on the EL and EL Low cost Pbfree available (RoHS compliant) Applications Imaging Instrumentation Video Communications devices EL ( LD SOT) TOP VIEW NC 8 CE OUT 6 VS OUT VS IN IN 7 6 VS OUT IN CE IN VS IN VS IN VS NC EL ( LD MSOP) TOP VIEW EL (8 LD MSOP) TOP VIEW EL ( LD SOIC) TOP VIEW INA INA OUTA 8 VS OUTA OUTD CEA VS CEB OUTA VS OUTB 7 6 INA INA VS OUTB INB INB INA INA VS IND IND VS INB 6 INB INB INC INC INB 6 9 OUTB 7 8 OUTC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 888INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 8. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 EL, EL, EL, EL, EL Ordering Information PART NUMBER PART MARKING PACKAGE PKG. DWG. # ELIS IS 8 Ld SOIC MDP7 ELIST7* IS 8 Ld SOIC (Tape and Reel) MDP7 ELIST* IS 8 Ld SOIC (Tape and Reel) MDP7 ELISZ (Note) ISZ 8 Ld SOIC (Pbfree) MDP7 ELISZT7* (Note) ISZ 8 Ld SOIC (Tape and Reel) (Pbfree) MDP7 ELISZT* (Note) ISZ 8 Ld SOIC (Tape and Reel) (Pbfree) MDP7 ELIWT7* BEAA 6 Ld SOT (Tape and Reel) MDP8 ELIWT7A* BEAA 6 Ld SOT (Tape and Reel) MDP8 ELIWZT7* (Note) BAAJ 6 Ld SOT (Tape and Reel) (Pbfree) MDP8 ELIWZT7A* (Note) BAAJ 6 Ld SOT (Tape and Reel) (Pbfree) MDP8 ELIWT7* BFAA Ld SOT (Tape and Reel) MDP8 ELIWT7A* BFAA Ld SOT (Tape and Reel) MDP8 ELIWZT7* (Note) BAAK Ld SOT (Tape and Reel) (Pbfree) MDP8 ELIWZT7A* (Note) BAAK Ld SOT (Tape and Reel) (Pbfree) MDP8 ELIY BAEAA Ld MSOP MDP ELIYT7* BAEAA Ld MSOP (Tape and Reel) MDP ELIYT* BAEAA Ld MSOP (Tape and Reel) MDP ELIS IS 8 Ld SOIC MDP7 ELIST7* IS 8 Ld SOIC (Tape and Reel) MDP7 ELIST* IS 8 Ld SOIC (Tape and Reel) MDP7 ELISZ (Note) ISZ 8 Ld SOIC (Pbfree) MDP7 ELISZT* (Note) ISZ 8 Ld SOIC (Tape and Reel) (Pbfree) MDP7 ELISZT7* (Note) ISZ 8 Ld SOIC (Tape and Reel) (Pbfree) MDP7 ELIY BAFAA 8 Ld MSOP MDP ELIYT7* BAFAA 8 Ld MSOP (Tape and Reel) MDP ELIYT* BAFAA 8 Ld MSOP (Tape and Reel) MDP ELIYZ (Note) BBBHA 8 Ld MSOP (Pbfree) MDP ELIYZT* (Note) BBBHA 8 Ld MSOP (Tape and Reel) (Pbfree) MDP ELIYZT7* (Note) BBBHA 8 Ld MSOP (Tape and Reel) (Pbfree) MDP ELIS IS Ld SOIC MDP7 ELIST7* IS Ld SOIC (Tape and Reel) MDP7 ELIST* IS Ld SOIC (Tape and Reel) MDP7 ELISZ (Note) ISZ Ld SOIC (Pbfree) MDP7 ELISZT7* (Note) ISZ Ld SOIC (Tape and Reel) (Pbfree) MDP7 ELISZT* (Note) ISZ Ld SOIC (Tape and Reel) (Pbfree) MDP7 *Please refer to TB7 for details on reel specifications. NOTE: These Intersil Pbfree plastic packaged products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate PLUS ANNEAL e termination finish, which is RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD. FN78.7 January 6, 8

3 EL, EL, EL, EL, EL Absolute Maximum Ratings (T A = C) Supply Voltage between V S and V S V Slewrate of Voltage between V S and V S V/µs Maximum Continuous Output Current ma Pin Voltages GND.V to V S.V Current into I N, I N, CE ma Thermal Information Junction Temperature C to C Storage Temperature C to C Ambient Operating Temperature C to 8 C Power Dissipation See Curves PbFree Reflow Profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S = V, V S = V, R L = Ω, T A = C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW db Bandwidth A V =, MHz A V =, R L = Ω MHz GBWP Gain Bandwidth Product A V = MHz BW.dB Bandwidth A V =, MHz SR Slew Rate V O = ±.V, A V = 67 V/µs V O = ±.V, A V =, V/µs t S.% Settling Time V OUT = V to V, A V = 8 ns dg Differential Gain Error (Note ) A V =, R L = Ω. % dp Differential Phase Error (Note ) A V =, R L = Ω.9 V N Input Referred Voltage Noise nv/ Hz I N Input Referred Current Noise. pa/ Hz DC PERFORMANCE V OS Offset Voltage. mv T C V OS Input Offset Voltage Temperature Coefficient Measured from T MIN to T MAX µv/ C A VOL Open Loop Gain 6 kv/v INPUT CHARACTERISTICS CMIR Common Mode Input Range Guaranteed by CMRR test.. V CMRR Common Mode Rejection Ratio 8 db I B Input Bias Current na I OS Input Offset Current 6 na R IN Input Resistance 8 7 MΩ C IN Input Capacitance pf OUTPUT CHARACTERISTICS V OUT Output Voltage Swing Low R L = Ω to GND ±. ±.8 V to GND ±. ±. V I OUT Output Current R L = Ω to GND ± ±7 ma FN78.7 January 6, 8

4 EL, EL, EL, EL, EL Electrical Specifications V S = V, V S = V, R L = Ω, T A = C, unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT ENABLE (SELECTED PACKAGES ONLY) t EN Enable Time EL ns t DIS Disable Time EL 6 ns I IHCE CE Pin Input High Current CE = V S µa I ILCE CE Pin Input Low Current CE = V S V µa V IHCE CE Input High Voltage for Powerdown Disable V S V V ILCE CE Input Low Voltage for Powerdown Enable V S V SUPPLY I SON Supply Current Enabled (per amplifier) No load, V IN = V, CE = V...6 ma I SOFF Supply Current Disabled (per amplifier) µa I SOFF Supply Current Disabled (per amplifier) No load, V IN = V µa PSRR Power Supply Rejection Ratio DC, V S = ±.V to ±6.V 8 db NOTE:. Standard NTSC test, AC signal amplitude = 86mV PP, f =.8MHz, V OUT is swept from.8v to.v, R L is DCcoupled. Typical Performance Curves 8 GAIN (db) PHASE ( ) PHASE ( ) A V = R L = Ω R F = Ω A V = R F =.kω A V = R F = Ω 8 k k k M M M G 7 k M M M G FIGURE. EL FREQUENCY vs OPEN LOOP GAIN/PHASE FIGURE. PHASE vs FREQUENCY FOR VARIOUS GAINS FN78.7 January 6, 8

5 EL, EL, EL, EL, EL Typical Performance Curves (Continued) A V = R L = Ω R L = Ω V S = ±V A V = R F = R G = Ω R L = Ω R L = kω R L = Ω R L = Ω k M M M G. FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS R L FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS R L A V = R F =.kω R L = Ω R L = Ω A V = C L = 8.pF C L =.9pF C L = pf R L = Ω 6 k M M M k M M M M FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS R L FIGURE 6. EL GAIN vs FREQUENCY FOR VARIOUS C L A V = R F = R G = Ω C L = 68pF C L = 7pF C L = pf C L = pf A V = R F =.kω C L = 8pF C L = 68pF C L = 7pF C L = pf k M M M k M M M FIGURE 7. EL GAIN vs FREQUENCY FOR VARIOUS C L FIGURE 8. EL GAIN vs FREQUENCY FOR VARIOUS C L FN78.7 January 6, 8

6 EL, EL, EL, EL, EL Typical Performance Curves (Continued) A V = C C IN =.7pF IN = 8pF C IN = pf C IN = 8.pF C IN =.pf C IN = pf C IN = pf A V = R F = R G = Ω C IN = pf C IN = 8.pF C IN =.9pF C IN = pf k M M M M 6 k M M M FIGURE 9. EL GAIN vs FREQUENCY FOR VARIOUS C IN FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS C IN 6 k A V = R F =.kω C IN = pf C IN = 68pF C IN = 8.pF C IN = 8pF C IN =.pf C IN = pf M C IN = pf M M 6 k A V = R F =.kω R L = Ω R L = Ω R L = Ω M R L = Ω M M FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS C IN FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS R L A V = R F = R G = kω R F = R G = kω R F = R G = kω R F = R G = Ω R F = R G = Ω A V = A V = A V = k M M M 6 k M M M M FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS R F /R G FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS GAINS 6 FN78.7 January 6, 8

7 EL, EL, EL, EL, EL Typical Performance Curves (Continued) BOTH CHANNELS SHOWN A V = A V = A V = PSRR (db) 6 8 A V = POSITIVE SUPPLY 6 k M M M k k k M M M FIGURE. EL GAIN vs FREQUENCY FOR VARIOUS GAINS FREQUENCY RESPONSE (Hz) FIGURE 6. PSRR vs FREQUENCY PSRR (db) 6 A V = NEGATIVE SUPPLY CROSSTALK (db) 6 7 A V = IN CHANNEL A OUT CHANNEL B 8 8 k k k M M M 9 k M M M FREQUENCY RESPONSE (Hz) FIGURE 7. PSRR vs FREQUENCY FIGURE 8. EL CROSSTALK vs FREQUENCY CROSSTALK (db) 6 7 A V = IN CHANNEL B OUT CHANNEL A IMPEDANCE (Ω).k... A V = 8. 9 k M M M. k k k M M M FIGURE 9. EL CROSSTALK vs FREQUENCY FIGURE. OUTPUT IMPEDANCE 7 FN78.7 January 6, 8

8 EL, EL, EL, EL, EL Typical Performance Curves (Continued) CMRR (db) 6 8 A V = NORMALIZED GROUP DELAY (ps/div) A V = k k k M M M M M M 6M FIGURE. CMRR FIGURE. GROUP DELAY SUPPLY CURRENT (ma) A V = VOLTAGE NOISE (nv/ Hz) CURRENT NOISE (pa/ Hz) SUPPLY VOLTAGE (V) FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE. k k k FIGURE. VOLTAGE CURRENT NOISE vs FREQUENCY 9 DISTORTION (dbc) RD HD ND HD A V = C L =.pf FREQ =.9MHz SLEW RATE (V/µs) OUTPUT SWING (V PP ) SPLIT POWER SUPPLY (V) FIGURE. DISTORTION vs OUTPUT AMPLITUDE FIGURE 6. SLEW RATE vs POWER SUPPLY 8 FN78.7 January 6, 8

9 EL, EL, EL, EL, EL Typical Performance Curves (Continued) THD (dbc) 6 A V = V S = ±V R F = Ω THD_Fin = khz THD_Fin = MHz HARMONIC DISTORTION (dbc) 6 A V = V S = ±V R F = Ω V OUT = V PP RD HD THD ND HD OUTPUT VOLTAGE (V PP ) FIGURE 7. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGE 7... FUNDAMENTAL FREQUENCY (MHz) FIGURE 8. HARMONIC DISTORTION vs FREQUENCY VOLTAGE (mv/div) A V = C L =.pf %8% CH RISE.87ns 8%% CH FALL.6ns VOLTAGE (mv/div) A V = C L =.pf %8% CH RISE.7ns 8%% CH FALL.8ns TIME (ns/div) TIME (ns/div) FIGURE 9. SMALL SIGNAL STEP RESPONSE FIGURE. LARGE SIGNAL STEP RESPONSE VOLTAGE (mv/div) A V = R L =Ω C L =.pf %8% CH RISE.7ns 8%% CH FALL 6.9ns VOLTAGE (mv/div) A V = R L = Ω C L =.pf %8% CH RISE.87ns 8%% CH FALL.67ns TIME (ns/div) FIGURE. SMALL SIGNAL STEP RESPONSE TIME (ns/div) FIGURE. LARGE SIGNAL STEP RESPONSE 9 FN78.7 January 6, 8

10 EL, EL, EL, EL, EL Typical Performance Curves (Continued) A V = SUPPLY = ±.V, ±.7mA CH CH CH ns ENABLE 6ns DISABLE 8ns ENABLE ns DISABLE TIME (ns/div) TIME (µs/div) FIGURE. EL ENABLE/DISABLE FIGURE. EL ENABLE/DISABLE DIFFERENTIAL GAIN (%) DIFFERENTIAL PHASE ( ) IRE IRE FIGURE. DIFFERENTIAL GAIN FIGURE 6. DIFFERENTIAL PHASE A V = ±6.V ±.V ISOSLATION (db) 7 9 A V = C L =.7pF 6 k M M M M k M M M M FIGURE 7. SMALL SIGNAL FREQUENCY vs SUPPLY FIGURE 8. INPUTTOOUTPUT ISOLATION WITH PART DISABLED FN78.7 January 6, 8

11 EL, EL, EL, EL, EL Typical Performance Curves (Continued) JEDEC JESD7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. JEDEC JESD LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD POWER DISSPIATION (W)...6W 99mW SO θ JA = 88 C/W.8 87mW SO8 θ JA = C/W.6 mw. MSOP8/ θ JA = C/W. SOT/6 θ JA = C/W 7 8 POWER DISSPIATION (W) mW 6mW 86mW 9mW SOT/6 θ JA = 6 C/W SO θ JA = C/W SO8 θ JA = 6 C/W MSOP8/ θ JA = 6 C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Product Description The EL, EL, EL, EL and EL are wide bandwidth, low power, low offset voltage feedback operational amplifiers capable of operating from a single or dual power supplies. This family of operational amplifiers are internally compensated for closed loop gain of or greater. Connected in voltage follower mode, driving a Ω load members of this amplifier family demonstrate a db bandwidth of about MHz. With the loading set to accommodate typical video application, Ω load and gain set to, bandwidth reduces to about MHz with a 67V/µs slew rate. Power down pins on the EL and EL reduce the already low power demands of this amplifier family to µa typical while the amplifier is disabled. Input, Output and Supply Voltage Range The EL and family members have been designed to operate with supply voltage ranging from V to V. Supply voltages range from ±.V to ±V for split supply operation. And of course split supply operation can easily be achieved using single supplies with by splitting off half of the single supply with a simple voltage divider as illustrated in the application circuit section. Input Common Mode Range These amplifiers have an input common mode voltage ranging from.v above the negative supply (V S pin) to.v below the positive supply (V S pin). If the input signal is driven beyond this range the output signal will exhibit distortion. Maximum Output Swing & Load Resistance The outputs of the EL and family members exhibit maximum output swing ranges from V to V for V S = ±V with a load resistance of Ω. Naturally, as the load resistance becomes lower, the output swing lowers accordingly; for instance, if the load resistor is Ω, the output swing ranges from.v to.v. This response is a simple application of Ohms law indicating a lower value resistance results in greater current demands of the amplifier. Additionally, the load resistance affects the frequency response of this family as well as all operational amplifiers; as clearly indicated by the Gain vs Frequency For Various R L curves clearly indicate. In the case of the frequency response reduced bandwidth with decreasing load resistance is a function of load resistance in conjunction with the output zero response of the amplifier. Choosing A Feedback Resistor A feedback resistor is required to achieve unity gain; simply short the output pin to the inverting input pin. Gains greater than require a feedback and gain resistor to set the desired gain. This gets interesting because the feedback resistor forms a pole with the parasitic capacitance at the inverting input; as the feedback resistance increases the position of the pole shifts in the frequency domain, the amplifier's phase margin is reduced and the amplifier becomes less stable. Peaking in the frequency domain and ringing in the time domain are symptomatic of this shift in pole location. So we want to keep the feedback resistor as small as possible. You may want to use a large feedback resistor for some reason; in this case to compensate the shift of the pole and maintain stability a small capacitor in the few Pico farad range in parallel with the feedback resistor is recommended. For the gains greater than unity it has been determined a feedback resistance ranging from Ω to 7Ω provides optimal response. FN78.7 January 6, 8

12 EL, EL, EL, EL, EL Gain Bandwidth Product The EL and family members have a gain bandwidth product of MHz for a gain of. Bandwidth can be predicted by the following equation: (Gain) x (BW) = GainBandwidthProduct Video Performance For good video performance, an amplifier is required to maintain the same output impedance and same frequency response as DC levels are changed at the output; this characteristic is widely referred to as diffgaindiffphase. Many amplifiers have a difficult time with this especially while driving standard video loads of Ω, as the output current has a natural tendency to change with DC level. The dg and dp for these families is a respectable.% and.9, while driving Ω at a gain of. Driving high impedance loads would give a similar or better dg and dp performance as the current output demands placed on the amplifier lessen with increased load. Driving Capacitive Loads These devices can easily drive capacitive loads as demanding as 7pF in parallel with Ω while holding peaking to within db of peaking at unity gain. Of course if less peaking is desired, a small series resistor (usually between Ω to Ω) can be placed in series with the output to eliminate most peaking; however, there will be a small sacrifice of gain which can be recovered by simply adjusting the value of the gain resistor. Driving Cables Both ends of all cables must always be properly terminated; double termination is absolutely necessary for reflectionfree performance. Additionally, a backtermination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a backtermination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/PowerDown Devices with disable can be disabled with their output placed in a high impedance state. The turn off time is about ns and the turn on time is about ns. When disabled, the amplifier's supply current is reduced to 7µA typically; essentially eliminating power consumption. The amplifier's power down is controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to V S pin. Letting the ENABLE pin float or the application of a signal that is less than.8v above V S enables the amplifier. The amplifier is disabled when the signal at ENABLE pin is above V S.V. Output Drive Capability Members of the EL family do not have internal short circuit protection circuitry. Typically, short circuit currents ranging from 7mA and 9mA can be expected and naturally, if the output is shorted indefinitely the part can easily be damaged from overheating; or excessive current density may eventually compromise metal integrity. Maximum reliability is maintained if the output current is always held below ±ma. This limit is set and limited by the design of the internal metal interconnect. Note that in transient applications, the part is extremely robust. Power Dissipation With the high output drive capability of these devices, it is possible to exceed the C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation : T JMAX T AMAX PD MAX = (EQ. ) Θ JA Where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature θ JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing: n V OUTi PD MAX = V S I SMAX ( V S V OUTi ) (EQ. ) R Li i = For sinking: PD MAX = V S I SMAX ( V OUTi V S ) I (EQ. ) LOADi Where: V S = Supply voltage I SMAX = Maximum quiescent supply current V OUT = Maximum output voltage of the application R LOAD = Load resistance tied to ground I LOAD = Load current i = N = number of amplifiers (Max = ) n By setting the two PD MAX equations equal to each other, we can solve the output current and R LOAD to avoid the device overheat. FN78.7 January 6, 8

13 EL, EL, EL, EL, EL Power Supply Bypassing Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as short as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S pin is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a.µf ceramic capacitor from V S to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V S pin becomes the negative supply rail. Printed Circuit Board Layout For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. Application Circuits Sallen Key Low Pass Filter A common and easy to implement filter taking advantage of the wide bandwidth, low offset and low power demands of the EL. A derivation of the transfer function is provided for convenience (see Figure ). Sallen Key High Pass Filter Again, this useful filter benefits from the characteristics of the EL. The transfer function is very similar to the low pass so only the results are presented (see Figure ). V R k R k C n RA C n k RB k V UA V V V.µF R7 V OUT k RB K = RA Vo = K V RCs Vo V Vi Vo Vi K V = R R Cs K H(s) = RC R Cs (( K)RC RC RC )s H(jw) = w RC R C jw(( K)RC RC RC) Holp = K wo = RC R C Q = RC RC RC ( K) RC RC RC V V.µF Holp = K wo = RC Q = K Equations simplify if we let all components be equal R = C FIGURE. SALLEN KEY LOW PASS FILTER FN78.7 January 6, 8

14 EL, EL, EL, EL, EL V V.µF V C7 n C9 n C n R8 k k UA V V R7 V OUT k Holp = K wo = RC R C Q = RC RC ( K) RC RC RC RC RA k RB V V.µF K Holp = K wo = RC Q = K Equations simplify if we let all components be equal R = C FIGURE. SALLEN KEY HIGH PASS FILTER Differential Output Instrumentation Amplifier The addition of a third amplifier to the conventional three amplifier Instrumentation Amplifier introduces the benefits of differential signal realization; specifically the advantage of using common mode rejection to remove coupled noise and ground potential errors inherent in remote transmission. This configuration also provides enhanced bandwidth, wider output swing and faster slew rate than conventional three amplifier solutions with only the cost of an additional amplifier and few resistors. e A R R G R R R R A R R e o REF e o R A e o e A R R e o = ( R R G )( e e ) e o = ( R R G )( e e ) e o = ( R R G )( e e ) BW f C, = A Di A Di = ( R R G ) FN78.7 January 6, 8

15 EL, EL, EL, EL, EL Strain Gauge The strain gauge is an ideal application to take advantage of the moderate bandwidth and high accuracy of the EL. The operation of the circuit is very straightforward. As the strain variable component resistor in the balanced bridge is subjected to increasing strain, its resistance changes resulting in an imbalance in the bridge. A voltage variation from the referenced high accuracy source is generated and translated to the difference amplifier through the buffer stage. This voltage difference as a function of the strain is converted into an output voltage. V V.µF VARIABLE SUBJECT TO STRAIN k V V R k R R k R7 k R8 k k UA V V RL k V OUT (VVVV) RF.µF V V FN78.7 January 6, 8

16 Small Outline Package Family (SO) A EL, EL, EL, EL, EL D h X N (N/) E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE.. C. M C A B b A DETAIL X L ± MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (. ) SO SO SO8 SYMBOL SO8 SO (. ) (SOL6) (SOL) (SOL) (SOL8) TOLERANCE NOTES A MAX A ±. A ±. b ±. c ±. D ±., E ±.8 E ±., e Basic L ±.9 L Basic h Reference N Reference Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M99 6 FN78.7 January 6, 8

17 EL, EL, EL, EL, EL SOT Package Family. C D X C E SEATING PLANE. C NX e N. C AB X (L) A 6 e B. M C AB D b NX D H E A D. C X A MDP8 SOT PACKAGE FAMILY MILLIMETERS SYMBOL SOT SOT6 TOLERANCE A.. MAX A.. ±. A.. ±. b.. ±. c.. ±.6 D.9.9 Basic E.8.8 Basic E.6.6 Basic e.9.9 Basic e.9.9 Basic L.. ±. L.6.6 Reference N 6 Reference Rev. F /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. This dimension is measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M99.. Index area Pin # I.D. will be located within the indicated zone (SOT6 only). 6. SOT version has no center lead (shown as a dashed line). A GAUGE PLANE. c L 7 FN78.7 January 6, 8

18 EL, EL, EL, EL, EL Mini SO Package Family (MSOP). M C A B A D (N/) N MDP MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL MSOP8 MSOP TOLERANCE NOTES A.. Max. A.. ±. E E PIN # I.D. A ±.9 b...7/.8 c.8.8 ±. B (N/) D.. ±., E.9.9 ±. E.. ±., C e H e.6. Basic L.. ±. SEATING PLANE. C N LEADS c L b SEE DETAIL "X".8 M C A B A L.9.9 Basic N 8 Reference Rev. D /7 NOTES:. Plastic or metal protrusions of.mm maximum per side are not included.. Plastic interlead protrusions of.mm maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M99. A GAUGE PLANE. A L DETAIL X ± All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 8 FN78.7 January 6, 8