DATASHEET EL5127, EL5227, EL5327, EL5427. Features. Applications. 2.5MHz 4-, 8-, 10- and 12-Channel Rail-to-Rail Buffers. FN7111 Rev 4.

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1 .5MHz -, 8-, - and -Channel Rail-to-Rail Buffers The EL57, EL57, EL57, and EL57 are low power, high voltage rail-to-rail input/output buffers designed for use in reference voltage buffering applications in small LCD displays. They are available in quad (EL57), octal (EL57), -Channel (EL57), and -Channel (EL57) topologies. All buffers feature a -db bandwidth of.5mhz and operate from just µa per buffer. This family also features a continuous output drive capability of ma (sink and source). The quad channel EL57 is available in the Ld MSOP package. The 8-Channel EL57 is available in both the Ld TSSOP and Ld QFN packages, the -Channel EL57 in the Ld TSSOP and Ld QFN packages, and the -Channel EL57 in the 8 Ld TSSOP and Ld QFN packages. All buffers are specified for operation over the full - C to +85 C temperature range. NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at -888-INTERSIL or Features.5MHz -db bandwidth Supply voltage =.5V to 6.5V Low supply current (per buffer) = µa High slew rate =.V/µs Rail-to-rail input/output swing Ultra-small packages DATASHEET Pb-free plus anneal available (RoHS compliant) Applications TFT-LCD drive circuits Electronic games Touch-screen displays Personal communication devices Personal digital assistants (PDAs) Portable instrumentation FN7 Rev. FN7 Rev. Page of 7

2 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL57CY R - Ld MSOP (.mm) MDP EL57CY-T7 R 7 Ld MSOP (.mm) MDP EL57CY-T R Ld MSOP (.mm) MDP EL57CYZ (Note) BAAAH - Ld MSOP (.mm) (Pb-Free) MDP EL57CYZ-T7 (Note) BAAAH 7 Ld MSOP (.mm) (Pb-Free) MDP EL57CYZ-T (Note) BAAAH Ld MSOP (.mm) (Pb-Free) MDP EL57CL 57CL - Ld QFN (mmx5mm) MDP6 EL57CL-T7 57CL 7 Ld QFN (mmx5mm) MDP6 EL57CL-T 57CL Ld QFN (mmx5mm) MDP6 EL57CLZ (Note) 57CLZ - Ld QFN (mmx5mm) (Pb-Free) MDP6 EL57CLZ-T7 (Note) 57CLZ 7 Ld QFN (mmx5mm) (Pb-Free) MDP6 EL57CLZ-T (Note) 57CLZ Ld QFN (mmx5mm) (Pb-Free) MDP6 EL57CR 57CR - Ld TSSOP (.mm) MDP EL57CR-T7 57CR 7 Ld TSSOP (.mm) MDP EL57CR-T 57CR Ld TSSOP (.mm) MDP EL57CRZ (Note) 57CRZ - Ld TSSOP (.mm) (Pb-Free) M.7 EL57CRZ-T7 (Note) 57CRZ 7 Ld TSSOP (.mm) (Pb-Free) M.7 EL57CRZ-T (Note) 57CRZ Ld TSSOP (.mm) (Pb-Free) M.7 EL57CL 57CL - Ld QFN (mmx5mm) MDP6 EL57CL-T7 57CL 7 Ld QFN (mmx5mm) MDP6 EL57CL-T 57CL Ld QFN (mmx5mm) MDP6 EL57CLZ (Note) 57CLZ - Ld QFN (mmx5mm) (Pb-Free) MDP6 EL57CLZ-T7 (Note) 57CLZ 7 Ld QFN (mmx5mm) (Pb-Free) MDP6 EL57CLZ-T (Note) 57CLZ Ld QFN (mmx5mm) (Pb-Free) MDP6 EL57CR 57CR - Ld TSSOP (.mm) MDP EL57CR-T7 57CR 7 Ld TSSOP (.mm) MDP EL57CR-T 57CR Ld TSSOP (.mm) MDP EL57CRZ (Note) 57CRZ - Ld TSSOP (.mm) (Pb-Free) MDP EL57CRZ-T7 (Note) 57CRZ 7 Ld TSSOP (.mm) (Pb-Free) MDP EL57CRZ-T (Note) 57CRZ Ld TSSOP (.mm) (Pb-Free) MDP EL57CL 57CL - Ld QFN (5mmx6mm) MDP6 EL57CL-T7 57CL 7 Ld QFN (5mmx6mm) MDP6 EL57CL-T 57CL Ld QFN (5mmx6mm) MDP6 EL57CLZ (Note) 57CLZ - Ld QFN (5mmx6mm) (Pb-Free) MDP6 EL57CLZ-T7 (Note) 57CLZ 7 Ld QFN (5mmx6mm) (Pb-Free) MDP6 FN7 Rev. Page of 7

3 Ordering Information (Continued) PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL57CLZ-T (Note) 57CLZ Ld QFN (5mmx6mm) (Pb-Free) MDP6 EL57CR 57CR - 8 Ld TSSOP (.mm) MDP EL57CR-T 57CR 8 Ld TSSOP (.mm) MDP EL57CRZ (Note) 57CRZ - 8 Ld TSSOP (.mm) (Pb-Free) MDP EL57CRZ-T7 (Note) 57CRZ 7 8 Ld TSSOP (.mm) (Pb-Free) MDP EL57CRZ-T (Note) 57CRZ 8 Ld TSSOP (.mm) (Pb-Free) MDP NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN7 Rev. Page of 7

4 Pinouts EL57 ( LD MSOP) TOP VIEW EL57 ( LD TSSOP) TOP VIEW EL57 ( LD TSSOP) TOP VIEW EL57 (8 LD TSSOP) TOP VIEW VIN VOUT VIN VOUT VIN VOUT VIN 8 VOUT VIN 9 VOUT VIN 9 VOUT VIN VOUT VIN 7 VOUT 8 VS- VIN 8 VOUT VIN VOUT VIN 6 VOUT VIN 7 VOUT VIN 7 VOUT VIN VOUT VIN 5 VOUT VIN 5 6 VOUT 5 6 VS- VIN5 5 VOUT5 VIN5 5 VOUT VS- 9 VS- VIN6 6 VOUT6 VIN5 7 VOUT VS- VS- VIN6 8 VOUT6 VIN6 8 7 VOUT6 8 VS- VIN7 9 VOUT7 VIN7 9 6 VOUT7 VIN7 9 VOUT7 VIN8 VOUT8 VIN8 5 VOUT8 VIN8 9 VOUT8 VIN9 VOUT9 VIN9 8 VOUT9 VIN VOUT VIN 7 VOUT VIN 6 VOUT VIN 5 VOUT EL57, EL57 ( LD QFN) TOP VIEW EL57 ( LD QFN) TOP VIEW VIN VIN* NC VOUT* VOUT VIN VIN NC NC NC VOUT VOUT VIN VIN VIN5 VIN6 VIN7 VIN VIN9 9 CVIN* NC THERMAL PAD VOUT* VOUT9 VIN VIN VIN5 VIN6 VIN7 VIN8 VIN9 VIN THERMAL PAD VOUT 8 VOUT 7 VOUT5 6 VS- 5 VOUT6 VOUT7 VOUT8 5 VOUT VOUT VOUT5 VOUT6 VS- VOUT7 9 VOUT8 8 VOUT9 7 VOUT * NOT AVAILABLE IN EL57 VIN VIN NC NC NC VOUT VOUT FN7 Rev. Page of 7

5 Absolute Maximum Ratings (T A = +5 C) Supply Voltage Between V S + and V S V Input Voltage V S - -.5V, V S +.5V Maximum Continuous Output Current ma ESD Voltage kV Thermal Information Maximum Die Temperature C Storage Temperature C to +5 C Power Dissipation See Curves Operating Temperature C to +85 C Pb-free reflow profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, R L = k, C L = pf to V, T A = +5 C, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = V 5 mv TCV OS Average Offset Voltage Drift (Note ) 5 µv/ C I B Input Bias Current V CM = V 5 na R IN Input Impedance G C IN Input Capacitance.5 pf A V Voltage Gain -.5V V OUT.5V.99. V/V OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -5mA V V OH Output Swing High I L = +5mA V I OUT (max) Max Output Current (Note ) R L = ± ma POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from ±.5V to ±7.75V 55 8 db I S Supply Current No load (EL57).7.9 ma No load (EL57).. ma No load (EL57). ma No load (EL57).6. ma DYNAMIC PERFORMANCE SR Slew Rate (Note ) -.V V OUT.V, % to 8%.9. V/µs t S Settling to +.% (A V = +) (A V = +), V O = V step 9 ns BW -db Bandwidth R L = k, C L = pf.5 MHz CS Channel Separation f = khz 75 db NOTES:. Measured over operating temperature range.. Instantaneous peak current.. Slew rate is measured on rising and falling edges. FN7 Rev. Page 5 of 7

6 Electrical Specifications V S + = +5V, V S - = V, R L = k, C L = pf to.5v, T A = +5 C, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM =.5V 5 mv TCV OS Average Offset Voltage Drift (Note ) 5 µv/ C I B Input Bias Current V CM =.5V 5 na R IN Input Impedance G C IN Input Capacitance.5 pf A V Voltage Gain.5V V OUT.5V.99. V/V OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -5mA 8 5 mv V OH Output Swing High I L = +5mA V I OUT (max) Output Current (Note 5) R L = ± ma POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from.5v to 5.5V 55 8 db I S Supply Current No load (EL57).7.9 ma No load (EL57)..5 ma No load (EL57).5.9 ma No load (EL57).5.5 ma DYNAMIC PERFORMANCE SR Slew Rate (Note 6) V V OUT V, % to 8%.9.5 V/µs t S Settling to +.% (A V = +) (A V = +), V O = V step ns BW -db Bandwidth R L = k, C L = pf.5 MHz CS Channel Separation f = 5MHz 75 db NOTES:. Measured over operating temperature range. 5. Instantaneous peak current. 6. Slew rate is measured on rising and falling edges. FN7 Rev. Page 6 of 7

7 Electrical Specifications V S + = +5V, V S - = V, R L = k, C L = pf to 7.5V, T A = +5 C, Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 7.5V 8 mv TCV OS Average Offset Voltage Drift (Note 7) 5 µv/ C I B Input Bias Current V CM = 7.5V 5 na R IN Input Impedance G C IN Input Capacitance.5 pf AV Voltage Gain.5V V OUT.5V.99. V/V OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -5mA 5 5 mv V OH Output Swing High I L = +5mA V I OUT (max) Output Current (Note 8) R L = ± ma POWER SUPPLY PERFORMANCE PSRR Power Supply Rejection Ratio V S is moved from.5v to 5.5V 55 8 db I S Supply Current No load (EL57) ma No load (EL57)..55 ma No load (EL57).5. ma No load (EL57).6. ma DYNAMIC PERFORMANCE SR Slew Rate (Note 9) V V OUT V, % to 8%.9. V/µs t S Settling to +.% (A V = +) (A V = +), V O = V step 9 ns BW -db Bandwidth R L = k, C L = pf.5 MHz CS Channel Separation f = 5MHz 75 db NOTES: 7. Measured over operating temperature range. 8. Instantaneous peak current. 9. Slew rate is measured on rising and falling edges. FN7 Rev. Page 7 of 7

8 Typical Performance Curves NORMALIZED MAGNITUDE (db) - - C L =pf k 56 5 k NORMALIZED MAGNITUDE (db) - - R L =k nf pf 7pF pf - K K K M M - K K K M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. FREQEUNCY RESPONSE FOR VARIOUS R L FIGURE. FREQUENCY RESPONSE FOR VARIOUS C L OUTPUT IMPEDANCE ( ) 6 8 T A =5 C K K K M MAXIMUM OUTPUT SWING (V P-P ) 8 6 R L =k C L =pf T A =5 C K K M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. OUTPUT IMPEDANCE vs FREQUENCY FIGURE. MAXIMUM OUTPUT SWING vs FREQUENCY. VOLTAGE NOISE (nv/ Hz) THD + NOISE (%) K K K M M M K K K FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 5. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY FN7 Rev. Page 8 of 7

9 Typical Performance Curves OVERSHOOT (%) R L =k V IN =±5mV T A =5 C K % OF BUFFERS CAPACITANCE (pf) FIGURE 7. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE INPUT OFFSET VOLTAGE (mv) FIGURE 8. INPUT OFFSET VOLTAGE DISTRIBUTION INPUT BIAS CURRENT (na) OUTPUT HIGH VOLTAGE (V) I OUT =5mA TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE FIGURE. OUTPUT HIGH VOLTAGE vs TEMPERATURE OUTPUT LOW VOLTAGE (V) I OUT =-5mA VOLTAGE GAIN (V/V) TEMPERATURE ( C) TEMPERATURE ( C) FIGURE. OUTPUT LOW VOLTAGE vs TEMPERATURE FIGURE. VOLTAGE GAIN vs TEMPERATURE FN7 Rev. Page 9 of 7

10 Typical Performance Curves SLEW RATE (V/µs) SUPPLY CURRENT (ma) TEMPERATURE ( C) TEMPERATURE ( C) FIGURE. SLEW RATE vs TEMPERATURE FIGURE. SUPPLY CURRENT PER CHANNEL vs TEMPERATURE.95 T A =5 C SUPPLY CURRENT (ma) V/DIV SUPPLY VOLTAGE (V) 8 µs/div FIGURE 5. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE FIGURE 6. LARGE SIGNAL TRANSIENT RESPONSE JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.857W mv/div POWER DISSIPATION (W) W 87mW QFN JA =7 C/W MSOP JA =5 C/W QFN JA =5 C/W µs/div AMBIENT TEMPERATURE ( C) FIGURE 7. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7 Rev. Page of 7

11 Typical Performance Curves POWER DISSIPATION (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.W TSSOP8 JA =75 C/W.W.76W TSSOP JA =9 C/W TSSOP JA =85 C/W POWER DISSIPATION (W) JEDEC JESD5- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.8 758mW.7 7mW.6 QFN JA = C/W.5 86mW. QFN JA = C/W. MSOP. JA =6 C/W AMBIENT TEMPERATURE ( C) AMBIENT TEMPERATURE ( C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD5- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.9 8mW.8 78mW.7.6 7mW TSSOP8 JA = C/W.5. TSSOP JA =8 C/W... TSSOP JA = C/W AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Applications Information Product Description The EL57, EL57, EL57, and EL57 unity gain buffers are fabricated using a high voltage CMOS process. It exhibits rail-to-rail input and output capability and has low power consumption (µa per buffer). These features make the EL57, EL57, EL57, and EL57 ideal for a wide range of general-purpose applications. When driving a load of k and pf, the EL57, EL57, EL57, and EL57 have a -db bandwidth of.5mhz and exhibits.v/µs slew rate. Operating Voltage, Input, and Output The EL57, EL57, EL57, and EL57 are specified with a single nominal supply voltage from 5V to 5V or a split supply with its total range from 5V to 5V. Correct operation is guaranteed for a supply range of.5v to 6.5V. Most EL57, EL57, EL57, and EL57 specifications are stable over both the full supply range and operating temperatures of - C to +85 C. Parameter variations with operating voltage and/or temperature are shown in the typical performance curves. The output swings of the EL57, EL57, EL57, and EL57 typically extend to within 8mV of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure shows the input and output waveforms for the device. Operation is from ±5V supply with a k load connected to GND. The input is a V P-P sinusoid. The output voltage is approximately 9.985V P-P. FN7 Rev. Page of 7

12 5V µs application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: 5V T A =5 C V IN =V P-P OUTPUT INPUT T JMAX - T AMAX P DMAX = JA where: T JMAX = Maximum junction temperature FIGURE. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT Short Circuit Current Limit The EL57, EL57, EL57, and EL57 will limit the short circuit current to ±ma if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±ma. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The EL57, EL57, EL57, and EL57 are immune to phase reversal as long as the input voltage is limited from V S - -.5V to V S + +.5V. Figure shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than.6v, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. V µs T AMAX = Maximum ambient temperature JA = Thermal resistance of the package P DMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = iv S I SMAX + V S + - V OUT i I LOAD i when sourcing, and: P = DMAX when sinking. where: iv S I SMAX + i = to Total number of buffers V S = Total supply voltage V i - V OUT S - I LOAD i I SMAX = Maximum quiescent current per channel V OUT i = Maximum output voltage of the application I LOAD i = Load current V V S =±.5V T A =5 C V IN =6V P-P FIGURE. OPERATION WITH BEYOND-THE-RAILS INPUT Power Dissipation With the high-output drive capability of the EL57, EL57, EL57, and EL57 buffer, it is possible to exceed the +5 C absolute-maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the If we set the two P DMAX equations equal to each other, we can solve for R LOAD i to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if P DMAX exceeds the device's power derating curves. Unused Buffers It is recommended that any unused buffer have the input tied to the ground plane. FN7 Rev. Page of 7

13 Driving Capacitive Loads The EL57, EL57, EL57, and EL57 can drive a wide range of capacitive loads. As load capacitance increases, however, the -db bandwidth of the device will decrease and the peaking increase. The buffers drive pf loads in parallel with k with just.5db of peaking, and pf with 6.dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5 and 5 ) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a snubber circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 5 and nf are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - pin is connected to ground, a.µf ceramic capacitor should be placed from V S + pin to V S - pin. A.7µF tantalum capacitor should then be connected from V S + pin to ground. One.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. FN7 Rev. Page of 7

14 Mini SO Package Family (MSOP).5 M C A B A D (N/)+ N MDP MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL MSOP8 MSOP TOLERANCE NOTES A.. Max. - A.. ±.5 - E E PIN # I.D. A ±.9 - b.. +.7/-.8 - c.8.8 ±.5 - B (N/) D.. ±., E.9.9 ±.5 - E.. ±., C e H e.65.5 Basic - L ±.5 - SEATING PLANE. C N LEADS c L b SEE DETAIL "X".8 M C A B A L Basic - N 8 Reference - Rev. D /7 NOTES:. Plastic or metal protrusions of.5mm maximum per side are not included.. Plastic interlead protrusions of.5mm maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99. A GAUGE PLANE.5 A L DETAIL X ± FN7 Rev. Page of 7

15 QFN (Quad Flat No-Lead) Package Family A X.75 C (E) C SEATING PLANE N LEADS L N (N-) (N-) b (N/) e PIN # I.D. MARK TOP VIEW (N/). M C A B (N-) (N-) N BOTTOM VIEW A DETAIL X. C.8 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW C A (c) D (D) 7 (L) NE N LEADS E B X.75 C PIN # I.D. 5 MDP6 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-) MILLIMETERS SYMBOL QFN QFN QFN TOLERANCE NOTES A ±. - A /-. - b ±. - c.... Reference - D Basic - D /.8 Reference 8 E Basic - E /. Reference 8 e Basic - L ±.5 - N 8 Reference ND Reference 6 NE 8 9 Reference 5 MILLIMETERS TOLER- SYMBOL QFN8 QFN QFN QFN6 ANCE NOTES A ±. - A / -. - b ±. - c..... Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ±.5 - N 8 6 Reference ND Reference 6 NE Reference 5 Rev /7 NOTES:. Dimensioning and tolerancing per ASME Y.5M-99.. Tiebar view shown is a non-functional feature.. Bottom-side pin # I.D. is a diepad chamfer as shown.. N is the total number of terminals on the device. 5. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN7 Rev. Page 5 of 7

16 Thin Shrink Small Outline Package Family (TSSOP) C E.5 M C A B E B SEATING PLANE. C N LEADS e N D TOP VIEW b SIDE VIEW SEE DETAIL X (N/)+ (N/) A PIN # I.D.. C B A X N/ LEAD TIPS.5. M C A B H MDP THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL LD 6 LD LD LD 8 LD TOLERANCE A..... Max A..... ±.5 A ±.5 b /-.6 c /-.6 D ±. E Basic E..... ±. e Basic L ±.5 L..... Reference Rev. F /7 NOTES:. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.5mm per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm per side.. Dimensions D and E are measured at datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99. c END VIEW L A A A DETAIL X L - 8 GAUGE PLANE.5 FN7 Rev. Page 6 of 7

17 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA.5(.) e D.(.) M C A M E -B- -Ab -C- SEATING PLANE A B S E.5(.) M B A GAUGE PLANE.(.).5. NOTES:. These package dimensions are within allowable dimensions of JEDEC MO-5-AC, Issue E.. Dimensioning and tolerancing per ANSI Y.5M-98.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.5mm (.6 inch) per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm (.6 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be.8mm (. inch) total in excess of b dimension at maximum material condition. Minimum space between protrusion and adjacent lead is.7mm (.7 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) A M L c M.7 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b c D E e.6 BSC.65 BSC - E L N 7 o 8 o o 8 o - Rev. 6/98 Copyright Intersil Americas LLC -7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN7 Rev. Page 7 of 7