Data Sheet September 3, Features TEMP. RANGE ( C)

Transcription

1 Data Sheet FN6387. Power Line Communication (PLC) The ISL57 is a dual operational amplifier designed for PLC line driving in OFDM and SSC based solutions. This device features a high drive capability of 750mA while consuming only 6mA of supply current per amplifier and operating from a single 4.5V to 2V supply. The driver achieves a typical distortion of -80dBc, at 50kHz into a 25Ω load. The ISL57 is available in the thermally-enhanced 6 Ld QFN or 0 Ld HMSOP package and is specified for operation over the full -40 C to +85 C temperature range. The ISL57 has control pins BIAS 0 and BIAS for controlling the bias and enable/disable of the outputs. These controls allow for lowering the power to fit the performance/power ratio for the application. The ISL57 is ideal for line driving applications following the Homeplug.0, Homeplug AV and UPA standard based PLC. Features 2dBm output power capability Drives up to 750mA from a +2V supply 20V P-P differential output drive into 2Ω Very low noise floor -75dBc typical driver output distortion at 4MHz -80dBc typical driver output distortion at 0MHz -79dBc typical driver output distortion at 7MHz Low quiescent current of 6mA per amplifier Supply range - For ISL57IUEZ 4.5V to 2V - For ISL57IRZ ±2.25V to ±6V, 4.5V to 2V 250MHz bandwidth Thermal shutdown Pb-free (RoHS compliant) Ordering Information PART NUMBER (Note) PART MARKING TEMP. RANGE ( C) Applications Homeplug.0 Homeplug AV UPA digital home standard PACKAGE (Pb-Free) PKG. DWG. # ISL57IRZ 57 IRZ -40 to Ld QFN MDP0046 ISL57IRZ-T7* 57 IRZ -40 to Ld QFN (Tape and Reel) MDP0046 ISL57IUEZ BBBDA -40 to Ld HMSOP MDP0050 ISL57IUEZ-T7* BBBDA -40 to Ld HMSOP (Tape and Reel) MDP0050 *Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 00% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 Pinouts ISL57 6 LD QFN TOP VIEW ISL57 (0 LD HMSOP) TOP VIEW OUTA VS+ OUTB VS+ 0 OUTB INB- 2 3 V S- * 2 0 INA- INA+ INB- INB+ OUTA 3 INA- 4 V S- * 8 INB+ 7 BIAS INA+ 5 6 BIAS 0 GND 4 9 BIAS VS- BIAS 0 *THERMAL PAD MUST BE CONNECTED TO NEGATIVE SUPPLY: V S-. QFN PACKAGE CAN BE USED IN SINGLE AND DUAL SUPPLY APPLICATIONS. *THERMAL PAD MUST BE CONNECTED TO NEGATIVE SUPPLY: V S-. HMSOP PACKAGE CAN BE USED IN SINGLE SUPPLY APPLICATIONS ONLY. Pin Descriptions 6 LD QFN 0 LD HMSOP PIN NAME FUTION, 5, 6, 2, 5 2 No Connect 2 4 INA- Inverting Input of Amplifier A 3 5 INA+ Non-Inverting Input of Amplifier A 4 Thermal Pad GND Ground Connect 7 Thermal Pad VS- Negative Supply 8 6 BIAS 0 (Note ) Current Control Bias Pin 9 7 BIAS (Note ) Current Control Bias Pin 0 8 INB+ Non-Inverting Input of Amplifier B 9 INB- Inverting Input of Amplifier B 3 0 OUTB Output of Amplifier B 4 VS+ Positive Supply 6 3 OUTA Output of Amplifier A NOTE:. Single DSL port is comprised of amplifiers A and B. BIAS 0 and BIAS control I S settings for the DSL port. 2 FN6387.

3 pplications Information Absolute Maximum Ratings (T A = +25 C) V S + Voltage to Ground V to +3.2V V IN + Voltage GND to V S + Current into any Input mA Continuous Output Current mA BIAS 0, BIAS to Ground V ESD Rating Human Body Model kv* Charge Device Model kV Thermal Information Ambient Operating Temperature Range C to +85 C Storage Temperature Range C to +50 C Operating Junction Temperature C Power Dissipation See Curves Pb-free Reflow Profile see link below *Excludes C0 and C pins which show less than kv of HBM ESD sensitivity. CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S = 2V,, R L-DIFF = 50Ω, BIAS 0 = BIAS = 0V, T A = +25 C, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMAE BW -3dB Bandwidth, A V = MHz, A V = MHz THD Total Harmonic Distortion, Differential f = 4MHz, V O = 4V P-P_DIFF, R L-DIFF = 00Ω -75 dbc f = 0MHz, V O = 4V P-P_DIFF, R L-DIFF = 00Ω -80 dbc f = 7MHz, V O = 4V P-P_DIFF, R L-DIFF = 00Ω -79 dbc SR Slew Rate, Single-ended V OUT from -3V to +3V V/µs DC PERFORMAE V OS_CM Offset Voltage Common Mode mv V OS_DM Offset Voltage Differential Mode mv R OL Differential Transimpedance V OUT = 2V P-P differential, unloaded 3.0 MΩ INPUT CHARACTERISTICS I B + Non-Inverting Input Bias Current µa I B - DM Inverting Input Bias Current Differential Mode µa e N Input Noise Voltage 6 nv Hz i N -Input Noise Current 3 pa/ Hz OUTPUT CHARACTERISTICS V OUT Loaded Output Swing (single ended), R L DIFF = 50Ω ±4.8 ±5.0 V, R L DIFF = 20Ω ±4.35 ±4.7 V I OUT Output Current R L = 0Ω 000 ma SUPPLY V S Supply Voltage Single supply V I S + (Full Bias) Positive Supply Current per Amplifier All outputs at 0V, BIAS 0 = BIAS = 0V ma I S + (Medium Bias) Positive Supply Current per Amplifier All outputs at 0V, BIAS 0 = 5V, BIAS = 0V ma I S + (Low Bias) Positive Supply Current per Amplifier All outputs at 0V, BIAS 0 = 0V, BIAS = 5V 6.0 ma I S + (Power-down) Positive Supply Current per Amplifier All outputs at 0V, BIAS 0 = BIAS = 5V ma I INH, BIAS 0 or BIAS BIAS 0, BIAS Input Current, High BIAS 0, BIAS = 6V µa I INL, BIAS 0 or BIAS BIAS 0, BIAS Input Current, Low BIAS 0, BIAS = 0V µa V INH, BIAS 0 or BIAS BIAS 0, BIAS Input Voltage, High 2.0 V V INL, BIAS 0 or BIAS BIAS 0, BIAS Input Voltage, Low 0.8 V 3 FN6387.

4 Typical Performance Curves R F = kω R F = kω FIGURE. DIFFERENTIAL FREQUEY RESPONSE WITH VARIOUS R F (FULL BIAS MODE) FIGURE 2. DIFFERENTIAL FREQUEY RESPONSE WITH VARIOUS R F (MEDIUM BIAS MODE) A V = 0 R F = kω R F = kω FIGURE 3. DIFFERENTIAL FREQUEY RESPONSE WITH VARIOUS R F (LOW BIAS MODE) FIGURE 4. DIFFERENTIAL FREQUEY RESPONSE WITH VARIOUS R F (FULL BIAS MODE) A V = 0 A V = 0 R F = kω R F = kω FIGURE 5. DIFFERENTIAL FREQUEY RESPONSE WITH VARIOUS R F (MEDIUM BIAS MODE) FIGURE 6. DIFFERENTIAL FREQUEY RESPONSE WITH VARIOUS R F (LOW BIAS MODE) 4 FN6387.

5 Typical Performance Curves (Continued) c) V O(P-P) = 4V DIFFERENTIAL VOLTAGE OUTPUT P-P FIGURE 7. HARMONIC 2MHz FIGURE 8. 2ND AND 3RD HARMONIC DISTORTION vs R 2MHz V O(P-P) = 4V DIFFERENTIAL VOLTAGE OUTPUT P-P FIGURE 9. HARMONIC 3MHz FIGURE 0. 2ND AND 3RD HARMONIC DISTORTION vs R 3MHz V OPP = 4V DIFFERENTIAL VOLTAGE OUTPUT P-P FIGURE. HARMONIC 5MHz FIGURE 2. 2ND AND 3RD HARMONIC DISTORTION vs R 5MHz 5 FN6387.

6 Typical Performance Curves (Continued) c) V OPP = 4V DIFFERENTIAL VOLTAGE OUTPUT P-P FIGURE 3. HARMONIC 0MHz FIGURE 4. 2ND AND 3RD HARMONIC DISTORTION vs R 0MHz c) I S + I S - FULL BIAS MEDIUM BIAS LOW BIAS DIFFERENTIAL VOLTAGE OUTPUT P-P FIGURE 5. HARMONIC 7MHz ±V S (V) FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE R L = 00Ω C L = 22pF C L = 2pF R L = 00Ω C L = 22pF C L = 2pF C L = 0pF C L = 0pF FIGURE 7. FREQUEY RESPONSE WITH VARIOUS C L (FULL BIAS MODE) FIGURE 8. FREQUEY RESPONSE vs VARIOUS C L (MEDIUM BIAS MODE) 6 FN6387.

7 Typical Performance Curves (Continued) R L = 00Ω C L = 22pF C L = 2pF PSRR+ C L = 0pF PSRR- FIGURE 9. FREQUEY RESPONSE WITH VARIOUS C L (LOW BIAS MODE) FIGURE 20. PSRR vs FREQUEY OUTPUT IMPEDAE (Ω) A V = POWER DISSIPATION (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - EXPOSED DIEPAD SOLDERED TO PCB PER JESD W 2.02W HMSOP0 θ JA = +62 C/W QFN6 θ JA = +52 C/W 0.0 0k 00k M 0M 00M FREQUEY (Hz) AMBIENT TEMPERATURE ( C) FIGURE 2. OUTPUT IMPEDAE vs FREQUEY FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Product Description The ISL57 is a dual operational amplifier designed for line driving in OFDM and PLC solutions. It is a dual current mode feedback amplifier with low distortion while drawing moderately low supply current. It is built using Intersil s proprietary complimentary bipolar process and is offered in industry standard pinouts. Due to the current feedback architecture, the ISL57 closed-loop 3dB bandwidth is dependent on the value of the feedback resistor. First the desired bandwidth is selected by choosing the feedback resistor, R F, and then the gain is set by picking the gain resistor, R G. The curves at the beginning of the Typical Performance Curves on page 4, show the effect of varying both R F and R G. The 3dB bandwidth is somewhat dependent on the power supply voltage. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended. Lead lengths should be as short as possible, below The power supply pins must be well bypassed to reduce the risk of oscillation. A 4.7µF tantalum capacitor in parallel with a 0.µF ceramic capacitor is adequate for each supply pin. During power-up, it is necessary to limit the slew rate of the rising power supply to within V/µs. If the power supply rising time is undetermined, a series 0Ω resistor on the power supply line can be used to ensure the proper power supply rise time. For good AC performance, parasitic capacitances should be kept to a minimum, especially at the inverting input. This implies keeping the ground plane away from this pin. Carbon resistors are acceptable, while use of wire-wound resistors 7 FN6387.

8 should be avoided because of their parasitic inductance. Similarly, capacitors should be low inductance for best performance. Capacitance at the Inverting Input Due to the topology of the current feedback amplifier, stray capacitance at the inverting input will affect the AC and transient performance of the ISL57 when operating in the non-inverting configuration. In the inverting gain mode, added capacitance at the inverting input has little effect since this point is at a virtual ground and stray capacitance is therefore not seen by the amplifier. Feedback Resistor Values The ISL57 has been designed and specified with for A V = +5. This value of feedback resistor yields extremely flat frequency response with db peaking out to 250MHz. As is the case with all current feedback amplifiers, wider bandwidth, at the expense of slight peaking, can be obtained by reducing the value of the feedback resistor. Inversely, larger values of feedback resistor will cause rolloff to occur at a lower frequency. See the curves in the Typical Performance Curves section, beginning on page 4, which show 3dB bandwidth and peaking vs frequency for various feedback resistors and various supply voltages. Bandwidth vs Temperature Whereas many amplifier's supply current and consequently 3dB bandwidth drop off at high temperature, the ISL57 was designed to have little supply current variations with temperature. An immediate benefit is the 3dB bandwidth does not drop off drastically with temperature. Supply Voltage Range The ISL57IRZ has been designed to operate with supply voltages from ±2.25V to ±6V nominal. Optimum bandwidth, slew rate, and video characteristics are obtained at higher supply voltages. Single Supply Operation If a single supply is desired, values from +4.5V to +2V nominal can be used as long as the input common mode range is not exceeded. When using a single supply, be sure to either:. DC bias the inputs at an appropriate common mode voltage and AC couple the signal, or: 2. Ensure the driving signal is within the common mode range of the ISL57. ISL57IUEZ must be used in single supply applications. PLC Modem Applications The ISL57 is designed as a line driver for PLC modems. It is capable of outputting 450mA of output current with a typical supply voltage headroom of.3v. It can achieve -85dBc of distortion at low 7.mA of supply current per amplifier. The average line power requirement for the PLC application is 3dBm (20mW) into a 00Ω line. The average line voltage is.4v RMS. Using a differential drive configuration and transformer coupling with standard back termination, a transformer ratio of :2 is selected. The circuit configuration is shown in Figure 23. AFE Ω TX : FIGURE 23. CIRCUIT CONFIGURATION 8 FN6387.

9 QFN (Quad Flat No-Lead) Package Family A 2X C (E2) C 2 3 SEATING PLANE N LEADS L N (N-) (N-2) b (N/2) e PIN # I.D. MARK TOP VIEW (N/2) 0.0 M C A B (N-2) (N-) N BOTTOM VIEW A DETAIL X C 0.08 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW C A (c) D (D2) 2 7 (L) NE N LEADS E B 2X C PIN # I.D. 5 3 MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL QFN44 QFN38 QFN32 TOLERAE NOTES A ±0.0 - A / b ± c Reference - D Basic - D /2.48 Reference 8 E Basic - E /3.40 Reference 8 e Basic - L ± N Reference 4 ND Reference 6 NE Reference 5 MILLIMETERS TOLER- SYMBOL QFN28 QFN24 QFN20 QFN6 AE NOTES A ±0.0 - A / b ± c Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ± N Reference 4 ND Reference 6 NE Reference 5 Rev 2/07 NOTES:. Dimensioning and tolerancing per ASME Y4.5M Tiebar view shown is a non-functional feature. 3. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 9 FN6387.

10 HMSOP (Heat-Sink MSOP) Package Family E 0.25 M C A B B E N MDP0050 HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY SYMBOL MILLIMETERS HMSOP8 HMSOP0 TOLERAE NOTES D (N/2)+ A Max. - A / A ± (N/2) PIN # I.D. TOP VIEW A b / c ± D ±0.0, 3 EXPOSED THERMAL PAD E2 D Reference - E ±0.5 - E ±0.0 2, 3 D E Reference - e Basic - L ±0.5 - L Basic - BOTTOM VIEW N 8 0 Reference - C SEATING PLANE 0.0 C N LEADS e b SIDE VIEW H 0.08 M C A B Rev. 2/07 NOTES:. Plastic or metal protrusions of 0.5mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.5M-994. L A c END VIEW SEE DETAIL "X" 0.25 GAUGE PLANE A2 3 Ð L DETAIL X A All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 0 FN6387.