Comlinear. CLC1003 Low Distortion, Low Offset, RRIO Amplifier. Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier Rev 1B.

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1 Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier F E A T U R E S n mv max input offset voltage n.5% THD at khz n 5.nV/ Hz input voltage noise >khz n -9dB/-85dB HD/HD at khz, R L =Ω n <-db HD and HD at khz, R L =kω n Rail-to-Rail input and output n 55MHz unity gain bandwidth n V/μs slew rate n +8mA, -55mA output current n -4 C to +5 C operating temperature range n Fully specified at V and ±5V supplies n CLC: Pb-free SOT-5, SOIC-8 n Future option CLC: Dual n Future option CLC4: Quad A P P L I C A T I O N S n Active filters n Sensor interface n High-speed transducer amp n Medical instrumentation n Probe equipment n Test equipment n Smoke detecters n Hand-held analytic instruments General Description The COMLINEAR CLC is a single channel, high-performance, voltage feedback amplifier with near precision performance, low input voltage noise, and ultra low distortion. The CLC family of amplifiers offers mv maximum input offset voltage,.5nv/ Hz broadband input voltage noise, and.5% THD at khz. These amplifiers also provide 55MHz gain bandwidth product and V/μs slew rate making them well suited for applications requiring precision DC performance and high AC performance. These COMLINEAR high-performance amplifiers also offer a rail-to-rail input and output, simplifying single supply designs and offering larger dynamic range possibilities. The inputs extend beyond the rails by 5mV. The COMLINEAR CLC family of amplifiers are designed to operate from.5v to V supplies and operate over the extended temperature range of -4 C to +5. Typical Application - Current Sensing in -Phase Motor SPM (Smart Power Module) M V CC + CLC lph_ lph_ Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B lph_ Ordering Information Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CLCIST5X SOT-5 Yes Yes -4 C to +85 C Reel CLCISO8X SOIC-8 Yes Yes -4 C to +85 C Reel CLCISO8 SOIC-8 Yes Yes -4 C to +85 C Rail CLCAST5X SOT-5 Yes Yes -4 C to +5 C Reel CLCASO8X SOIC-8 Yes Yes -4 C to +5 C Reel CLCASO8 SOIC-8 Yes Yes -4 C to +5 C Rail Moisture sensitivity level for all parts is MSL-. 7- CADEKA Microcircuits LLC

2 CLC SOT Pin Configuration CLC SOT-5 Pin Assignments OUT -V S +IN CLC Pin Configuration OUT -IN +IN -V S CLC4 Pin Configuration OUT -IN +IN +VS +IN -IN OUT V S -IN CLC SOIC Pin Configuration NC -IN +IN -V S NC +V S OUT NC +V S OUT -IN +IN OUT4 -IN4 +IN4 -VS +IN -IN OUT Pin No. Pin Name Description OUT Output -V S Negative supply +IN Positive input 4 -IN Negative input 5 +V S Positive supply CLC SOIC Pin Assignments Pin No. Pin Name Description NC No connect -IN Negative input +IN Positive input 4 -V S Negative supply 5 NC No connect 6 OUT Output 7 +V S Positive supply 8 NC No connect CLC (Future Option) Pin Configuration Pin No. Pin Name Description OUT Output, channel -IN Negative input, channel +IN Positive input, channel 4 -V S Negative supply 5 +IN Positive input, channel 6 -IN Negative input, channel 7 OUT Output, channel 8 +V S Positive supply CLC4 (Future Option) Pin Configuration Pin No. Pin Name Description OUT Output, channel -IN Negative input, channel +IN Positive input, channel 4 +VS Positive supply 5 +IN Positive input, channel 6 -IN Negative input, channel 7 OUT Output, channel 8 OUT Output, channel 9 -IN Negative input, channel +IN Positive input, channel -V S Negative supply +IN4 Positive input, channel 4 -IN4 Negative input, channel 4 4 OUT4 Output, channel 4 Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B 7- CADEKA Microcircuits LLC

3 Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the Absolute Maximum Ratings. The device should not be operated at these absolute limits. Adhere to the Recommended Operating Conditions for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Parameter Min Max Unit Supply Voltage 4 V Input Voltage Range -V s -.5V +V s +.5V V Reliability Information Parameter Min Typ Max Unit Junction Temperature 5 C Storage Temperature Range 5 5 C Lead Temperature (Soldering, s) 6 C Package Thermal Resistance 5-Lead SOT C/W 8-Lead SOIC C/W 4-Lead SOIC 88 C/W Notes: Package thermal resistance (q JA ), JDEC standard, multi-layer test boards, still air. Recommended Operating Conditions Parameter Min Typ Max Unit Operating Temperature Range (CLCI) C Operating Temperature Range (CLCA) C Supply Voltage Range.5 V Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B 7- CADEKA Microcircuits LLC

4 Electrical Characteristics at +V T A = 5 C, V s = +V, R f = kω, R L = kω to V S /, G = ; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response GBWP -db Gain Bandwidth Product G =, V OUT =.5V pp MHz UGBW Unity Gain Bandwidth V OUT =.5V pp, R f = 5 MHz BW SS -db Bandwidth V OUT =.5V pp 4 MHz BW LS Large Signal Bandwidth V OUT = V pp. MHz Time Domain Response t R, t F Rise and Fall Time V OUT = V step; (% to 9%) 5 ns t S Settling Time to.% V OUT = V step 78 ns OS Overshoot V OUT = V step. % SR Slew Rate V step V/µs Distortion/Noise Response HD HD nd Harmonic Distortion rd Harmonic Distortion V pp, khz, R L = kω -98 dbc V pp, khz, R L = Ω -85 dbc V pp, khz, R L = kω -95 dbc V pp, khz, R L = Ω -8 dbc THD Total Harmonic Distortion V pp, khz, G=, R L = kω.5 % e n DC Performance Input Voltage Noise > khz 5.5 nv/ Hz > khz.9 nv/ Hz V IO Input Offset Voltage.88 mv dv IO Average Drift. µv/ C I b Input Bias Current -.4 μa di b Average Drift.8 na/ C I os Input Offset Current. na PSRR Power Supply Rejection Ratio DC db A OL Open-Loop Gain V OUT = V S / 4 db I S Supply Current per channel.85 ma Input Characteristics R IN Input Resistance Non-inverting, G = MΩ C IN Input Capacitance. pf CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio DC, V cm =.5V to.5v 94 db Output Characteristics V OUT Output Voltage Swing R L = 5Ω R L = kω -.5 to.5.85 to.8 I OUT Output Current +75, -4 ma I SC Short-Circuit Output Current V OUT = V S / +95, -5 ma.4 to.9 V V V Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B Notes:. % tested at 5 C 7- CADEKA Microcircuits LLC 4

5 Electrical Characteristics at ±5V T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response GBWP -db Gain Bandwidth Product G =, V OUT =.5V pp 5 MHz UGBW Unity Gain Bandwidth V OUT =.5V pp, R f = 55 MHz BW SS -db Bandwidth V OUT =.5V pp 5 MHz BW LS Large Signal Bandwidth V OUT = V pp.6 MHz Time Domain Response t R, t F Rise and Fall Time V OUT = V step; (% to 9%) 5 ns t S Settling Time to.% V OUT = V step 8 ns OS Overshoot V OUT = V step. % SR Slew Rate 4V step V/µs Distortion/Noise Response HD HD nd Harmonic Distortion rd Harmonic Distortion V pp, khz, R L = kω -5 dbc V pp, khz, R L = Ω -9 dbc V pp, khz, R L = kω -7 dbc V pp, khz, R L = Ω -85 dbc THD Total Harmonic Distortion V pp, khz, G=, R L = kω.5 % e n DC Performance Input Voltage Noise > khz 5. nv/ Hz > khz.5 nv/ Hz V IO Input Offset Voltage () -.5 mv dv IO Average Drift. µv/ C I b Input Bias Current () μa di b Average Drift.85 na/ C I os Input Offset Current ()..7 μa PSRR Power Supply Rejection Ratio () DC 8 db A OL Open-Loop Gain () V OUT = V S / 95 5 db I S Supply Current () per channel..75 ma Input Characteristics R IN Input Resistance Non-inverting, G = MΩ C IN Input Capacitance pf CMIR Common Mode Input Range ±5.5 V CMRR Common Mode Rejection Ratio () DC, V cm = -V to V 7 95 db Output Characteristics V OUT Output Voltage Swing R L = 5Ω to 4.54 R L = kω () to 4.85 V 4.7 V I OUT Output Current +8, -55 ma I SC Short-Circuit Output Current V OUT = V S / +5, -9 ma Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B Notes:. % tested at 5 C 7- CADEKA Microcircuits LLC 5

6 Typical Performance Characteristics T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. Non-Inverting Frequency Response Inverting Frequency Response Frequency Response vs. C L Frequency Response vs. V OUT V OUT =.5V pp G = G = 5 G = G = R f =. C L = 5pF R s = Ω C L = pf R s = 7.5Ω C L = pf R s = 4Ω V OUT =.5V pp -8. V OUT = V pp V OUT = V pp V OUT = 4V pp V OUT =.5V pp G = - G = - G = -5 G = -. Frequency Response vs. C L without R S Frequency Response vs. R L V OUT =.5V pp Rs = Ω C L = 5pF C L = pf C L = pf C L = 5pF C L = pf. R L =.5KΩ R L = KΩ R L = 5Ω R L = 5Ω Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B -5 V OUT =.5V pp CADEKA Microcircuits LLC 6

7 Typical Performance Characteristics T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. Non-Inverting Frequency Response at V S = V Inverting Frequency Response at V S = V - -9 V OUT =.5V pp G = G = 5 G = G = R f =. Frequency Response vs. V OUT at V S = V - -9 V OUT = V pp V OUT = V pp V OUT =.5V pp. -db Bandwidth vs. Output Voltage at V S = V -db Bandwidth (MHz) G = - - G = - - G = -5 G = V OUT =.5V pp -7. Frequency Response vs. R L at V S = V V OUT =.5V pp. -db Bandwidth vs. Output Voltage -db Bandwidth (MHz) R L = 5Ω R L = 5Ω R L =.5KΩ R L = KΩ Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B V OUT (V PP ) V OUT (V PP ) 7- CADEKA Microcircuits LLC 7

8 Typical Performance Characteristics - Continued T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. Open Loop Gain and Phase vs. Frequency CMIR GAIN (db) GAIN Input Voltage Noise Input Voltage Noise (nv/ Hz) CMRR vs. Frequency -75 PHASE ,,,,, FREQ (KHz) PHASE ( ) Vout (V) Vni(V) CMIR at V S = V Vout (V) Vni(V) PSRR vs. Frequency Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B 9 9 CMRR (db) 8 7 CMRR (db) CADEKA Microcircuits LLC 8

9 Typical Performance Characteristics - Continued T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. nd Harmonic Distortion vs. R L rd Harmonic Distortion vs. R L Distortion (dbc) -5 R L = Ω R L = KΩ R L = KΩ R L = 5Ω - V OUT = V pp Frequency (KHz) nd Harmonic Distortion vs. V OUT Distortion (dbc) -4-5 RF=RL=K -7-8 RF=RL=K -9 FREQ = 5KHz Output Amplitude (V pp ) THD vs. Frequency 5-7 Distortion (dbc) -5 R L = KΩ -7 R L = Ω -8-9 R L = 5Ω R L = KΩ - V OUT = V pp Frequency (KHz) rd Harmonic Distortion vs. V OUT Distortion (dbc) RF=RL=K -7-8 RF=RL=K -9 FREQ = 5KHz Output Amplitude (V pp ) Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B -75 THD (db) Frequency (khz) V OUT = V pp RL = K AV+ 7- CADEKA Microcircuits LLC 9

10 Typical Performance Characteristics - Continued T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. nd Harmonic Distortion vs. R L at V S = V rd Harmonic Distortion vs. R L at V S = V Distortion (dbc) -4-5 R L = Ω -7 R L = KΩ R L = KΩ R -8 L = 5Ω -9 V OUT = V pp Frequency (KHz) nd Harmonic Distortion vs. V OUT at V S = V Distortion (dbc) -4-5 RF=RL=K -7-8 RF=RL=K -9 FREQ = 5KHz Output Amplitude (V pp ) THD vs. Frequency at V S = V 5-7 Distortion (dbc) -4-5 R L = Ω -7-8 R L = KΩ R L = KΩ R L = 5Ω -9 V OUT = V pp Frequency (KHz) rd Harmonic Distortion vs. V OUT at V S = V Distortion (dbc) -4-5 RF=RL=K -7-8 RF=RL=K -9 FREQ = 5KHz Output Amplitude (V pp ) Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B -75 THD (db) Frequency (khz) V OUT = V pp RL = K AV+ 7- CADEKA Microcircuits LLC

11 Typical Performance Characteristics - Continued T A = 5 C, V s = ±5V, R f = kω, R L = kω to GND, G = ; unless otherwise noted. Small Signal Pulse Response Small Signal Pulse Response at V S = V Voltage (V) Time (ns) Large Signal Pulse Response Voltage (V) Time (ns) Input Offset Voltage vs. Temperature..5 Voltage (V) Time (ns) Large Signal Pulse Response at V S = V Voltage (V) Time (ns) Input Offset Voltage Distribution 5 4 Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B Vio (V) -.5 Units Temperature ( C) Input Offset Voltage (mv) CADEKA Microcircuits LLC

12 Application Information Basic Operation Figures and illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. Input Input R g + - +V s -V s 6.8μF.μF.μF 6.8μF R f Output G = + (R f/r g) Figure. Typical Non-Inverting Gain Circuit R R g + Power Dissipation - +V s -V s 6.8μF.μF.μF 6.8μF R L Figure. Typical Inverting Gain Circuit Power dissipation should not be a factor when operating under the stated ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it s intended operating range. R f R L G = - (R f/r g) Output For optimum input offset voltage set R = R f R g Maximum power levels are set by the absolute maximum junction rating of 5 C. To calculate the junction temperature, the package thermal resistance value Theta JA (Ө JA ) is used along with the total die power dissipation. T Junction = T Ambient + (Ө JA P D ) Where T Ambient is the temperature of the working environment. In order to determine P D, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. P D = P supply - P load Supply power is calculated by the standard power equation. P supply = V supply I RMS supply V supply = V S+ - V S- Power delivered to a purely resistive load is: P load = ((V LOAD ) RMS )/Rloadeff The effective load resistor (Rload eff ) will need to include the effect of the feedback network. For instance, Rload eff in figure would be calculated as: R L (R f + R g ) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, P D can be found from P D = P Quiescent + P Dynamic - P Load Quiescent power can be derived from the specified I S values along with known supply voltage, V Supply. Load power can be calculated as above with the desired signal amplitudes using: (V LOAD ) RMS = V PEAK / ( I LOAD ) RMS = ( V LOAD ) RMS / Rload eff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: P DYNAMIC = (V S+ - V LOAD ) RMS ( I LOAD ) RMS Assuming the load is referenced in the middle of the power rails or V supply /. Figure shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B 7- CADEKA Microcircuits LLC

13 Maximum Power Dissipation (W) SOT SOIC Ambient Temperature ( C) Figure. Maximum Power Derating Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, R S, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 4. Input R g + - R f R s C L R L Output Figure 4. Addition of R S for Driving Capacitive Loads The CLC family of amplifiers is capable of driving up to pf directly, with no series resistance. Directly driving 5pF causes over 4dB of frequency peaking, as shown in the plot on page 6. Table provides the recommended R S for various capacitive loads. The recommended R S values result in <=db peaking in the frequency response. The Frequency Response vs. C L plots, on page 6, illustrates the response of the CLCx. For a given load capacitance, adjust R S to optimize the tradeoff between settling time and bandwidth. In general, reducing R S will increase bandwidth at the expense of additional overshoot and ringing. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx will typically recover in less than ns from an overdrive condition. Figure 5 shows the CLC in an overdriven condition. Input Voltage (V) Input Figure 5. Overdrive Recovery Considerations for Offset and Noise Performance Offset Analysis Output Time (us) V IN =.8V pp G = 5 There are three sources of offset contribution to consider; input bias current, input bias current mismatch, and input offset voltage. The input bias currents are assumed to be equal with and additional offset current in one of the inputs to account for mismatch. The bias currents will not affect the offset as long as the parallel combination of R f and R g matches R t. Refer to Figure Output Voltage (V) Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B C L (pf) R S (Ω) -db BW (MHz) R g R f +V s IN R t CLC + R L Table : Recommended R S vs. C L -V s Figure 6: Circuit for Evaluating Offset 7- CADEKA Microcircuits LLC

14 The first place to start is to determine the source resistance. If it is very small an additional resistance may need to be added to keep the values of R f and R g to practical levels. For this analysis we assume that R t is the total resistance present on the non-inverting input. This gives us one equation that we must solve: R t = Rg Rf This equation can be rearranged to solve for R g : R g = (R t * R f ) / (R f - R t ) The other consideration is desired gain (G) which is: G = ( + R f /R g ) By plugging in the value for R g we get R f = G * R t And R g can be written in terms of R t and G as follows: R g = (G * R t ) / (G - ) The complete input offset equation is now only dependent on the voltage offset and input offset terms given by: VI OS = And the output offset is: Noise analysis VO OS = G ( V IO ) + ( I OS RT) ( V IO ) + ( I OS RT) The complete equivalent noise circuit is shown in Figure R g R f + + R g + w CLC + R L Where V orext is the noise due to the external resistors and is given by: v o = e n + RF RG + eg RF RG The complete equation can be simplified to: v o + e F = ( 4kT G RT) + ( e n G) + ( i n RT) It s easy to see that the effect of amplifier voltage noise is proportionate to gain and will tend to dominate at large gains. The other terms will have their greatest impact at large R t values at lower gains. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: Include 6.8µF and.µf ceramic capacitors for power supply decoupling Place the 6.8µF capacitor within.75 inches of the power pin Place the.µf capacitor within. inches of the power pin Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B Figure 7: Complete Equivalent Noise Circuit Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: The complete noise equation is given by: v o = v orext + e n + RF RG + ibp RT + RF RG + ( ibn RF) Evaluation Board # CEB CEB Products CLC in SOT-5 CLC in SOIC-8 7- CADEKA Microcircuits LLC 4

15 Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 8-. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application:. Short -Vs to ground.. Use C and C4, if the -V S pin of the amplifier is not directly connected to the ground plane. Figure 8. CEB Schematic Figure. CEB Bottom View Figure. CEB Top View Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B Figure 9. CEB Top View Figure. CEB Bottom View 7- CADEKA Microcircuits LLC 5

16 Mechanical Dimensions SOT-5 Package SOIC-8 Comlinear CLC Low Distortion, Low Offset, RRIO Amplifier Rev B For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: T: (toll free) CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright 7- by CADEKA Microcircuits LLC. All rights reserved.