Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps AD8597/AD8599 PIN CONFIGURATIONS FEATURES APPLICATIONS

Transcription

1 Single and Dual, Ultralow Distortion, Ultralow Noise Op Amps FEATURES Low noise:. nv/ Hz at khz Low distortion: db khz Input noise,. Hz to Hz: <76 nv p-p Slew rate: 4 V/μs Wide bandwidth: MHz Supply current: 4.8 ma/amp typical Low offset voltage: μv typical CMRR: db Unity-gain stable ±5 V operation APPLICATIONS Professional audio preamplifiers ATE/precision testers Imaging systems Medical/physiological measurements Precision detectors/instruments Precision data conversion PIN CONFIGURATIONS NC IN 2 +IN 3 V 4 TOP VIEW (Not to Scale) NC = NO CONNECT 8 NC 7 V+ 6 OUT 5 NC Figure. 8-Lead SOIC (R-8) NC IN 2 +IN 3 V 4 PIN INDICATOR TOP VIEW 8 NC 7 V+ 6 OUT 5 NC NOTES. NC = NO CONNECT. 2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE CONNECTED TO V. Figure 2. 8-Lead LFCSP (CP-8-2) OUT A IN A 2 +IN A 3 V 4 TOP VIEW (Not to Scale) 8 +V 7 OUT B 6 IN B 5 +IN B Figure 3. 8-Lead SOIC (R-8) GENERAL DESCRIPTION The are very low noise, low distortion operational amplifiers ideal for use as preamplifiers. The low noise of. nv/ Hz and low harmonic distortion of db (or better) at audio bandwidths give the the wide dynamic range necessary for preamplifiers in audio, medical, and instrumentation applications. The excellent slew rate of 4 V/μs and MHz gain bandwidth make them highly suitable for medical applications. The low distortion and fast settling time make them ideal for buffering of high resolution data converters. The is available in 8-lead SOIC and LFCSP packages, while the is available in an 8-lead SOIC package. They are both specified over a C to +25 C temperature range. The and are members of a growing series of low noise op amps offered by Analog Devices, Inc., (see Table ). Table. Low Noise Op Amps Package.9 nv. nv.8 nv 2.8 nv 3.8 nv Single AD797 ADA4- AD8675 AD867 Dual ADA4-2 AD8676 AD8672 Quad ADA4-4 AD8674 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 96, Norwood, MA 62-96, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: Trademarks and registered trademarks are the property of their respective owners. Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 5 Thermal Resistance... 5 Power Sequencing... 5 ESD Caution...5 Typical Performance Characteristics...6 Functional Operation... 5 Input Voltage Range... 5 Output Phase Reversal... 5 Noise and Source Impedance Considerations... 5 Outline Dimensions... 7 Ordering Guide... 7 REVISION HISTORY 2/9 Rev. B to Rev. C Changes to Table... /8 Rev. A to Rev. B Added... Universal Added LFCSP_VD... Universal Added Table... Changes to Specifications Section... 3 Changes to Absolute Maximum Ratings Section... 5 Changes to Typical Performance Characteristics Section... 6 Added Figure 2 and Figure Added Figure 8 and Figure Added Figure and Figure Added Figure 34 to Figure Added Figure 42 and Figure Added Figure 52, Figure 55, Figure Added Functional Operation Section... 5 Added Figure Updated Outline Dimensions... 7 Changes to Ordering Guide /7 Rev. to Rev. A Updated Layout... 5 Changes to Figure 45 Caption... 2 Added Figure Changes to Figure 5 Caption /7 Revision : Initial Version Rev. C Page 2 of

3 SPECIFICATIONS VSY = ±5 V, VCM = V, VO = V, TA = 25 C, unless otherwise specified. Table 2. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 5 μv C TA +25 C 8 μv Offset Voltage Drift ΔVOS/ΔT C TA +25 C μv/ C Input Bias Current IB na C TA +25 C 3 na Input Offset Current IOS 65 2 na C TA +25 C 3 na Input Voltage Range IVR V Common-Mode Rejection Ratio CMRR 2. V VCM +2. V 35 db C TA +25 C 5 db Large Signal Voltage Gain AVO RL Ω, VO = V to + V 5 db C TA +25 C db Input Capacitance Differential Capacitance CDIFF 5.4 pf Common-Mode Capacitance CCM 5.5 pf OUTPUT CHARACTERISTICS Output Voltage High VOH RL = Ω V C TA +25 C 3.3 V RL = 2 kω V C TA +25 C 3.5 V Output Voltage Low VOL RL = Ω V C TA +25 C 3.3 V RL = 2 kω V C TA +25 C 3.4 V Output Short-Circuit Current ISC ±52 ma Closed-Loop Output Impedance ZOUT At MHz, AV = 5 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = ±8 V to ±4.5 V db C TA +25 C 8 db Supply Current per Amplifier ISY ma C TA +25 C 6.5 ma DYNAMIC PERFORMANCE Slew Rate SR AV =, RL = 2 kω 4 V/μs AV =, RL = 2 kω 4 V/μs Settling Time ts To.%, step = V 2 μs Gain Bandwidth Product GBP MHz Phase Margin ΦM Degrees NOISE PERFORMANCE Peak-to-Peak Noise en p-p. Hz to Hz 76 nv p-p Voltage Noise Density en f = khz.7.5 nv/ Hz f = Hz.5 nv/ Hz Correlated Current Noise f = khz 2. pa/ Hz f = Hz 4.2 pa/ Hz Uncorrelated Current Noise f = khz 2.4 pa/ Hz f = Hz 5.2 pa/ Hz Total Harmonic Distortion + Noise THD + N G =, RL kω, f = khz, VRMS = V db Channel Separation CS f = khz db Rev. C Page 3 of

4 VS = ±5 V, VCM = V, VO = V, TA = +25 C, unless otherwise specified. Table 3. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS μv C TA +25 C 8 μv Offset Voltage Drift ΔVOS/ΔT C TA +25 C μv/ C Input Bias Current IB 25 na C TA +25 C na Input Offset Current IOS na C TA +25 C na Input Voltage Range IVR V Common-Mode Rejection Ratio CMRR 2.5 V VCM +2.5 V 35 db C TA +25 C 5 db Large Signal Voltage Gain AVO RL Ω, VO = V to + V 6 db C TA +25 C 6 db Input Capacitance Differential Capacitance CDIFF 2. pf Common-Mode Capacitance CCM 5. pf OUTPUT CHARACTERISTICS Output Voltage High VOH RL = Ω V C TA +25 C 2.8 V RL = 2 kω V C TA +25 C 3.2 V Output Voltage Low VOL RL = Ω V C TA +25 C 2.8 V RL = 2 kω V C TA +25 C 3.3 V Output Short-Circuit Current ISC ±52 ma Closed-Loop Output Impedance ZOUT At MHz, AV = 5 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = ±8 V to ±4.5 V db C TA +25 C 8 db Supply Current per Amplifier ISY ma C TA +25 C 6.75 ma DYNAMIC PERFORMANCE Slew Rate SR AV =, RL = 2 kω 6 V/μs AV =, RL = 2 kω 5 V/μs Settling Time ts To.%, step = V 2 μs Gain Bandwidth Product GBP MHz Phase Margin ΦM 65 Degrees NOISE PERFORMANCE Peak-to-Peak Noise en p-p. Hz to Hz 76 nv p-p Voltage Noise Density en f = khz.7.5 nv/ Hz f = Hz.5 nv/ Hz Correlated Current Noise f = khz.9 pa/ Hz f = Hz 4.3 pa/ Hz Uncorrelated Current Noise f = khz 2.3 pa/ Hz f = Hz 5.3 pa/ Hz Total Harmonic Distortion + Noise THD + N G =, RL kω, f = khz, VRMS = 3 V db Channel Separation CS f = khz db Rev. C Page 4 of

5 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage ±8 V Input Voltage V VIN +V Differential Input Voltage ± V Output Short-Circuit to GND Indefinite Storage Temperature Range 65 C to + C Operating Temperature Range C to +25 C Lead Temperature Range (Soldering sec) C Junction Temperature C If the differential input voltage exceeds V, the current should be limited to 5 ma. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified with the device soldered on a circuit board with its exposed paddle soldered to a pad (if applicable) on a 4-layer JEDEC standard PCB with zero air flow. Table 5. Package Type θja θjc Unit 8-Lead LFCSP_VD (CP-8-2) 78 C/W 8-Lead SOIC (R-8) () 39 C/W 8-Lead SOIC (R-8) () 36 C/W POWER SEQUENCING The op amp supplies should be applied simultaneously. The op amp supplies should be stable before any input signals are applied. In any case, the input current must be limited to 5 ma. ESD CAUTION Rev. C Page 5 of

6 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25 C, unless otherwise noted. NUMBER OF AMPLIFIERS 7 MEAN = 8.23 STDEV = MIN = MAX = 62.9 NUMBER OF AMPLIFIERS 7 MEAN = 7.9 STDEV = 2.89 MIN = 63.2 MAX = V OS (µv) Figure 4. Input Offset Voltage Distribution V OS (µv) Figure 7. Input Offset Voltage Distribution NUMBER OF AMPLIFIERS MEAN =.346 STDEV =.28 MIN =. MAX =.55 NUMBER OF AMPLIFIERS MEAN =.765 STDEV =.234 MIN =.338 MAX = TCV OS (µv) Figure 5. TCVOS Distribution, C TA +25 C TCV OS (µv) Figure 8. TCVOS Distribution, C TA +25 C NUMBER OF AMPLIFIERS MEAN =.46 STDEV =.245 MIN =.26 MAX =.26 NUMBER OF AMPLIFIERS MEAN =.342 STDEV =.22 MIN =.3 MAX = TCV OS (µv) Figure 6. TCVOS Distribution, C TA +85 C TCV OS (µv) Figure 9. TCVOS Distribution, C TA +85 C Rev. C Page 6 of

7 V OS (µv) 25 V OS (µv) V CM (V) Figure. Offset Voltage vs. VCM V CM (V) Figure 3. Offset Voltage vs. VCM V CM = V 3 2 V CM = V I B (na) I B (na) Figure. Input Bias Current vs. Temperature Figure 4. Input Bias Current vs. Temperature V OS (µv) ±5V ±5V Figure 2. Input Offset Voltage vs. Temperature I B (na) T A = +25 C V CM (V) T A = C T A = +85 C T A = +25 C Figure 5. Input Bias Current vs. Temperature Rev. C Page 7 of

8 8 7 I OS (na) I I B (na) ±5V ±5V I Figure 6. Input Offset Current vs. Temperature Figure 9. Input Offset Current vs. Temperature R L = 2kΩ, V O = ±2V 8 R L = 2kΩ, V O = ±V A VO (db) 8 6 R L = Ω, V O = ±2V A VO (db) 6 4 R L = Ω, V O = ±V Figure 7. Large Signal Voltage Gain vs. Temperature Figure. Large Signal Voltage Gain vs. Temperature I SY (ma) T A = +25 C T A = +85 C T A = +25 C T A = C V SY (V) I B (na) T A = C T A = +25 C T A = +85 C T A = +25 C 2 2 V CM (V) Figure 8. Supply Current vs. Supply Voltage Figure 2. Input Bias Current vs. VCM Rev. C Page 8 of

9 8 8 OUTPUT CURRENT (ma) I SINK I SOURCE OUTPUT CURRENT (ma) I SINK I SOURCE Figure 22. ISC vs. Temperature Figure 25. ISC vs. Temperature OUTPUT SATURATION VOLTAGE (mv) k k I SINK I SOURCE OUTPUT SATURATION VOLTAGE (mv) k k I SINK I SOURCE... I L (ma) I L (ma) Figure 23. Output Saturation Voltage vs. Current Load Figure 26. Output Saturation Voltage vs. Current Load V CC V R L = Ω V CC V OH (V).5. V CC V R L = Ω V CC V R L = 2kΩ V CC V OH (V).5. V CC V R L = 2kΩ Figure 24. Output Saturation Voltage vs. Temperature Figure 27. Output Saturation Voltage vs. Temperature Rev. C Page 9 of

10 .5.5 V EE V OL (V)..5 V EE V R L = 2kΩ V EE V R L = Ω V EE V OL (V)..5 V EE V R L = 2kΩ V EE V R L = Ω Figure 28. Output Saturation Voltage vs. Temperature Figure 3. Output Saturation Voltage vs. Temperature V R L = Ω V R L = 2kΩ V OL (V) 4. V OH (V) V R L = 2kΩ Figure 29. Output Voltage Low vs. Temperature V R L = Ω Figure 32. Output Voltage High vs. Temperature GAIN (db) AND PHASE (Degrees) C L = pf 8 R L = 2kΩ k k k FREQUENCY (khz) Figure. Gain and Phase vs. Frequency C L = pf GAIN (db) AND PHASE (Degrees) 8 8 R L = 2kΩ C L = pf k k k FREQUENCY (khz) Figure 33. Gain and Phase vs. Frequency C L = pf Rev. C Page of

11 A V = A V = A V = A V = GAIN (db) A V = GAIN (db) A V = R L = 2kΩ k k k FREQUENCY (khz) Figure 34. Closed-Loop Gain vs. Frequency R L = 2kΩ k k k FREQUENCY (khz) Figure 37. Closed-Loop Gain vs. Frequency A V = A V = A V = A V = Z OUT (Ω) A V = + Z OUT (Ω) A V = +... k k k FREQUENCY (khz) Figure 35. Closed-Loop Output Impedance vs. Frequency k k k FREQUENCY (khz) Figure 38. Closed-Loop Output Impedance vs. Frequency ±5V V SY ±5V PSRR+ (db) PSRR (db) CMRR (db) 7, ±5V PSRR (db) k k FREQUENCY (khz) Figure 36. Common-Mode Rejection Ratio vs. Frequency k k k M M FREQUENCY (Hz) Figure 39. Power Supply Rejection Ratio vs. Frequency Rev. C Page of

12 NUMBER OF AMPLIFIERS MEAN =. STDEV =.9 MIN =. MAX =.5 ±5V V SY ±5V NUMBER OF AMPLIFIERS MEAN =.7 STDEV =.2 MIN =.5 MAX =.5 ±5V V SY ±5V VOLTAGE NOISE DENSITY (nv/ Hz) Figure. Voltage Noise Hz VOLTAGE NOISE DENSITY (nv/ Hz) Figure 43. Voltage Noise khz ±5V V SY ±5V ±5V V SY ±5V VOLTAGE NOISE DENSITY (nv/ Hz) CURRTENT NOISE DENSITY (pa/ Hz). k FREQUENCY (Hz) Figure 4. Voltage Noise Density vs. Frequency FREQUENCY (Hz) Figure 44. Current Noise Density vs. Frequency k THD + N (%).. A V = + R L = Ω THD + N (%).. A V = + R L = Ω R L = kω.... V rms (V) Figure 42. THD + N vs. Amplitude R L = kω.... V rms (V) Figure 45. THD + N vs. Amplitude Rev. C Page 2 of

13 . V IN = 3V rms V IN = 5V rms V IN = 7V rms. V IN = 3V rms.. THD + N (%). THD + N (%). R L = Ω R L = 2kΩ. k k k FREQUENCY (Hz) Figure 46. THD + N vs. Frequency k k k FREQUENCY (Hz) Figure 49. THD + N vs. Frequency AMPLITUDE (V) V IN = V p-p A V = R F = kω R L = 2kΩ VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4µs/DIV AMPLITUDE (V) V IN = V p-p A V = R F = 2kΩ R S = 2kΩ C L = pf VERTICAL AXIS = 5V/DIV HORIZONTAL AXIS = 4µs/DIV TIME (µs) Figure 47. Large Signal Response TIME (µs) Figure. Large Signal Response AMPLITUDE (mv) 8, ±5V V IN = mv p-p A V = EXTERNAL C L = pf EXTERNAL R L = kω VERTICAL AXIS = mv/div HORIZONTAL AXIS = ns/div TIME (ns) Figure 48. Small Signal Response OVERSHOOT (%) ±5V V SY ±5V A V = R L = kω k CAPACITANCE (pf) Figure 5. Overshoot vs. Capacitance Rev. C Page 3 of

14 45 45 OVERSHOOT (%) OS OS+ OVERSHOOT (%) OS+ OS 5 k CAPACITANCE (pf) Figure 52. Overshoot vs. Capacitive Load k CAPACITANCE (pf) Figure 55. Overshoot vs. Capacitive Load CHANNEL SEPARATION (db) 8 A V = R L = kω V IN = V p-p V IN = V p-p I SY (ma) k k k M FREQUENCY (Hz) Figure 53. Channel Separation vs. Frequency Figure 56. Supply Current vs. Temperature ±5V V SY ±5V AMPLITUDE (nv) I SY (ma) TIME (Seconds) Figure 54. Peak-to-Peak Noise Figure 57. Supply Current vs. Temperature Rev. C Page 4 of

15 FUNCTIONAL OPERATION INPUT VOLTAGE RANGE The are not rail-to-rail input amplifiers; therefore, care is required to ensure that both inputs do not exceed the input voltage range. Under normal negative feedback operating conditions, the amplifier corrects its output to ensure that the two inputs are at the same voltage. However, if either input exceeds the input voltage range, the loop opens and large currents begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and they are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes can become forward-biased. Without current limiting, excessive amounts of current may flow through these diodes, causing permanent damage to the device. If inputs are subject to overvoltage, insert appropriate series resistors to limit the diode current to less than 5 ma maximum. The input stage has two diodes between the input pins to protect the differential pair. Under high slew rate conditions, when the op amp is connected as a voltage follower, the diodes may become forward-biased and the source may try to drive the output. A small resistor should be placed in the feedback loop and in the noninverting input. The noise of a Ω resistor at room temperature is ~.25 nv/ Hz, which is higher than the. Thus, there is a tradeoff between noise performance and protection. If possible, limiting should be placed earlier in the signal path. For further details, see the Amplifier Input Protection Friend or Foe article at Because of the large transistors used to achieve low noise, the input capacitance may seem rather high. To take advantage of the low noise performance, impedance around the op amp should be low, less than Ω. Under these conditions, the pole from the input capacitance should be greater than MHz, which does not affect the signal bandwidth. OUTPUT PHASE REVERSAL Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As the commonmode voltage is moved outside the input voltage range, the outputs of these amplifiers can suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down that causes a radical shifting of internal voltages that results in the erratic output behavior. The amplifiers have been carefully designed to prevent any output phase reversal if both inputs are maintained within the specified input voltage range. If one or both inputs exceed the input voltage range but remain within the supply rails, the op amp specifications, such as CMRR, are not guaranteed, but the output remains close to the correct value. NOISE AND SOURCE IMPEDANCE CONSIDERATIONS The ultralow voltage noise of. nv/ Hz is achieved with special input transistors running at high collector current. Therefore, it is important to consider the total inputreferred noise (en total), which includes contributions from voltage noise (en), current noise (in), and resistor noise ( 4 ktrs). en total = [en ktrs + (in RS) 2 ] /2 () where RS is the total input source resistance. This equation is plotted for the in Figure 58. Because optimum dc performance is obtained with matched source resistances, this case is considered even though it is clear from Equation that eliminating the balancing source resistance lowers the total noise by reducing the total RS by a factor of 2. At a very low source resistance (RS < Ω), the voltage noise of the amplifier dominates. As source resistance increases, the Johnson noise of RS dominates until a higher resistance of RS > 2 kω is achieved; the current noise component is larger than the resistor noise. TOTAL NOISE (nv/ Hz) TOTAL NOISE RESISTOR NOISE ONLY. k k SOURCE RESISTANCE (Ω) Figure 58. Noise vs. Source Resistance Rev. C Page 5 of

16 The are the optimum choice for low noise performance if the source resistance is kept < kω. At higher values of source resistance, optimum performance with respect to only noise is obtained with other amplifiers from Analog Devices. Both voltage noise and current noise need to be considered. For more information on avoiding noise from grounding problems and inadequate bypassing, see the AN-345 Application Note, Grounding for Low- and High-Frequency Circuits. For general noise theory with extensive calculations, see the AN-358 Application Note, Noise and Operational Amplifier Circuits. A good selection table for low noise op amps can be found in AN-9 Application Note, Low Noise Amplifier Selection Guide for Optimal Noise Performance. An interesting note on using one section of a monolithic dual to phase compensate the other section is in the AN-7 Application Note, Active Feedback Improves Amplifier Phase Accuracy. V+ 7 D R8 R9 Q36 INVERTING INPUT NONINVERTING INPUT D39 D D4 D42 Q8 Q9 V B Q9 Q C D3 D34 R Q32 R3 R32 D2 D3 6 OUTPUT D2 4 V Q27 Q28 Figure 59. Simplified Schematic Rev. C Page 6 of

17 OUTLINE DIMENSIONS 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.244) 5.8 (.2284).25 (.98). (.) COPLANARITY. SEATING PLANE.27 (.) BSC.75 (.688).35 (.532).5 (.).3 (.22) 8.25 (.98).7 (.67). (.96).25 (.99).27 (.). (.57) 45 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 27-A SQ MAX. MAX. BSC PIN INDICATOR TOP VIEW SQ EXPOSED PAD (BOTTOM VIEW) MAX.7 MAX....9 MAX.65 TYP.85 NOM.5 MAX. NOM SEATING PLANE REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATIONS SECTION OF THIS DATA SHEET. Figure 6. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters PIN INDICATOR 78-B ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ACPZ-R2 C to +25 C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22 ACPZ-REEL C to +25 C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22 ACPZ-REEL7 C to +25 C 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] CP-8-2 A22 ARZ C to +25 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ARZ-REEL C to +25 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ARZ-REEL7 C to +25 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ARZ C to +25 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ARZ-REEL C to +25 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 ARZ-REEL7 C to +25 C 8-Lead Standard Small Outline Package [SOIC_N] R-8 Z = RoHS Complaint Part. Rev. C Page 7 of

18 NOTES Rev. C Page 8 of

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20 NOTES 7 9 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /9(C) Rev. C Page of