High Voltage, Precision Operational Amplifier ADA4700-1

Transcription

1 FEATURES Low input offset voltage:.2 mv typical High output current drive: 3 ma Wide range of operating voltage: ±5 V to ±5 V High slew rate: 2 V/µs typical High gain bandwidth product: 3.5 MHz typical Thermal regulation at junction temperature >45 C Ambient temperature range: 4 C to +85 C Low input bias current 5 na typical APPLICATIONS Automated and bench top test equipment High voltage regulators and power amplifiers Data acquisition and signal conditioning Piezo drivers and predrivers General-purpose current sensing GENERAL DESCRIPTION The is a high voltage, precision, single-channel operational amplifier with a wide operating voltage range (±5 V to ±5 V) and relatively high output current drive. Its advanced design combines low power (7 mw for a ±5 V supply), high bandwidth (3.5 MHz), and a high slew rate with unity-gain stability and phase inversion free performance. The ability to swing near rail to rail at the output enables designers to maximize signalto-noise ratios (SNRs). The is designed for applications requiring both ac and dc precision performance, making the useful in a wide variety of applications, including high voltage test equipment and instrumentation, high voltage regulators and power amplifiers, power supply control and protection, and as an amplifier or buffer for transducers with wide output ranges. It is particularly well suited for high intensity LED testing applications where it provides highly accurate voltage and current feedback as well as a predriver to provide accurate voltage and/or current sourcing stimulus to the LED string under test. The is specified over the industrial temperature range of 4 C to +85 C and includes thermal regulation at a junction temperature greater than 45 C and an integrated current limit. The is available in a thermally enhanced, 8-lead SOIC package with an exposed pad. OUTPUT (V) High Voltage, Precision Operational Amplifier NC IN +IN V PIN CONFIGURATION TOP VIEW (Not to Scale) Figure. Figure 2. Slew Rate NC V+ OUT NC NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT EXPOSED PAD TO V OR LEAVE FLOATING. OUTPUT INPUT 3 3 V SY = ±5V 4 A V = 2V/V 4 R L = 2kΩ TIME (µs) INPUT (V) 55-2 Rev. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 * PRODUCT PAGE QUICK LINKS Last Content Update: 2/23/27 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS EVALUATION BOARD DOCUMENTATION : High Voltage, Precision Operational Amplifier User Guides UG-67: Evaluating Universal Precision High-Voltage Op Amps in SOIC Packages TOOLS AND SIMULATIONS Analog Filter Wizard Analog Photodiode Wizard ADA47 SPICE Macro Model DESIGN RESOURCES Material Declaration PCN-PDN Information Quality And Reliability Symbols and Footprints DISCUSSIONS View all EngineerZone Discussions. SAMPLE AND BUY Visit the product page to see pricing options. TECHNICAL SUPPORT Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

3 TABLE OF CONTENTS Features... Applications... Pin Configuration... General Description... Revision History... 2 Specifications... 3 VSY = ±5 V Electrical Characteristics... 3 VSY = ±24 V Electrical Characteristics... 5 VSY = ±5 V Electrical Charateristics... 7 Absolute Maximum Ratings... 8 Thermal Resistance... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Typical Performance Characteristics... Test Circuits... 2 Theory of Operation... 2 Thermal Regulation... 2 Applications Information Thermal Management Safe Operating Area Driving Capacitive Loads Increasing Current Drive Constant Current Applications Outline Dimensions Ordering Guide REVISION HISTORY 8/3 Revision : Initial Version Rev. Page 2 of 28

4 SPECIFICATIONS V SY = ±5 V ELECTRICAL CHARACTERISTICS VSY = ±5 V, VCM = V, TA = 25 C, unless otherwise specified. Table. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.2 2 mv 4 C TA +85 C 2.5 mv Offset Voltage Drift ΔVOS/ΔT 4 C TA +85 C 2 3 µv/ C Input Bias Current IB 5 3 na 4 C TA +85 C 5 na Input Offset Current IOS 2 25 na 4 C TA +85 C 3 na Input Voltage Range IVR 4 C TA +85 C (V ) + 3 (V+) 3 V Common-Mode Rejection Ratio CMRR (V ) + 3 V VCM (V+) 3 V 3 8 db 4 C TA +85 C 3 db Large Signal Voltage Gain AVO 47 V VOUT +47 V, RL = 2 kω 3 6 db 4 C TA +85 C db Input Impedance Common-Mode RIN CINCM MΩ pf Differential RIN CINDM MΩ pf OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω to GND V 4 C TA +85 C 47.8 V RL = 2 kω to GND V 4 C TA +85 C 47.3 V Output Voltage Low VOL RL = kω to GND V 4 C TA +85 C 47.8 V RL = 2 kω to GND V 4 C TA +85 C 47.3 V Capacitive Load Drive 2 CL AV = + nf Output Current Drive 3 IOUT 3 ma Short-Circuit Limit ISC Sourcing/Sinking +72/ 65 ma Closed-Loop Impedance ZOUT f = Hz, AV = +. Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±55 V 3 db 4 C TA +85 C db Supply Current per Amplifier ISY ma 4 C TA +85 C 2.4 ma DYNAMIC PERFORMANCE Slew Rate SR VIN = ±45 V p-p, AV = +, RL = 2 kω, CL = 3 pf 2 V/µs Gain Bandwidth Product GBP VIN = 5 mv p-p, AV = MHz Unity-Gain Crossover UGC VIN = 5 mv p-p, AV = MHz 3 db Bandwidth 3 db VIN = 5 mv p-p, AV = 4.8 MHz Phase Margin ΦM VIN = 5 mv p-p, RL = MΩ, CL = 35 pf, AV = 7 Degrees Settling Time to.% ts VIN = 3 V p-p, RL = kω, CL = 5 pf, AV = 4 µs Settling Time to.% ts VIN = 3 V p-p, RL = kω, CL = 5 pf, AV = 8 µs Rev. Page 3 of 28

5 Parameter Symbol Test Conditions/Comments Min Typ Max Unit NOISE PERFORMANCE Total Harmonic Distortion + Noise THD + N AV = +, VIN = V p-p at khz, RL = kω,.2 % bandwidth = 8 khz Peak-to-Peak Noise en p-p f =. Hz to Hz 8 nv p-p Voltage Noise Density en f = khz 4.7 nv/ Hz f = Hz 27 nv/ Hz Current Noise Density in f = khz 4 fa/ Hz See Figure 7 through Figure 9. 2 Overshoot vs. temperature and capacitive load performance is shown in Figure 27 through Figure 3. Refer to the Driving Capacitive Loads section for recommendations on driving capacitive loads greater than nf. 3 Refer to the Safe Operating Area section. Rev. Page 4 of 28

6 V SY = ±24 V ELECTRICAL CHARACTERISTICS VSY = ±24 V, VCM = V, TA = 25 C, unless otherwise specified. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.2 2 mv 4 C TA +85 C 2.5 mv Offset Voltage Drift ΔVOS/ΔT 4 C TA +85 C µv/ C Input Bias Current IB 5 3 na 4 C TA +85 C 5 na Input Offset Current IOS 2 25 na 4 C TA +85 C 3 na Input Voltage Range IVR 4 C TA +85 C (V ) + 3 (V+) 3 V Common-Mode Rejection Ratio CMRR (V ) + 3 V VCM (V+) 3 V 3 db 4 C TA +85 C db Large Signal Voltage Gain AVO 2 V VOUT +2 V, RL = 2 kω 3 5 db 4 C TA +85 C db Input Impedance Common-Mode RIN CINCM MΩ pf Differential RIN CINDM MΩ pf OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω to GND V 4 C TA +85 C 22. V RL = 2 kω to GND V 4 C TA +85 C 2.8 V Output Voltage Low VOL RL = kω to GND V 4 C TA +85 C 22. V RL = 2 kω to GND V 4 C TA +85 C 2.8 V Capacitive Load Drive 2 CL AV = + nf Output Current Drive IOUT 3 ma Short-Circuit Limit 3 ISC Sourcing/Sinking +72/ 65 ma Closed-Loop Impedance ZOUT f = Hz, AV = +. Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±55 V 3 db 4 C TA +85 C db Supply Current per Amplifier ISY ma 4 C TA +85 C 2.3 ma DYNAMIC PERFORMANCE Slew Rate SR VIN = ±2 V p-p, AV = +, RL = 2 kω, CL = 3 pf 2 V/µs Gain Bandwidth Product GBP VIN = 5 mv p-p, AV = MHz Unity-Gain Crossover UGC VIN = 5 mv p-p, AV = MHz 3 db Bandwidth 3 db VIN = 5 mv p-p, AV = 4.8 MHz Phase Margin ΦM VIN = 5 mv p-p, RL = MΩ, CL = 35 pf, AV = 7 Degrees Settling Time to.% ts VIN = 2 V p-p, RL = kω, CL = 5 pf, AV = 4 µs Settling Time to.% ts VIN = 2 V p-p, RL = kω, CL = 5 pf, AV = 9 µs Rev. Page 5 of 28

7 Parameter Symbol Test Conditions/Comments Min Typ Max Unit NOISE PERFORMANCE Total Harmonic Distortion + Noise THD + N AV = +, VIN = V p-p at khz, RL = kω,.2 % bandwidth = 8 khz Peak-to-Peak Noise en p-p f =. Hz to Hz 8 nv p-p Voltage Noise Density en f = khz 4.7 nv/ Hz f = Hz 27 nv/ Hz Current Noise Density in f = khz 4 fa/ Hz See Figure 7 through Figure 9. 2 Overshoot vs. temperature and capacitive load performance is shown in Figure 27 through Figure 3. Refer to the Driving Capacitive Loads section for recommendations on driving capacitive loads greater than nf. 3 Refer to the Safe Operating Area section. Rev. Page 6 of 28

8 V SY = ±5 V ELECTRICAL CHARATERISTICS VSY = ±5 V, VCM = V, TA = 25 C, unless otherwise specified. Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS.2 2 mv 4 C TA +85 C 2.5 mv Offset Voltage Drift ΔVOS/ΔT 4 C TA +85 C 3 μv/ C Input Bias Current IB 5 3 na 4 C TA +85 C 5 na Input Offset Current IOS 2 25 na 4 C TA +85 C 3 na Input Voltage Range IVR 4 C TA +85 C 2 +2 V Common-Mode Rejection Ratio CMRR 2 V VCM +2 V db 4 C TA +85 C 86 db Large Signal Voltage Gain AVO 2 V VOUT +2 V, RL = 2 kω db 4 C TA +85 C 95 db Input Impedance Common-Mode RIN CINCM MΩ pf Differential RIN CINDM MΩ pf OUTPUT CHARACTERISTICS Output Voltage High VOH RL = 2 kω to GND V 4 C TA +85 C 3.2 V Output Voltage Low VOL RL = 2 kω to GND V 4 C TA +85 C 3.2 V Capacitive Load Drive 2 CL AV = + nf Output Current Drive IOUT 3 ma Short Circuit Limit 3 ISC Sourcing/Sinking +72/ 65 ma Closed-Loop Impedance ZOUT f = Hz, AV = +.3 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±55 V 3 db 4 C TA +85 C db Supply Current per Amplifier ISY.5 2 ma 4 C TA +85 C 2.2 ma DYNAMIC PERFORMANCE Slew Rate SR VIN = ±2 V p-p, AV = +, RL = 2 kω, CL = 3 pf 8 V/μs Gain Bandwidth Product GBP VIN = 5 mv p-p, AV = MHz Unity-Gain Crossover UGC VIN = 5 mv p-p, AV = MHz 3 db Bandwidth 3 db VIN = 5 mv p-p, AV = 4.8 MHz Phase Margin ΦM VIN = 5 mv p-p, RL = MΩ, CL = 35 pf, AV = 7 Degrees Settling Time to.% ts VIN = 6 V p-p, RL = kω, CL = 5 pf, AV =.5 μs NOISE PERFORMANCE Total Harmonic Distortion + Noise THD + N AV = +, VIN = 2 V p-p at khz, RL = kω,.5 % bandwidth = 8 khz Peak-to-Peak Noise en p-p f =. Hz to Hz 8 nv p-p Voltage Noise Density en f = khz 4.7 nv/ Hz Current Noise Density in f = khz 4 fa/ Hz See Figure 7 through Figure 9. 2 Overshoot vs. temperature and capacitive load performance is shown in Figure 27 through Figure 3. Refer to the Driving Capacitive Loads section for recommendations on driving capacitive loads greater than nf. 3 Refer to the Safe Operating Area section. Rev. Page 7 of 28

9 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage V Input Voltage V VIN V+ Input Current ± ma Differential Input Voltage V VIN V+ Storage Temperature Range 65 C to +5 C Operating Temperature Range 4 C to +85 C Junction Temperature Range 65 C to +5 C Lead Temperature (Soldering, 6 sec) 3 C ESD Charged Device Model (CDM) 25 V Human Body Model (HBM) 45 V Machine Model (MM) 2 V Refer to the Thermal Management section. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. The values in Table 5 were obtained per JEDEC standard JESD5. Table 5. Thermal Resistance Package Type θja θjc Unit 8-Lead SOIC_N_EP 45 3 C/W Board layout impacts thermal characteristics such as θja. When proper thermal management techniques are used, a better θja can be achieved. Refer to the Thermal Management section for additional information. Although the exposed pad can be left floating, it must be connected to an external V plane for proper thermal management. ESD CAUTION Rev. Page 8 of 28

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NC 8 NC IN 2 7 V+ +IN 3 6 OUT V 4 TOP VIEW (Not to Scale) 5 NC NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. CONNECT EXPOSED PAD TO V OR LEAVE FLOATING. Figure 3. Pin Configuration 55-3 Table 6. Pin Function Descriptions Pin No. Mnemonic Description, 5, 8 NC No Connect. Do not connect to these pins. 2 IN Inverting Input. 3 +IN Noninverting Input. 4 V Negative Supply Voltage. 6 OUT Output. 7 V+ Positive Supply Voltage. 9 EPAD Exposed Pad. Connect the exposed pad to V or leave floating. The exposed pad is electrically connected to the device. Rev. Page 9 of 28

11 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25 C, unless otherwise noted. NUMBER OF AMPLIFIERS V SY = ±5V V CM = V MEAN = 5µV NUMBER OF AMPLIFIERS V SY = ±5V V CM = V MEAN: 2.7µV/ C V OS (µv) Figure 4. Input Offset Voltage Distribution, VSY = ±5 V TCV OS (μv/ C) Figure 7. Input Offset Voltage Drift Distribution, VSY = ±5 V V SY = ±24V V CM = V MEAN = 5µV 35 3 V SY = ±24V V CM = V MEAN: 2.4µV/ C NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS V OS (µv) TCV OS (μv/ C) 55-6 Figure 5. Input Offset Voltage Distribution, VSY = ±24 V Figure 8. Input Offset Voltage Drift Distribution, VSY = ±24 V NUMBER OF AMPLIFIERS V SY = ±5V V CM = V MEAN = 8µV NUMBER OF AMPLIFIERS V SY = ±5V V CM = V MEAN: 2.µV/ C V OS (µv) TCV OS (μv/ C) 55-9 Figure 6. Input Offset Voltage Distribution, VSY = ±5 V Figure 9. Input Offset Voltage Drift Distribution, VSY = ±5 V Rev. Page of 28

12 TA = 25 C, unless otherwise noted. 5 V SY = ±5V 3 V SY = ±5V V OS (µv) C +25 C +25 C I B (na) C +85 C 4 C +25 C 4 C V CM (V) Figure. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±5 V V CM (V) Figure 3. Input Bias Current (IB) vs. Common-Mode Voltage (VCM) and Temperature, VSY = ±5 V V SY = ±5V 3 V SY = ±5V V OS (µv) C +85 C +25 C 4 C I B (na) C +25 C 4 C +85 C V CM (V) Figure. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±5 V V CM (V) Figure 4. Input Bias Current (IB) vs. Common-Mode Voltage (VCM) and Temperature, VSY = ±5 V 55-2 V OS (µv) V SY = ±5V 4 C +25 C +85 C +25 C I B (na) V SY = ±5V +25 C +85 C 4 C +25 C V CM (V) Figure 2. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±5 V V CM (V) Figure 5. Input Bias Current (IB) vs. Common-Mode Voltage (VCM) and Temperature, VSY = ±5 V 55-5 Rev. Page of 28

13 TA = 25 C, unless otherwise noted. OUTPUT (V OH ) TO SUPPLY RAIL (V) V SY = ±5V TO ±5V SOURCING CURRENT 4 C +25 C +25 C +85 C OUTPUT (V OL ) TO SUPPLY RAIL (V) V SY = ±5V TO ±5V SINKING CURRENT 4 C +25 C +25 C +85 C V CONTROL.... LOAD CURRENT (ma) Figure 6. Output Voltage (VOH) to Supply Rail vs. Load Current, VSY = ±5 V to ±5 V OFF ON TIME (µs/div) OUTPUT V SY = ±5V A V = + LOAD = 2mA SOURCING Figure 7. Output Current Transient Settling Time (Sourcing), VSY = ±5 V, Refer to Figure 56 for the Test Circuit OUTPUT AMPLITUDE (mv) V CONTROL.... LOAD CURRENT (ma) Figure 9. Output Voltage (VOL) to Supply Rail vs. Load Current, VSY = ±5 V to ±5 V OFF TIME (µs/div) OUTPUT Figure 2. Output Current Transient Settling Time (Sinking), VSY = ±5 V, Refer to Figure 57 for the Test Circuit ON V SY = ±5V A V = + LOAD = 2mA SINKING OUTPUT AMPLITUDE (mv) C +25 C SUPPLY CURRENT (ma) C 4 C SUPPLY VOLTAGE (±V) Figure 8. Supply Current vs. Supply Voltage Rev. Page 2 of 28

14 TA = 25 C, unless otherwise noted. UNITY-GAIN BANDWIDTH (MHz) V CM = +47V V CM = V V CM = 47V V SY = ±5V R L = MΩ C L = 2pF UNITY-GAIN BANDWIDTH (MHz) C +25 C +85 C +25 C V SY = ±5V R L = 2kΩ TEMPERATURE ( C) Figure 2. Unity-Gain Bandwidth vs. Temperature, VSY = ±5 V LOAD CAPACITIVE (pf) Figure 24. Unity-Gain Bandwidth vs. Load Capacitance and Temperature, VSY = ±5 V GAIN (db) V SY = ±5V TO ±5V V CM = V R L = MΩ C L = 35pF 5 k k k M M FREQUENCY (Hz) PHASE GAIN Figure 22. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V to ±5 V PHASE (Degrees) 55-3 GAIN (db) V SY = ±5V 5 V SY = ±5V V SY = ±5V LOAD CURRENT (ma) Figure 25. Open-Loop Gain vs. Load Current for Various Supply Voltages A V = + V SY = ±5V TO ±5V 5 V SY = ±5V GAIN (db) 3 2 A V = + A V = + GAIN (db) 5 R L = kω R L = 2kΩ 2 3 k k k M M FREQUENCY (Hz) Figure 23. Closed-Loop Gain vs. Frequency, VSY = ±5 V to ±5 V TEMPERATURE ( C) Figure 26. Open-Loop Gain vs. Temperature for Various Load Resistances, VSY = ±5 V 55-3 Rev. Page 3 of 28

15 TA = 25 C, unless otherwise noted. 4 3 V SY = ±5V V IN = ±5mV A V = + R L = kω C L = pf 4 3 V SY = ±5V V IN = ±5mV A V = + R L = kω OVERSHOOT (%) 2 C L = 5pF C L = 3pF OVERSHOOT (%) 2 C L = pf C L = 5pF C L = 3pF C L = pf C L = pf TEMPERATURE ( C) TEMPERATURE ( C) Figure 27. Small Signal Overshoot vs. Temperature for Various Capacitance Loads, VSY = ±5 V Figure 29. Small Signal Overshoot vs. Temperature for Various Capacitance Loads, VSY = ±5 V 4 3 V SY = ±5V V IN = ±5mV A V = + R L = kω C L = pf 6 5 V SY = ±5V TO ±5V V IN = ±5mV A V = + R L = kω OS +OS OVERSHOOT (%) 2 C L = 5pF C L = 3pF OVERSHOOT (%) C L = pf TEMPERATURE ( C) Figure 28. Small Signal Overshoot vs. Temperature for Various Capacitance Loads, VSY = ±5 V LOAD CAPACITANCE (pf) Figure 3. Small Signal Overshoot vs. Load Capacitance, VSY =±5 V to ±5 V Rev. Page 4 of 28

16 TA = 25 C, unless otherwise noted.. V SY = ±5V V CM = V 8kHz LOW-PASS FILTER THD + NOISE (%).. R L = 2kΩ THD + NOISE (%).. V IN = 2V p-p R L = 2kΩ. V SY = ±5V V CM = V f IN = khz R L = kω.... AMPLITUDE (V p-p) Figure 3. Total Harmonic Distortion + Noise (THD + Noise) vs. Amplitude, VSY = ±5 V k k k FREQUENCY (Hz) Figure 34. Total Harmonic Distortion + Noise (THD + Noise) vs. Frequency, VSY = ±5 V. V IN = 3V p-p R L = kω V SY = ±5V V CM = V 8kHz LOW-PASS FILTER THD + NOISE (%).. R L = 2kΩ THD + NOISE (%).. V IN = 2V p-p R L = 2kΩ. V SY = ±5V V CM = V f IN = khz R L = kω.... AMPLITUDE (V p-p) Figure 32. Total Harmonic Distortion + Noise (THD + Noise) vs. Amplitude, VSY = ±5 V V IN = V p-p R L = kω. k k k FREQUENCY (Hz) Figure 35. Total Harmonic Distortion + Noise (THD + Noise) vs. Frequency, VSY = ±5 V V SY = ±5V V CM = V 8kHz LOW-PASS FILTER THD + NOISE (%).. R L = 2kΩ. V SY = ±5V V CM = V f IN = khz R L = kω.... AMPLITUDE (V p-p) Figure 33. Total Harmonic Distortion + Noise (THD + Noise) vs. Amplitude, VSY = ±5 V THD + NOISE (%).. V IN = 2V p-p R L = 2kΩ V IN = V p-p R L = kω. k k k FREQUENCY (Hz) Figure 36. Total Harmonic Distortion + Noise (THD + Noise) vs. Frequency, VSY = ±5 V Rev. Page 5 of 28

17 TA = 25 C, unless otherwise noted. 4 2 V CM = (V+) 3V 2 V CM = V V SY = ±5V CMRR (db) 8 6 V CM = (V ) + 3V CMRR (db) V SY = ±5V 4 9 V SY = ±5V 2 V SY = ±5V TO ±5V k k k M FREQUENCY (Hz) Figure 37. Common-Mode Rejection Ratio (CMRR) vs. Frequency, VSY = ±5 V to ±5 V Figure 39. Common-Mode Rejection Ratio (CMRR) vs. Temperature for Various Supply Voltages 4 35 V SY = ±4.5V TO ±55V TEMPERATURE ( C) PSRR (db) 6 4 +PSRR PSRR (db) 3 2 PSRR 25 V SY = ±5V TO ±5V 2 k k k M M FREQUENCY (Hz) Figure 38. Power Supply Rejection Ratio (PSRR) vs. Frequency, VSY = ±5 V to ±5 V TEMPERATURE ( C) Figure 4. Power Supply Rejection Ratio (PSRR) vs. Temperature Rev. Page 6 of 28

18 TA = 25 C, unless otherwise noted. V SY = ±5V A V = + V SY = ±5V A V = + A V = + Z OUT (Ω). A V = + Z OUT (Ω) A V = +. A V = k k k M M FREQUENCY (Hz) Figure 4. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V k k k M M FREQUENCY (Hz) Figure 44. Closed-Loop Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V INPUT VOLTAGE (V) 5 INPUT 6 INPUT VOLTAGE (V) 5 5 INPUT 2 OUTPUT V SY = ±5V V IN = 7.5V p-p A V = TIME (µs) Figure 42. Positive Output Overload Recovery, VSY = ±5 V 4 2 OUTPUT VOLTAGE (V) 55-6 OUTPUT V 4 SY = ±5V V IN = 7.5V p-p A V = TIME (µs) Figure 45. Negative Output Overload Recovery, VSY = ±5 V 2 OUTPUT VOLTAGE (V) V SY = ±5V A V = + 2 OUTPUT (V) 2 4 OUTPUT INPUT TIME (µs) Figure 43. No Phase Reversal, VSY = ±5 V Rev. Page 7 of 28

19 TA = 25 C, unless otherwise noted. VOLTAGE NOISE DENSITY (nv/ Hz) k V SY = ±5V TO ±5V V CM = V CURRENT NOISE DENSITY (pa/ Hz) V SY = ±5V TO ±5V V CM = V k k k FREQUENCY (Hz) k k FREQUENCY (Hz) Figure 46. Input Voltage Noise Density vs. Frequency Figure 48. Input Current Noise Density vs. Frequency INPUT REFERRED VOLTAGE (2nV/DIV) V SY = ±5V V CM = V INPUT REFERRED VOLTAGE (2nV/DIV) V SY = ±5V V CM = V TIME (s/div) TIME (s/div) Figure 47.. Hz to Hz Noise, VSY = ±5 V Figure 49.. Hz to Hz Noise, VSY = ±5 V Rev. Page 8 of 28

20 TA = 25 C, unless otherwise noted. VOLTAGE (V) C T A +25 C VOLTAGE (V) V SY = ±5V A V = + V OUT = ±45V R L = 2kΩ C L = 3pF +85 C +25 C 4 C +25 C.4 V SY = ±5V.6 A V = + R L = 2kΩ C L = 3pF TIME (µs) TIME (µs) Figure 5. Small Signal Transient Response, VSY = ±5 V Figure 53. Large Signal Transient Response, VSY = ±5 V SLEW RATE (V/µs) SR +SR V SY = ±5V A V = + V OUT = ±45V R L = 2kΩ C L = 3pF SETTLING TIME (µs) V SY = ±5V A V = R L = kω C L = 2pF.%.% TEMPERATURE ( C) Figure 5. Slew Rate (SR) vs. Temperature, VSY = ±5 V STEP SIZE (V) Figure 54..% and.% Settling Time vs. Step Size, VSY = ±5 V V SY = ±5V A V = R L = kω C L = 2pF.% 8 V SY = ±5V A V = R L = kω C L = 2pF.% SETTLING TIME (µs) 6 4.% SETTLING TIME (µs) 6 4.% STEP SIZE (V) Figure 52..% and.% Settling Time vs. Step Size, VSY = ±5 V STEP SIZE (V) Figure 55..% and.% Settling Time vs. Step Size, VSY = ±5 V Rev. Page 9 of 28

21 TEST CIRCUITS +5V V OUT 5V 75Ω V CONTROL 5V Figure 56. Test Circuit for Output Current Transient Settling Time (Sourcing) Shown in Figure V V CONTROL +5V 75Ω V OUT 5V Figure 57. Test Circuit for Output Current Transient Settling Time (Sinking) Shown in Figure Rev. Page 2 of 28

22 THEORY OF OPERATION V+ Q9 Q I I 3 I 2 Q Q5 C3 D5 Q7 R Q9 I 4 D6 D9 R3 Ω C +IN Q Q7 Q8 Q2 IN OUT D D3 Q3 Q5 D5 D6 Q6 D4 Q4 D2 D7 D8 D R4 Ω Q8 Q2 C2 R2 C4 Q4 Q6 I 5 I 6 Q2 Q3 Figure 58. Simplified Schematic of the V The is a high voltage operational amplifier featuring a slew enhanced bipolar input stage that provides all of the voltage gain. Single stage amplifiers are noted for their excellent stability but poor open-loop gain; however, the advanced design provides gain comparable to multistage amplifiers and, therefore, combines the advantages of both. Referring to Figure 58, the input stage is formed by Q5 to Q8 loaded by the current mirrors, Q9 to Q4. The output stage is of the complementary Darlington type formed by Q5 to Q8. Like other bipolar amplifiers, the input stage is internally clamped to prevent degradation with large differential inputs; however, the addition of Q and Q2 in conjunction with the high voltage diodes, D and D2, maintain high differential input impedance even when the voltage between the inputs is equal to the supply voltage. This configuration makes the suitable for applications with unavoidable large differential voltages, such as rectifiers, peak detectors, and comparators. The uses a single-pole compensation set by C3 and C4. The internal snubber networks, R/C and R2/C2, further enhance the stability. This design enables large capacitive loads to be driven without the risk of oscillation. The Q9 and Q2 transistors in conjunction with the R3 and R4 resistors provide output short-circuit protection. Additionally, a thermal regulating circuit (not shown in Figure 58) limits the die temperature to 45 C or greater to protect against excessive power dissipation. With approximately equal split supplies up to ±5 V, the output can be shorted to ground unconditionally; however, operating this way is not recommended. If the voltage between the output and either supply is more than 6 V, avoid a short circuit to the supply. Transient dissipation in the output transistors can exceed their safe operating area and cause subsequent destruction. THERMAL REGULATION The circuitry for thermal regulation of the is dependent on the ambient temperature and time duration of the current drive. When thermal regulation of the is active, the supply current, ISY, reduces from.7 ma to 3 µa. The output stage remains biased during thermal regulation due to the parasitics of the output devices in conjunction with the elevated die temperature. For example, with a current drive, IOUT, of 3 ma for 8 seconds and with an ambient temperature of 85 C, the thermal regulation is triggered at a junction temperature of 45 C with an output current level of 22 ma. For additional information, refer to the Thermal Management section and the Safe Operating Area section. Rev. Page 2 of 28

23 APPLICATIONS INFORMATION THERMAL MANAGEMENT Thermal management of high power amplifiers such as the is an essential consideration in system design. Two conditions affect junction temperature (TJ): power dissipation (PD) of the device and ambient temperature (TA) surrounding the package. This relationship is shown in Equation. TJ = PD θja + TA () where θja is the thermal resistance between the die and the ambient environment. Power dissipation is the sum of quiescent power of the device and the power required to drive a load. Power dissipation for the sourcing current is shown in Equation 2. PD = ((V+) (V )) ISY + ((V+) VOUT) IOUT (2) Replace ((V+) VOUT) in Equation 2 with ((V ) VOUT) when sinking current. The specified thermal resistance of the is 45 C/W. Printed circuit board (PCB) layout and an external heat sink can improve thermal performance by reducing θja. To reduce the thermal resistance between the junction and ambient environment, the exposed pad of the can be soldered to the V plane layer of the PCB, which acts as a heat sink. By using the PCB layout shown in Figure 6, θja reduces to 26 C/W. The guards the die from exceeding the absolute maximum temperature. When the die reaches a junction temperature greater than 45 C, thermal regulation is triggered, the supply current is reduced, and the output load current is limited. SAFE OPERATING AREA The safe operating area (SOA) of Figure 59 is the range of voltages, currents, and temperatures under which an amplifier can safely operate without failure. It is directly dependent on the ambient temperature and the thermal resistance. Figure 59 shows the SOA for the at steady state using the PCB shown in Figure 6. The duration of the 3 ma load driven is 8 seconds. Different time intervals produce alternate sets of curves. The guaranteed ambient temperature range of the is 4 C to +85 C. The 25 C shown in Figure 59 is for reference only. To maintain normal operation, the must remain in the SOA (area under each curve) up to an ambient temperature of 85 C. I OUT (ma) θ JA = 26 C/W V+ = +6V TO +V V OUT +25 C + Ω 5 +3V V = 3V V CC V OUT (V) Figure 59. Safe Operating Area with θja = 26 C/W 4 C +25 C +85 C LAYER FR4 PCB WITH INTERNAL GROUND AND POWER PLANE. COPPER TOP/BOTTOM:.5oz INTERNAL LAYERS: oz 9.65mm (38mil) 2.7mm (5mil) a b LANDING VIAS: EPOXY FILLED ARRAY: 3 4 DIAMETER: a =.348mm (2mil) PITCH: b =.762mm (3mil) 6.mm (24mil) PAD mm (mil) 9.65mm (38mil) Figure 6. Thermal Landing and PCB Material Used to Obtain a θja of 26 C/W c PADDLE VIAS: EPOXY FILLED ARRAY: 8 DIAMETER: a =.348mm (2mil) PITCH: c =.27mm (5mil) 55-3 Rev. Page 22 of 28

24 DRIVING CAPACITIVE LOADS Although the behaves well when driving capacitive loads, CL, as seen in Figure 27 to Figure 3, extra compensation can improve the response when large capacitances need to be accommodated. The simplest way of accomplishing this is with a snubber network, as shown in Figure 6. V IN R SNUB Figure 6. Snubber Network V OUT For unity-gain applications and capacitive loads up to nf, RSNUB = 5 Ω and CSNUB = nf works well. Results for this circuit are shown in Figure 64. With higher closed-loop gains, lighter snubbing can be used. For capacitive loads up to nf, the snubber must be larger. Figure 65 shows the results of using an RSNUB = 22 Ω, CSNUB = nf, and CL = nf with the in a gain of. Because the snubber network places an ac load on the amplifier, snubbing does not work well when larger capacitive loads are used, or when large transients are present. A better approach is to use a bypass network in the feedback path, as shown in Figure 62. V IN C SNUB Figure 62. Unity-Gain Configuration with Bypass Network The bypass network in Figure 62 performs well with loads up to nf. The resulting waveforms are shown in Figure 66 for various output amplitudes. For heavier loads, capacitive feedback, CFB, must be increased. The configuration in Figure 62 can be modified to work with gains greater than. Figure 63 shows a bypass network with a gain of system, and results for various output amplitudes are shown in Figure 67. V IN 5.kΩ C FB nf 3.3kΩ 43kΩ C FB 22Ω 22Ω 3.3kΩ Figure 63. Bypass Network with Gain of System C L CL C L V OUT V OUT VOLTAGE (V) OUTPUT 6 INPUT V SY = ±5V 8 A V = + C L = pf TO nf TIME (µs) Figure 64. Results from Snubber Network with AV = + and CL = pf to nf OUTPUT (V) TIME (ms) Figure 65. Results from Snubber Network with Higher Gains, CL = nf OUTPUT (V) V SY = ±5V A V = + C L = nf V SY = ±5V A V = + C L = nf TIME (ms) Figure 66. Results of Bypass Network for Various Output Amplitudes, Unity Gain with CL = nf Rev. Page 23 of 28

25 OUTPUT (V) V SY = ±5V A V = + C L = nf CONSTANT CURRENT APPLICATIONS When a constant current with high compliance is needed, the can be used as a modified Howland current pump. The values shown in Figure 7 yield a transfer function of ma/v. Applying this analysis to the modified Howland current pump in Figure 7 results in an output capability of A/V. +V IN R kω R2 5kΩ R SET 5Ω IF R 2 = R 4 + R SET AND R = R 3 V I OUT = IN R 2 R SET R 5.5. TIME (ms) Figure 67. Result of Bypass Network with AV = + and CL = nf INCREASING CURRENT DRIVE.5 2. Extra output current can be obtained by adding external driver transistors. Crossover distortion is minimized by allowing the amplifier to drive the lower currents directly via the bypass resistor, as is shown in Figure 68. This circuit can provide a few hundred miliamps; however, keep the driver transistors within their safe operating area. For heavier loads (up to 5 A), power Darlingtons can be used, as is shown in Figure 69. V IN 8Ω 2N555 2N54 Figure 68. Increasing Current Drive Using Discrete Transistors +V I OUT +V kΩ kω R3 kω R4 49.5kΩ Figure 7. Transfer Function of ma/v BDW93C I OUT 2kΩ V IN 27Ω.5Ω kω BDW94C Figure 7. Modified Howland Current Pump V I OUT V BDW93C +V V IN 27Ω I OUT BDW94C V Figure 69. Bilateral Current Source with Transfer Function ma/v 55-9 Rev. Page 24 of 28

26 OUTLINE DIMENSIONS SEATING PLANE.27 BSC TOP VIEW REF MAX.5 NOM COPLANARITY BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MS-2-AA Figure Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-2) Dimensions shown in millimeters 45.4 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET B ORDERING GUIDE Model Temperature Range Package Description Package Option ARDZ 4 C to +85 C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-2 ARDZ-R7 4 C to +85 C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-2 ARDZ-RL 4 C to +85 C 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] RD-8-2 Z = RoHS Compliant Part. Rev. Page 25 of 28

27 NOTES Rev. Page 26 of 28

28 NOTES Rev. Page 27 of 28

29 NOTES 23 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D55--8/3() Rev. Page 28 of 28