ADA4857-1/ADA Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp. Data Sheet FEATURES CONNECTION DIAGRAMS APPLICATIONS

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1 FEATURES High speed 85 MHz, db bandwidth (G =, RL = kω, LFCSP) 75 MHz, db bandwidth (G =, RL = kω, SOIC) 8 V/μs slew rate Low distortion: 88 dbc at MHz (G =, RL = kω) Low power: 5 ma/amplifier at V Low noise: 4.4 nv/ Hz Wide supply voltage range: 5 V to V Power-down feature Available in mm mm 8-lead LFCSP (single), 8-lead SOIC (single), and 4 mm 4 mm 6-lead LFCSP (dual) APPLICATIONS Instrumentation IF and baseband amplifiers Active filters ADC drivers DAC buffers Ultralow Distortion, Low Power, Low Noise, High Speed Op Amp ADA4857-/ADA4857- CONNECTION DIAGRAMS PD FB IN IN 4 ADA4857- TOP VIEW (Not to Scale) 8 V S 7 OUT 6 NC 5 V S NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.. THE EXPOSED PAD MAY BE CONNECTED TO GND OR VS. Figure. 8-Lead LFCSP (CP) ADA4857- TOP VIEW (Not to Scale) FB IN IN V S 4 8 PD 7 V S 6 OUT 5 NC NC = NO CONNECT Figure. 8-Lead SOIC (R) ADA4857- TOP VIEW (Not to Scale) FB PD V S OUT IN IN NC V S 4 9 V S NC IN IN GENERAL DESCRIPTION The ADA4857 is a unity-gain stable, high speed, voltage feedback amplifier with low distortion, low noise, and high slew rate. With a spurious-free dynamic range (SFDR) of 88 dbc at MHz, the ADA4857 is an ideal solution for a variety of applications, including ultrasounds, ATE, active filters, and ADC drivers. The Analog Devices, Inc., proprietary next-generation XFCB process and innovative architecture enables such high performance amplifiers. The ADA4857 has 85 MHz bandwidth, 8 V/μs slew rate, and settles to.% in 5 ns. With a wide supply voltage range (5 V to Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. OUT V S PD FB NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.. THE EXPOSED PAD MAY BE CONNECTED TO GND OR VS. Figure. 6-Lead LFCSP (CP) V), the ADA4857 is an ideal candidate for systems that require high dynamic range, precision, and speed. The ADA4857- amplifier is available in a mm mm, 8-lead LFCSP and a standard 8-lead SOIC. The ADA4857- is available in a 4 mm 4 mm, 6-lead LFCSP. The LFCSP features an exposed paddle that provides a low thermal resistance path to the printed circuit board (PCB). This path enables more efficient heat transfer and increases reliability. The ADA4857 works over the extended industrial temperature range ( 4 C to 5 C). One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support 74-

2 ADA4857-/ADA4857- TABLE OF CONTENTS Features... Applications... Connection Diagrams... General Description... Revision History... Specifications... ±5 V Supply... 5 V Supply... 4 Absolute Maximum Ratings... 6 Thermal Resistance... 6 Maximum Power Dissipation... 6 ESD Caution... 6 Pin Configurations and Function Descriptions... 7 Typical Performance Characteristics... 9 Test Circuits... 6 Applications Information... 7 Power-Down Operation... 7 Capacitive Load Considerations... 7 Recommended Values for Various Gains... 7 Active Low-Pass Filter (LPF)... 8 Noise... 9 Circuit Considerations... 9 PCB Layout... 9 Power Supply Bypassing... 9 Grounding... 9 Outline Dimensions... Ordering Guide... REVISION HISTORY /7 Rev. C to Rev. D Changes to Figure... Changes to Table... Changes to Table... 4 Changes to Figure Added Figure 4 and Figure 4; Renumbered Sequentially... 4 Added Figure 44, Figure 45, Figure 46, Figure 47, and Figure Changes to Power-Down Operation Section... 7 Updated Outline Dimensions... Changes to Ordering Guide... 9/ Rev. B to Rev. C Changes to Figure and Figure... Change to Figure Change to Figure Updated Outline Dimensions... Changes to Ordering Guide... /8 Rev. to Rev. A Changes to Table Changes to Table Changes to Figure... Added Figure 44; Renumbered Sequentially... 5 Changes to Layout... 5 Changes to Table Added Active Low-Pass Filter (LFP) Section... 7 Added Figure 48 and Figure 49; Renumbered Sequentially... 7 Changes to Grounding Section... 8 Exposed Paddle Notation Added to Outline Dimensions... 9 Changes to Ordering Guide... 5/8 Revision : Initial Version 8/ Rev. A to Rev. B Changes to Table Conditions... Changes to Table Conditions... 4 Changes to Typical Performance Characteristics Conditions... 9 Changes to Figure 8... Changes to Figure Changes to Table Changes to Ordering Guide... Rev. D Page of

3 ADA4857-/ADA4857- SPECIFICATIONS ±5 V SUPPLY TA = 5 C, G =, RG = RF = 499 Ω, RS = Ω for G = (SOIC), RL = kω to ground, PD = no connect, unless otherwise noted. Table. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth (LFCSP/SOIC) Gain (G) =, VOUT =. V p-p 65 85/75 MHz G =, VOUT = V p-p 6/55 MHz G =, VOUT =. V p-p 4/5 MHz Full Power Bandwidth G =, VOUT = V p-p, THD < 4 dbc MHz Bandwidth for. db Flatness G =, VOUT = V p-p, RL = 5 Ω 75/9 MHz (LFCSP/SOIC) Slew Rate (% to 9%) G =, VOUT = 4 V step 8 V/μs Settling Time to.% G =, VOUT = V step 5 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = MHz, G =, VOUT = V p-p (HD) 8 dbc f = MHz, G =, VOUT = V p-p (HD) 8 dbc f = MHz, G =, VOUT = V p-p (HD) 88 dbc f = MHz, G =, VOUT = V p-p (HD) 9 dbc f = 5 MHz, G =, VOUT = V p-p (HD) 65 dbc f = 5 MHz, G =, VOUT = V p-p (HD) 6 dbc Input Voltage Noise f = khz 4.4 nv/ Hz Input Current Noise f = khz.5 pa/ Hz DC PERFORMANCE Input Offset Voltage ± ±4.5 mv TMIN to TMAX ±7. mv Input Offset Voltage Drift TMIN to TMAX. μv/ C Input Bias Current. μa TMIN to TMAX.8 μa Input Bias Offset Current 5 8 na Open-Loop Gain VOUT =.5 V to.5 V 57 db PD (POWER-DOWN) PIN PD Input Voltage Chip powered down (VS ) V Chip powered down, TMIN to TMAX (VS.7) V Chip enabled (VS 4.) V Chip enabled, TMIN to TMAX (VS 5.) V Turn-Off Time 5% off PD to <% of final VOUT, VIN = V, G = 55 μs Turn-On Time 5% off PD to <% of final VOUT, VIN = V, G = ns PD Pin Leakage Current Chip enabled 58 μa Chip powered down 8 μa INPUT CHARACTERISTICS Input Resistance Common mode 8 MΩ Differential mode 4 MΩ Input Capacitance Common mode pf Input Common-Mode Voltage ±4 V Range Common-Mode Rejection Ratio VCM = ± V db VCM =.6 V to.7 V, TMIN to TMAX 7 db Rev. D Page of

4 ADA4857-/ADA4857- Parameter Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Overdrive Recovery Time VIN = ±.5 V, G = ns Output Voltage Swing High RL = kω VS V RL = kω, TMIN to TMAX VS. V RL = Ω VS. V RL = Ω, TMIN to TMAX VS V Low RL = kω VS V RL = kω, TMIN to TMAX VS. V RL = Ω VS. V RL = Ω, TMIN to TMAX VS V Output Current 5 ma Short-Circuit Current Sinking and sourcing 5 ma Capacitive Load Drive % overshoot, G = pf POWER SUPPLY Operating Range V Quiescent Current ma Quiescent Current (Power Down) PD VCC V 5 45 μa Positive Power Supply Rejection VS = 4.5 V to 5.5 V, VS = 5 V 59 6 db Negative Power Supply Rejection VS = 5 V, VS = 4.5 V to 5.5 V db 5 V SUPPLY TA = 5 C, G =, RF = RG = 499 Ω, RS = Ω for G = (SOIC), RL = kω to midsupply, PD = no connect, unless otherwise noted. Table. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth (LFCSP/SOIC) G =, VOUT =. V p-p 595 8/75 MHz G =, VOUT = V p-p 5/4 MHz G =, VOUT =. V p-p 6/ MHz Full Power Bandwidth G =, VOUT = V p-p, THD < 4 dbc 95 MHz Bandwidth for. db Flatness G =, VOUT = V p-p, RL = 5 Ω 5/4 MHz (LFCSP/SOIC) Slew Rate (% to 9%) G =, VOUT = V step 5 V/μs Settling Time to.% G =, VOUT = V step 5 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion f = MHz, G =, VOUT = V p-p (HD) 9 dbc f = MHz, G =, VOUT = V p-p (HD) 9 dbc f = MHz, G =, VOUT = V p-p (HD) 8 dbc f = MHz, G =, VOUT = V p-p (HD) 7 dbc f = 5 MHz, G =, VOUT = V p-p (HD) 69 dbc f = 5 MHz, G =, VOUT = V p-p (HD) 55 dbc Input Voltage Noise f = khz 4.4 nv/ Hz Input Current Noise f = khz.5 pa/ Hz DC PERFORMANCE Input Offset Voltage ± ±4. mv TMIN to TMAX ±6.4 mv Input Offset Voltage Drift TMIN to TMAX 4.6 μv/ C Input Bias Current.7. μa TMIN to TMAX 4. μa Input Bias Offset Current 5 8 na Open-Loop Gain VOUT =.5 V to.75 V 57 db Rev. D Page 4 of

5 ADA4857-/ADA4857- Parameter Test Conditions/Comments Min Typ Max Unit PD (POWER-DOWN) PIN PD Input Voltage Chip powered down (VS ) V Chip powered down, TMIN to TMAX (VS.4) V Chip enabled (VS 4.) V Chip enabled, TMIN to TMAX (VS 4.8) V Turn-Off Time 5% off PD to <% of final VOUT, VIN = 8 µs V, G = Turn-On Time 5% off PD to <% of final VOUT, VIN = ns V, G = PD Pin Leakage Current Chip enable 8 µa Chip powered down µa INPUT CHARACTERISTICS Input Resistance Common mode 8 MΩ Differential mode 4 MΩ Input Capacitance Common mode pf Input Common-Mode Voltage Range to 4 V Common-Mode Rejection Ratio VCM = V to V db VCM =. V to.7 V, TMIN to TMAX 7 db OUTPUT CHARACTERISTICS Overdrive Recovery Time G = 5 ns Output Voltage Swing High RL = kω VS V RL = kω, TMIN to TMAX VS. V RL = Ω VS. V RL = Ω, TMIN to TMAX VS.7 V Low RL = kω VS V RL = kω, TMIN to TMAX VS. V RL = Ω VS. V RL = Ω, TMIN to TMAX VS.6 V Output Current 5 ma Short-Circuit Current Sinking and sourcing 75 ma Capacitive Load Drive % overshoot, G = pf POWER SUPPLY Operating Range V Quiescent Current ma Quiescent Current (Power Down) PD VCC V 5 5 µa Positive Power Supply Rejection VS = 4.5 V to 5.5 V, VS = V 58 6 db Negative Power Supply Rejection VS = 5 V, VS =.5 V to.5 V db Rev. D Page 5 of

6 ADA4857-/ADA4857- ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage V Power Dissipation See Figure 4 Common-Mode Input Voltage VS.7 V to VS.7 V Differential Input Voltage ±VS Exposed Paddle Voltage VS Storage Temperature Range 65 C to 5 C Operating Temperature Range 4 C to 5 C Lead Temperature (Soldering, sec) C Junction Temperature 5 C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, θja is specified for device soldered in circuit board for surface-mount packages. Table 4. Package Type θja θjc Unit 8-Lead SOIC 5 5 C/W 8-Lead LFCSP C/W 6-Lead LFCSP C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the ADA4857 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 5 C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4857. Exceeding a junction temperature of 75 C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4857 drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power (Total Drive Power Load Power) P D = ( V I ) S S V V S OUT R L V R OUT RMS output voltages must be considered. If RL is referenced to VS, as in single-supply operation, the total drive power is VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. P D = ( V I ) S S ( V /4) S R L In single-supply operation with RL referenced to VS, the worst case is VOUT = VS/. Airflow increases heat dissipation, effectively reducing θja. In addition, more metal directly in contact with the package leads and exposed paddle from metal traces, through holes, ground, and power planes reduces θja. Figure 4 shows the maximum power dissipation in the package vs. the ambient temperature for the SOIC and LFCSP packages on a JEDEC standard 4-layer board. θja values are approximations. MAXIMUM POWER DISSIPATION (W) Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ADA4857- (LFCSP) AMBIENT TEMPERATURE ( C) L ADA4857- (LFCSP) ADA4857- (SOIC) 74-4 Rev. D Page 6 of

7 ADA4857-/ADA4857- PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PD FB IN IN 4 ADA4857- TOP VIEW (Not to Scale) 8 V S 7 OUT 6 NC 5 V S NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.. THE EXPOSED PAD MAY BE CONNECTED TO GND OR VS. Figure 5. 8-Lead LFCSP Pin Configuration 74-5 FB IN ADA4857- IN TOP VIEW (Not to Scale) V S 4 NC = NO CONNECT 8 PD 7 V S 6 OUT 5 NC Figure 6. 8-Lead SOIC Pin Configuration 74-6 Table 5. 8-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description PD Power Down. FB Feedback. IN Inverting Input. 4 IN Noninverting Input. 5 VS Negative Supply. 6 NC No Connect. 7 OUT Output. 8 VS Positive Supply. EP GND or VS Exposed Pad. The exposed pad may be connected to GND or VS. Table 6. 8-Lead SOIC Pin Function Descriptions Pin No. Mnemonic Description FB Feedback. IN Inverting Input. IN Noninverting Input. 4 VS Negative Supply. 5 NC No Connect. 6 OUT Output. 7 VS Positive Supply. 8 PD Power Down. Rev. D Page 7 of

8 ADA4857-/ADA4857- FB PD V S OUT IN IN NC V S ADA4857- TOP VIEW (Not to Scale) 4 9 V S NC IN IN OUT V S PD NOTES. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.. THE EXPOSED PAD MAY BE CONNECTED TO GND OR VS. Figure 7. 6-Lead LFCSP Pin Configuration Table 7. 6-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description IN Inverting Input. IN Noninverting Input., NC No Connect. 4 VS Negative Supply. 5 OUT Output. 6 VS Positive Supply. 7 PD Power Down. 8 FB Feedback. 9 IN Inverting Input. IN Noninverting Input. VS Negative Supply. OUT Output. 4 VS Positive Supply. 5 PD Power Down. 6 FB Feedback. EP GND or VS Exposed Pad. The exposed pad may be connected to GND or VS. FB 74-7 Rev. D Page 8 of

9 ADA4857-/ADA4857- TYPICAL PERFORMANCE CHARACTERISTICS T = 5 C, G =, RF = Ω, and, RG open, RS = Ω for SOIC, (for G =, RF = RG = 499 Ω), unless otherwise noted. NORMALIZED CLOSED-LOOP GAIN (db) 5 7 G = G = R L = kω V OUT =.V p-p G = G = Figure 8. Small Signal Frequency Responses for Various Gains (LFCSP) 74-8 NORMALIZED CLOSED-LOOP GAIN (db) 5 7 G = G = R L = kω V OUT = V p-p G = G = Figure. Large Signal Frequency Responses for Various Gains (LFCSP) 74- CLOSED-LOOP GAIN (db) G = 9 R L = kω V OUT =.V p-p Figure 9. Small Signal Frequency Response for Various Supply Voltages (LFCSP) 5V ±5V 74-9 CLOSED-LOOP GAIN (db) NO CAP LOAD G = 5 R L = kω V OUT =.V p-p 7 pf Figure. Small Signal Frequency Response for Various Capacitive Loads (LFCSP) 5pF 74- CLOSED-LOOP GAIN (db) G = 5 C 9 R L = kω V OUT =.V p-p 5 C C 74- CLOSED-LOOP GAIN (db) 5 7 4V p-p 8 G = 9 R L = Ω V p-p 74- Figure. Small Signal Frequency Response for Various Temperatures (LFCSP) Figure. Large Signal Frequency Response vs. VOUT (LFCSP) Rev. D Page 9 of

10 ADA4857-/ADA4857- CLOSED-LOOP GAIN (db) R L = Ω 5 G = V OUT =.V p-p 7 R L = kω Figure 4. Small Signal Frequency Response for Various Resistive Loads (LFCSP) 74-4 CLOSED-LOOP GAIN (db) 5 7 R L = Ω 8 G = 9 V OUT = V p-p R L = kω Figure 7. Large Signal Frequency Response for Various Resistive Loads (LFCSP) 74-7 NORMALIZED CLOSED-LOOP GAIN (db) 5 7 G = G = 5 8 V S = 5V 9 R L = kω V OUT =.V p-p G = G = Figure 5. Small Signal Frequency Response for Various Gains (LFCSP) 74-5 NORMALIZED CLOSED-LOOP GAIN (db) 5 7 V IN G = R T R S Ω G = G = 5 V S V S R L V OUT 8 9 R L = kω V OUT =.V p-p G = G = Figure 8. Small Signal Frequency Response for Various Gains (SOIC), RS = Ω for G = V OUT = V p-p R L = kω 5 G = V OUT = V p-p DISTORTION (dbc) G =, HD G =, HD G =, HD DISTORTION (dbc) R L = Ω, HD R L = Ω, HD R L = kω, HD G =, HD. Figure 6. Harmonic Distortion vs. Frequency and Gain (LFCSP) 74-6 R L = kω, HD. Figure 9. Harmonic Distortion vs. Frequency and Load (LFCSP) 74-9 Rev. D Page of

11 ADA4857-/ADA4857- DISTORTION (dbc) G = R L = kω HD, f = MHz HD, f = MHz HD, f = MHz HD, f = MHz OUTPUT VOLTAGE (V p-p) 74- SETTLING TIME (%) INPUT OUTPUT TIME (5ns/DIV) V OUT = V p-p G = V S = ±5 74- Figure. Harmonic Distortion vs. Output Voltage Figure. Short-Term Settling Time (LFCSP) G = R L = 5Ω G = R L = 5Ω CLOSED-LOOP GAIN (db) V OUT =.V p-p V OUT = V p-p CLOSED-LOOP GAIN (db) V OUT =.V p-p V OUT = V p-p 5.7 Figure.. db Flatness vs. Frequency for Various Output Voltages (SOIC) Figure 4.. db Flatness vs. Frequency for Various Output Voltages (LFCSP) 74-4 OUTPUT VOLTAGE (V) V p-p V p-p R L = kω G = OUTPUT VOLTAGE (V) V p-p V p-p R L = kω G = TIME (ns/div) Figure. Large Signal Transient Response for Various Output Voltages (SOIC) TIME (ns/div) Figure 5. Large Signal Transient Response for Various Output Voltages (LFCSP) 74-5 Rev. D Page of

12 ADA4857-/ADA R L = kω G =..6. G = OUTPUT VOLTAGE (V) C L =.5pF OUTPUT VOLTAGE (V) R L = kω.5 C L = pf..5 TIME (ns/div) Figure 6. Small Signal Transient Response for Various Capacitive Loads (LFCSP) R L = Ω.6. TIME (ns/div) Figure 9. Large Signal Transient Response for Various Load Resistances (SOIC) R L = kω G =..6. R L = kω G = OUTPUT VOLTAGE (V) V S = ±.5V OUTPUT VOLTAGE (V) TIME (ns/div) Figure 7. Small Signal Transient Response for Various Supply Voltages (LFCSP) R L = Ω.6. TIME (ns/div) Figure. Large Signal Transient Response for Various Load Resistances (LFCSP) 74- CLOSED-LOOP OUTPUT IMPEDANCE (Ω) G = 5 G = CLOSED-LOOP INPUT IMPEDANCE (kω). G =.. Figure 8. Closed-Loop Output Impedance vs. Frequency for Various Gains Figure. Closed-Loop Input Impedance vs. Frequency 74- Rev. D Page of

13 ADA4857-/ADA4857- OPEN-LOOP GAIN (db) GAIN PHASE R L = kω 8 OPEN-LOOP PHASE (Degrees) PD ISOLATION (db) G = R L = kω PD = V LFCSP SOIC Figure. Open-Loop Gain and Phase vs. Frequency Figure 5. PD Isolation vs. Frequency 8 6 G = 8 6 G = OUTPUT VOLTAGE (V) 4 8 INPUT OUTPUT R L = Ω OUTPUT R L = kω TIME (4ns/DIV) Figure. Input Overdrive Recovery for Various Resistive Loads 74- OUTPUT VOLTAGE (V) 4 8 INPUT OUTPUT R L = kω OUTPUT R L = Ω TIME (ns/div) Figure 6. Output Overdrive Recovery for Various Resistive Loads 74-6 R L = kω 5 R L = kω PSRR (db) CMRR (db) 5 PSRR 7 7 PSRR 8. Figure 4. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 7. Common-Mode Rejection Ratio (CMRR) vs. Frequency 74-7 Rev. D Page of

14 ADA4857-/ADA4857- CURRENT NOISE (pa/ Hz) VOLTAGE NOISE (nv/ Hz) k k k M FREQUENCY (Hz) 74-5 k k k M FREQUENCY (Hz) 74-4 Figure 8. Input Current Noise vs. Frequency Figure 4. Input Voltage Noise vs. Frequency 5 N = 8 MEAN: 5. SD: PD INPUT COUNT VOLTAGE (V) SUPPLY CURRENT (ma) OUTPUT TIME (µs/div) 74-4 Figure 9. Supply Current Figure 4. Disable/Enable Switching Speed V S = 5V NUMBER OF AMPLIFIERS 5 5 NUMBER OF AMPLIFIERS INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE (mv) 74-4 Figure 4. Input Offset Voltage Distribution, VS = ±5 V Figure 4. Input Offset Voltage Distribution, VS = 5 V Rev. D Page 4 of

15 ADA4857-/ADA NUMBER OF AMPLIFIERS 5 4 C 5C NUMBER OF AMPLIFIERS V S = 5V C 5C INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE (mv) Figure 44. Input Offset Voltage Distribution over Temperature, VS = ±5 V Figure 47. Input Offset Voltage Distribution over Temperature, VS = 5 V 5 V S = 5V 5 NUMBER OF AMPLIFIERS 5 NUMBER OF AMPLIFIERS INPUT OFFSET VOLTAGE DRIFT (µv/ C) Figure 45. Input Offset Voltage Drift Distribution, VS = ±5 V INPUT OFFSET VOLTAGE DRIFT (µv/ C) Figure 48. Input Offset Voltage Drift Distribution, VS = 5 V COMMON-MODE REJECTION (µv/v) 5 4 COMMON-MODE VOLTAGE (V) Figure 46. Common-Mode Rejection vs. Common-Mode Voltage Rev. D Page 5 of

16 ADA4857-/ADA4857- TEST CIRCUITS µf V S µf V S kω.µf.µf kω.µf.µf IN R L V R S V OUT 49.9Ω µf.µf V S V IN kω 5.6Ω kω µf V S.µF R L V OUT Figure 49. Noninverting Load Configuration Figure 5. Common-Mode Rejection V S V S AC 49.9Ω µf.µf V OUT V OUT µf V S.µF R L AC V S 49.9Ω R L Figure 5. Positive Power Supply Rejection Figure 5. Negative Power Supply Rejection µf V S µf V S R G R F.µF V IN 49.9Ω µf.µf V S.µF V OUT C L R L Figure 5. Typical Capacitive Load Configuration (LFCSP) 74-5 V IN R G R F.µF.µF 4Ω V R OUT SNUB C L R L 49.9Ω µf.µf V S Figure 54. Typical Capacitive Load Configuration (SOIC) Rev. D Page 6 of

17 APPLICATIONS INFORMATION POWER-DOWN OPERATION The PD pin powers down the chip, reducing the quiescent current and the overall power consumption. To enable the device, pull the PD pin low. Table 8 provides the PD pin voltages that enable the correct operation at different supplies. These voltages are applicable for ambient temperature only. Consult Table and Table when designing for use at the full operating temperature range. Note that PD does not put the output in a high-z state, which means that the ADA4857 must not be used as a multiplexer. ADA4857-/ADA4857- CAPACITIVE LOAD CONSIDERATIONS When driving a capacitive load using the SOIC package, RSNUB reduces the peaking (see Figure 54). An optimum resistor value of 4 Ω is found to maintain the peaking within db for any capacitive load up to 4 pf. RECOMMENDED VALUES FOR VARIOUS GAINS Table 9 provides a useful reference for determining various gains and associated performance. RF and RG are kept low to minimize their contribution to the overall noise performance of the amplifier. Table 8. PD Operation Table Guide Supply Voltage Condition ±5 V ±.5 V 5 V Enabled.8 V.7 V.8 V Powered down V.5 V V Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 5 C, RL = kω, RT = 49.9 Ω Gain RS (Ω) (CSP/SOIC) RF (Ω) RG (Ω) db SS BW (MHz) (CSP/SOIC) Slew Rate (V/µs), VOUT = V Step ADA4857 Voltage Noise (nv/ Hz), RTO Total System Noise (nv/ Hz), RTO / N/A 85/ / / / / / / Rev. D Page 7 of

18 ADA4857-/ADA4857- ACTIVE LOW-PASS FILTER (LPF) Active filters are used in many applications such as antialiasing filters and high frequency communication IF strips. With a 4 MHz gain bandwidth product and high slew rate, the ADA4857- is an ideal candidate for active filters. Figure 55 shows the frequency response of 9 MHz and 45 MHz LPFs. In addition to the bandwidth requirements, the slew rate must be capable of supporting the full power bandwidth of the filter. In this case, a 9 MHz bandwidth with a V p-p output swing requires at least 8 V/μs. The circuit shown in Figure 56 is a 4-pole, Sallen-Key LPF. The filter comprises two identical cascaded Sallen-Key LPF sections, each with a fixed gain of G =. The net gain of the filter is equal to G = 4 or db. The actual gain shown in Figure 55 is db. This does not take into account the output voltage being divided in half by the series matching termination resistor, RT, and the load resistor. Setting the resistors equal to each other greatly simplifies the design equations for the Sallen-Key filter. To achieve 9 MHz, the value of R must be set to 8 Ω. However, if the value of R is doubled, the corner frequency is cut in half to 45 MHz. This would be an easy way to tune the filter by simply multiplying the value of R (8 Ω) by the ratio of 9 MHz and the new corner frequency in megahertz. C.9pF Figure 55 shows the output of each stage is of the filter and the two different filters corresponding to R = 8 Ω and R = 65 Ω. Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. Due to the low capacitance values used in the filter circuit, the PCB layout and minimization of parasitics is critical. A few picofarads can detune the corner frequency, fc of the filter. The capacitor values shown in Figure 56 actually incorporate some stray PCB capacitance. Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors and silver mica, are good choices for filter elements. MAGNITUDE (db) R L = Ω OUT, f = 9MHz OUT, f = 45MHz OUT, f = 9MHz OUT, f = 45MHz. 5 Figure 55. Low-Pass Filter Response C.9pF V µf 5V µf IN R T 49.9Ω R R C 5.6pF U.µF µf R OUT R C4 5.6pF U.µF µf R T 49.9Ω OUT R 48Ω 5V.µF R 48Ω R4 48Ω 5V.µF R 48Ω Figure Pole, Sallen-Key Low-Pass Filter (ADA4857-) Rev. D Page 8 of

19 NOISE To analyze the noise performance of an amplifier circuit, identify the noise sources and determine if the source has a significant contribution to the overall noise performance of the amplifier. To simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions (noise spectral density, which is generally expressed in nv/ Hz, is equivalent to the noise in a Hz bandwidth). The noise model shown in Figure 57 has six individual noise sources: the Johnson noise of the three resistors, the operational amplifier voltage noise, and the current noise in each input of the amplifier. Each noise source has its own contribution to the noise at the output. Noise is generally referred to input (RTI), but it is often easier to calculate the noise referred to the output (RTO) and then divide by the noise gain to obtain the RTI noise. B A V N, R 4kTR V N, R 4kTR R R RTI NOISE = RTO NOISE = NG RTI NOISE Figure 57. Operational Amplifier Noise Analysis Model All resistors have Johnson noise that is calculated by ( 4kBTR ) I N I N V N V N, R 4kTR GAIN FROM A TO OUTPUT = NOISE GAIN = R NG = R GAIN FROM B TO OUTPUT = R R where: k is Boltzmann s Constant (.8 J/K). B is the bandwidth in Hertz. T is the absolute temperature in Kelvin. R is the resistance in ohms. A simple relationship that is easy to remember is that a 5 Ω resistor generates a Johnson noise of nv/ Hz at 5 C. In applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. Each resistor is a noise source. Attention to the following areas is critical to maintain low noise performance: design, layout, and component selection. A summary of noise performance for the amplifier and associated resistors can be seen in Table 9. R V N 4kTR 4kTR R R R V OUT I N R I R R N 4kTR R R R R R 74-7 ADA4857-/ADA4857- CIRCUIT CONSIDERATIONS Careful and deliberate attention to detail when laying out the ADA4857 board yields optimal performance. Power supply bypassing, parasitic capacitance, and component selection all contribute to the overall performance of the amplifier. PCB LAYOUT Because the ADA4857 can operate up to 85 MHz, it is essential that RF board layout techniques be employed. All ground and power planes under the pins of the ADA4857 must be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. A single mounting pad on the SOIC footprint can add as much as. pf of capacitance to ground if the ground plane is not cleared from under the mounting pads. The low distortion pinout of the ADA4857 increases the separation distance between the inputs and the supply pins, which improves the second harmonics. In addition, the feedback pin reduces the distance between the output and the inverting input of the amplifier, which helps minimize the parasitic inductance and capacitance of the feedback path, reducing ringing and peaking. POWER SUPPLY BYPASSING Power supply bypassing for the ADA4857 was optimized for frequency response and distortion performance. Figure 49 shows the recommended values and location of the bypass capacitors. The. μf bypassing capacitors must be placed as close as possible to the supply pins. Power supply bypassing is critical for stability, frequency response, distortion, and PSR performance. The capacitor between the two supplies helps improve PSR and distortion performance. The μf electrolytic capacitors must be close to the. μf capacitors; however, it is not as critical. In some cases, additional paralleled capacitors can help improve frequency and transient response. GROUNDING Ground and power planes must be used where possible. Ground and power planes reduce the resistance and inductance of the power planes and ground returns. The returns for the input, output terminations, bypass capacitors, and RG must all be kept as close to the ADA4857 as possible. The output load ground and the bypass capacitor grounds must be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. The ADA4857 LFSCP packages feature an exposed paddle. For optimum electrical and thermal performance, solder this paddle to the ground plane or the power plane. For more information on high speed circuit design, see A Practical Guide to High-Speed Printed-Circuit- Board Layout at Rev. D Page 9 of

20 ADA4857-/ADA4857- OUTLINE DIMENSIONS.. SQ BSC 5 8 PIN INDEX AREA TOP VIEW.5.4. EXPOSED PAD 4 BOTTOM VIEW PIN INDICATOR (R.5) SEATING PLANE MAX. NOM COPLANARITY.8. REF COMPLIANT TO JEDEC STANDARDS MO-9-WEED FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure Lead Lead Frame Chip Scale Package [LFCSP] mm mm Body and.75 mm Package Height (CP-8-) Dimensions shown in millimeters 5. (.968) 4.8 (.89) -7--A 4. (.574).8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).5 (.5).5 (.). (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) 47-A Rev. D Page of

21 ADA4857-/ADA4857- PIN INDICATOR SQ.9.65 BSC PIN INDICATOR EXPOSED PAD.5. SQ.95 Figure 6. 6-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm 4 mm Body and.75 mm Package Height (CP-6-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity Branding ADA4857-YCPZ-R C to 5 C 8-Lead LFCSP CP-8-5 H5 ADA4857-YCPZ-RL C to 5 C 8-Lead LFCSP CP-8-5, H5 ADA4857-YCPZ-R7 C to 5 C 8-Lead LFCSP CP-8-,5 H5 ADA4857-YRZ C to 5 C 8-Lead SOIC_N R-8 98 ADA4857-YRZ-R7 C to 5 C 8-Lead SOIC_N R-8,5 ADA4857-YCPZ-R C to 5 C 6-Lead LFCSP CP-6-5 ADA4857-YCPZ-RL C to 5 C 6-Lead LFCSP CP-6-5, ADA4857-YCPZ-R7 C to 5 C 6-Lead LFCSP CP-6-,5 ADA4857-YCP-EBZ Evaluation Board Z = RoHS Compliant Part SEATING PLANE TOP VIEW MAX. NOM COPLANARITY.8. REF BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO--WGGC..5 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 98-A 8 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D74--/7(D) Rev. D Page of