AD8510/AD8512/AD8513. Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers FEATURES PIN CONFIGURATIONS

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1 Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers AD5/AD5/AD5 FEATURES Fast settling time: 5 ns to.% Low offset voltage: μv maximum Low TCVOS: μv/ C typical Low input bias current: 5 pa typical at VS = ±5 V Dual-supply operation: ±5 V to ±5 V Low noise: nv/ Hz typical at f = khz Low distortion:.5% No phase reversal Unity gain stable APPLICATIONS Instrumentation Multipole filters Precision current measurement Photodiode amplifiers Sensors Audio NULL IN +IN AD5 TOP VIEW (Not to Scale) 7 V 5 NC = NO CONNECT PIN CONFIGURATIONS NC V+ OUT NULL Figure. -Lead MSOP (RM Suffix) OUT A IN A +IN A V AD5 7 TOP VIEW (Not to Scale) V+ OUT B IN B +IN B Figure. -Lead MSOP (RM Suffix) OUT A IN A +IN A V+ +IN B 5 AD5 TOP VIEW (Not to Scale) IN B OUT B 7 OUT D IN D +IN D V +IN C 9 IN C OUT C Figure 5. -Lead SOIC_N (R Suffix) NULL AD5 NC IN 7 V+ +IN TOP VIEW (Not to Scale) OUT V 5 NULL NC = NO CONNECT Figure. -Lead SOIC_N (R Suffix) OUT A IN A +IN A AD5 TOP VIEW (Not to Scale) 7 V+ OUT B IN B V 5 +IN B Figure. -Lead SOIC_N (R Suffix) OUT A IN A +IN A V+ +IN B IN B OUT B AD5 TOP VIEW 5 (Not to Scale) OUT D IN D +IN D V +IN C 9 IN C OUT C 79- Figure. -Lead TSSOP (RU Suffix) 79- GENERAL DESCRIPTION The AD5/AD5/AD5 are single-, dual-, and quadprecision JFET amplifiers that feature low offset voltage, input bias current, input voltage noise, and input current noise. The combination of low offsets, low noise, and very low input bias currents makes these amplifiers especially suitable for high impedance sensor amplification and precise current measurements using shunts. The combination of dc precision, low noise, and fast settling time results in superior accuracy in medical instruments, electronic measurement, and automated test equipment. Unlike many competitive amplifiers, the AD5/ AD5/AD5 maintain their fast settling performance even with substantial capacitive loads. Unlike many older JFET amplifiers, the AD5/AD5/AD5 do not suffer from output phase reversal when input voltages exceed the maximum common-mode voltage range. Fast slew rate and great stability with capacitive loads make the AD5/AD5/AD5 a perfect fit for high performance filters. Low input bias currents, low offset, and low noise result in a wide dynamic range of photodiode amplifier circuits. Low noise and distortion, high output current, and excellent speed make the AD5/AD5/AD5 great choices for audio applications. The AD5/AD5 are both available in -lead narrow SOIC_N and -lead MSOP packages. MSOP-packaged parts are only available in tape and reel. The AD5 is available in -lead SOIC_N and TSSOP packages. The AD5/AD5/AD5 are specified over the C to +5 C extended industrial temperature range. Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD5/AD5/AD5 TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... Specifications... Electrical Characteristics... Absolute Maximum Ratings... ESD Caution... Typical Performance Characteristics... 7 General Application Information... Input Overvoltage Protection... REVISION HISTORY /7 Rev. G to Rev. H Changes to Crosstalk Section... Added Figure 5... /7 Rev. F to Rev. G Changes to Figure and Figure... Changes to Table and Table... Updated Outline Dimensions... 9 Changes to Ordering Guide... / Rev. E to Rev. F Changes to Figure... 9 Updated Outline Dimensions... 9 Changes to Ordering Guide... / Rev. D to Rev. E Changes to Format...Universal Changes to Specifications... Updated Outline Dimensions... 9 / Rev. C to Rev. D Added AD5 Model...Universal Changes to Specifications... Added Figure through Figure... Added Figure 55 and Figure Changes to Ordering Guide... 9/ Rev. B to Rev. C Changes to Ordering Guide... Updated Figure... Changes to Input Overvoltage Protection Section... Changes to Figure and Figure... Changes to Photodiode Circuits Section... Changes to Figure and Figure... Deleted Precision Current Monitoring Section... Updated Outline Dimensions... 5 Output Phase Reversal... Total Harmonic Distortion (THD) + Noise... Total Noise Including Source Resistors... Settling Time... Overload Recovery Time... Capacitive Load Drive... Open-Loop Gain and Phase Response... 5 Precision Rectifiers... I-V Conversion Applications... 7 Outline Dimensions... 9 Ordering Guide... / Rev. A to Rev. B Updated Figure 5... Updated Outline Dimensions... 5 / Rev. to Rev. A Added AD5 Model...Universal Added Pin Configurations... Changes to Specifications... Changes to Ordering Guide... Changes to TPC and TPC...5 Added TPC and TPC... Replaced TPC... Replaced TPC Changes to General Application Information Section... Changes to Figure 5... Changes to I-V Conversion Applications Section... Changes to Figure and Figure... Changes to Figure 7... Rev. H Page of

3 AD5/AD5/AD5 VS = ±5 V, VCM = V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (B Grade) VOS.. mv C < TA < +5 C. mv Offset Voltage (A Grade) VOS..9 mv C < TA < +5 C. mv Input Bias Current IB 75 pa C < TA < +5 C.7 na C < TA < +5 C 7.5 na Input Offset Current IOS 5 5 pa C < TA < +5 C. na C < TA < +5 C.5 na Input Capacitance Differential.5 pf Common Mode.5 pf Input Voltage Range. +.5 V Common-Mode Rejection Ratio CMRR VCM =. V to +.5 V db Large-Signal Voltage Gain AVO RL = kω, VO = V to + V 5 7 V/mV Offset Voltage Drift (B Grade) ΔVOS/ΔT.9 5 μv/ C Offset Voltage Drift (A Grade) ΔVOS/ΔT.7 μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω.. V Output Voltage Low VOL RL = kω, C < TA < +5 C.9.7 V Output Voltage High VOH RL = kω.9. V Output Voltage Low VOL RL = kω, C < TA < +5 C.9.5 V Output Voltage High VOH RL = Ω.7. V Output Voltage Low VOL RL = Ω, C < TA < +5 C.. V Output Current IOUT ± ±5 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±.5 V to ± V db Supply Current/Amplifier ISY AD5/AD5/AD5 VO = V.. ma AD5/AD5 C < TA < +5 C.5 ma AD5 C < TA < +5 C.75 ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω V/μs Gain Bandwidth Product GBP MHz Settling Time ts To.%, V to V step, G = +. μs Total Harmonic Distortion (THD) + Noise THD + N khz, G = +, RL = kω.5 % Phase Margin φm.5 Degrees NOISE PERFORMANCE Voltage Noise Density en f = Hz nv/ Hz f = Hz nv/ Hz f = khz. nv/ Hz f = khz 7. nv/ Hz Peak-to-Peak Voltage Noise en p-p. Hz to Hz bandwidth. 5. μv p-p AD5/AD5 only. Rev. H Page of

4 AD5/AD5/AD5 ELECTRICAL VS = ±5 V, VCM = V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (B Grade) VOS.. mv C < TA < +5 C. mv Offset Voltage (A Grade) VOS.. mv C < TA < +5 C. mv Input Bias Current IB 5 pa C < TA < +5 C.7 na C < TA < +5 C na Input Offset Current IOS 75 pa C < TA < +5 C. na C < TA < +5 C.5 na Input Capacitance Differential.5 pf Common Mode.5 pf Input Voltage Range.5 +. V Common-Mode Rejection Ratio CMRR VCM =.5 V to +.5 V db Large-Signal Voltage Gain AVO RL = kω, VCM = V, VO =.5 V to +.5 V 5 9 V/mV Offset Voltage Drift (B Grade) ΔVOS/ΔT. 5 μv/ C Offset Voltage Drift (A Grade) ΔVOS/ΔT.7 μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω V Output Voltage Low VOL RL = kω, C < TA < +5 C.9. V Output Voltage High VOH RL = kω V Output Voltage Low VOL RL = kω, C < TA < +5 C..5 V Output Voltage High VOH RL = Ω V RL = Ω, C < TA < +5 C +. V Output Voltage Low VOL RL = Ω.. V RL = Ω, C < TA < +5 C. V Output Current IOUT ±7 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±.5 V to ± V db Supply Current/Amplifier ISY AD5/AD5/AD5 VO = V..5 ma AD5/AD5 C < TA < +5 C. ma AD5 C < TA < +5 C. ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω V/μs Gain Bandwidth Product GBP MHz Settling Time ts To.%, V to V step, G = +.5 μs To.%, V to V step, G = +.9 μs Total Harmonic Distortion (THD) + Noise THD + N khz, G = +, RL = kω.5 % Phase Margin φm 5 Degrees Rev. H Page of

5 AD5/AD5/AD5 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Voltage Noise Density en f = Hz nv/ Hz f = Hz nv/ Hz f = khz. nv/ Hz f = khz 7. nv/ Hz Peak-to-Peak Voltage Noise en p-p. Hz to Hz bandwidth. 5. μv p-p AD5/AD5 only. Rev. H Page 5 of

6 AD5/AD5/AD5 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ± V Input Voltage ±VS Output Short-Circuit Duration to GND Observe derating curves Storage Temperature Range 5 C to +5 C Operating Temperature Range C to +5 C Junction Temperature Range 5 C to +5 C Lead Temperature (Soldering, sec) C Electrostatic Discharge V (Human Body Model) Table. Thermal Resistance Package Type θja θjc Unit -Lead MSOP (RM) 5 C/W -Lead SOIC_N (R) 5 C/W -Lead SOIC_N (R) C/W -Lead TSSOP (RU) 5 C/W θja is specified for worst-case conditions, that is, θja is specified for device soldered in circuit board for surface-mount packages. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. H Page of

7 TYPICAL PERFORMANCE CHARACTERISTICS NUMBER OF AMPLIFIERS T A = 5 C INPUT OFFSET VOLTAGE (mv) Figure 7. Input Offset Voltage Distribution 79-7 INPUT BIAS CURRENT (pa) k k k AD5/AD5/AD5, ±5V TEMPERATURE ( C) Figure. Input Bias Current vs. Temperature 79-5 B GRADE NUMBER OF AMPLIFIERS 5 5 INPUT OFFSET CURRENT (pa) ±5V ±5V 5 T C V OS (µv/ C) Figure. AD5/AD5 TCVOS Distribution TEMPERATURE ( C) Figure. Input Offset Current vs. Temperature 79-5 A GRADE 5 T A = 5 C NUMBER OF AMPLIFIERS T C V OS (µv/ C) 79-9 INPUT BIAS CURRENT (pa) SUPPLY VOLTAGE (V+ V ) 79- Figure 9. AD5/AD5 TCVOS Distribution Figure. Input Bias Current vs. Supply Voltage Rev. H Page 7 of

8 AD5/AD5/AD5 SUPPLY CURRENT PER AMPLIFIER (ma) T A = 5 C SUPPLY VOLTAGE (V+ V ) Figure. AD5 Supply Current per Amplifier vs. Supply Voltage 79- SUPPLY CURRENT (ma) T A = 5 C SUPPLY VOLTAGE (V+ V ) Figure. AD5 Supply Current vs. Supply Voltage 79- OUTPUT VOLTAGE (V) V OL V OH V OL V OH 5 LOAD CURRENT (ma) 7 Figure. AD5/AD5 Output Voltage vs. Load Current 79- GAIN (db) 7 5 k k R L =.5kΩ C SCOPE = pf Φ M = 5 5 M M 5M Figure 7. Open-Loop Gain and Phase vs. Frequency PHASE (Degrees) SUPPLY CURRENT PER AMPLIFIER (ma) ±5V ±5V TEMPERATURE ( C) Figure 5. AD5 Supply Current per Amplifier vs. Temperature 79-5 SUPPLY CURRENT (ma) ±5V ±5V TEMPERATURE ( C) Figure. AD5 Supply Current vs. Temperature 79- Rev. H Page of

9 AD5/AD5/AD5 7, ±5V 7 V IN = 5mV 5 CLOSED-LOOP GAIN (db) A V = A V = A V = OUTPUT IMPEDANCE (Ω) 5 9 A V = A V = A V = k k k M M 5M Figure 9. Closed-Loop Gain vs. Frequency 79-9 k k k M M M Figure. Output Impedance vs. Frequency 79- CMRR (db) k k k M M M Figure. CMRR vs. Frequency 79- VOLTAGE NOISE DENSITY (nv/ Hz) k k TO ±5V Figure. Voltage Noise Density vs. Frequency k 79-, ±5V PSRR (db) PSRR +PSRR VOLTAGE (µv/div) k k k M M M Figure. PSRR vs. Frequency 79- TIME (s/div) Figure.. Hz to Hz Input Voltage Noise 79- Rev. H Page 9 of

10 AD5/AD5/AD5 VOLTAGE NOISE DENSITY (nv Hz) TO ±5V Figure 5. Voltage Noise Density vs. Frequency 79-5 SMALL-SIGNAL OVERSHOOT (%) R L = kω +OS OS k k LOAD CAPACITANCE (pf) Figure. Small-Signal Overshoot vs. Load Capacitance 79- R L = kω C L = pf A V = 7 5 R L =.5kΩ C SCOPE = pf Φ M = VOLTAGE (5V/DIV) OPEN-LOOP GAIN (db) PHASE (Degrees) 5 TIME (µs/div) Figure. Large-Signal Transient Response 79-9 k k M M 5 5M Figure 9. Open-Loop Gain and Phase vs. Frequency 79-9 R L = kω C L = pf A V = VOLTAGE (5mV/DIV) CMRR (db) TIME (ns/div) Figure 7. Small-Signal Transient Response 79-7 k k k M M M Figure. CMRR vs. Frequency 79- Rev. H Page of

11 AD5/AD5/AD5 OUTPUT IMPEDANCE (Ω) V IN = 5mV A V = A V = VOLTAGE (5mV/DIV) R L = kω C L = pf A V = k A V = k k M M M Figure. Output Impedance vs. Frequency 79- TIME (ns/div) Figure. Small-Signal Transient Response 79-9 R L = kω VOLTAGE (µv/div) SMALL-SIGNAL OVERSHOOT (%) 7 5 +OS OS TIME (s/div) Figure.. Hz to Hz Input Voltage Noise 79- k k LOAD CAPACITANCE (pf) Figure 5. Small-Signal Overshoot vs. Load Capacitance 79-5 VOLTAGE (V/DIV) R L = kω C L = pf A V = NUMBER OF AMPLIFIERS V S = ±5V TIME (µs/div) Figure. Large-Signal Transient Response 79-5 T C V OS (µv/ C) Figure. AD5 TCVOS Distribution 79- Rev. H Page of

12 AD5/AD5/AD5 NUMBER OF AMPLIFIERS V S = ±5V 5 T C V OS (µv/ C) Figure 7. AD5 TCVOS Distribution 79-7 OUTPUT VOLTAGE (V) V OL V OH V OL V OH 5 7 LOAD CURRENT (ma) Figure 9. AD5 Output Voltage vs. Load Current 79-9 SUPPLY CURRENT PER AMPLIFIER (ma) T A = 5 C.5 SUPPLY VOLTAGE (V+ V ) Figure. AD5 Supply Current per Amplifier vs. Supply Voltage 79- SUPPLY CURRENT PER AMPLIFIER (ma)..5 ±5V. ±5V TEMPERATURE ( C) Figure. AD5 Supply Current per Amplifier vs. Temperature 79- Rev. H Page of

13 AD5/AD5/AD5 GENERAL APPLICATION INFORMATION INPUT OVERVOLTAGE PROTECTION The AD5/AD5/AD5 have internal protective circuitry that allows voltages as high as.7 V beyond the supplies to be applied at the input of either terminal without causing damage. For higher input voltages, a series resistor is necessary to limit the input current. The resistor value can be determined from the formula VIN VS 5 ma R S With a very low offset current of <.5 na up to 5 C, higher resistor values can be used in series with the inputs. A 5 kω resistor protects the inputs from voltages as high as 5 V beyond the supplies and adds less than μv to the offset. OUTPUT PHASE REVERSAL Phase reversal is a change of polarity in the transfer function of the amplifier. This can occur when the voltage applied at the input of an amplifier exceeds the maximum common-mode voltage. Phase reversal can cause permanent damage to the device and can result in system lockups. The AD5/AD5/AD5 do not exhibit phase reversal when input voltages are beyond the supplies. VOLTAGE (V/DIV) V IN TIME (µs/div) Figure. No Phase Reversal V OUT A V = R L = kω TOTAL HARMONIC DISTORTION (THD) + NOISE The AD5/AD5/AD5 have low THD and excellent gain linearity, making these amplifiers great choices for precision circuits with high closed-loop gain and for audio application circuits. Figure shows that the AD5/AD5/AD5 have approximately.5% of total distortion when configured in positive unity gain (the worst case) and driving a kω load DISTORTION (%).. R L = kω BW = khz. k k k Figure. THD + N vs. Frequency TOTAL NOISE INCLUDING SOURCE RESISTORS The low input current noise and input bias current of the AD5/AD5/AD5 make them the ideal amplifiers for circuits with substantial input source resistance. Input offset voltage increases by less than 5 nv per 5 Ω of source resistance at room temperature. The total noise density of the circuit is ntotal ( inrs ) ktrs e = e n + + where: en is the input voltage noise density of the parts. in is the input current noise density of the parts. RS is the source resistance at the noninverting terminal. k is Boltzmann s constant (. J/K). T is the ambient temperature in Kelvin (T = 7 + C). For RS <.9 kω, en dominates and entotal en. The current noise of the AD5/AD5/AD5 is so low that its total density does not become a significant term unless RS is greater than 5 MΩ, an impractical value for most applications. The total equivalent rms noise over a specific bandwidth is expressed as e ntotal = e ntotal BW where BW is the bandwidth in hertz. Note that the previous analysis is valid for frequencies larger than 5 Hz and assumes flat noise above khz. For lower frequencies, flicker noise (/f) must be considered Rev. H Page of

14 AD5/AD5/AD5 SETTLING TIME Settling time is the time it takes the output of the amplifier to reach and remain within a percentage of its final value after a pulse is applied at the input. The AD5/AD5/AD5 settle to within.% in less than 9 ns with a step of V to V in unity gain. This makes each of these parts an excellent choice as a buffer at the output of DACs whose settling time is typically less than μs. In addition to the fast settling time and fast slew rate, low offset voltage drift and input offset current maintain the full accuracy of -bit converters over the entire operating temperature range. OVERLOAD RECOVERY TIME Overload recovery, also known as overdrive recovery, is the time it takes the output of an amplifier to recover to its linear region from a saturated condition. This recovery time is particularly important in applications where the amplifier must amplify small signals in the presence of large transient voltages. Figure shows the positive overload recovery of the AD5/ AD5/AD5. The output recovers in approximately ns from a saturated condition. VOLTAGE OUTPUT INPUT V 5V mv V V IN = mv A V = R L = kω 79-5 VOLTAGE INPUT OUTPUT +5V V V mv TIME (µs/div) Figure. Negative Overload Recovery A V = R L = kω CAPACITIVE LOAD DRIVE The AD5/AD5/AD5 are unconditionally stable at all gains in inverting and noninverting configurations. Each device is capable of driving a capacitive load of up to pf without oscillation in unity gain using the worst-case configuration. However, as with most amplifiers, driving larger capacitive loads in a unity gain configuration may cause excessive overshoot and ringing, or even oscillation. A simple snubber network significantly reduces the amount of overshoot and ringing. The advantage of this configuration is that the output swing of the amplifier is not reduced, because RS is outside the feedback loop. mv V+ 7 AD5 R S V OUT 79-5 TIME (µs/div) Figure. Positive Overload Recovery V C S CL The negative overdrive recovery time shown in Figure is less than ns. Figure 5. Snubber Network Configuration In addition to the fast recovery time, the AD5/AD5/ AD5 show excellent symmetry of the positive and negative recovery times. This is an important feature for transient signal rectification because the output signal is kept equally undistorted throughout any given period. Rev. H Page of

15 AD5/AD5/AD5 Figure shows a scope plot of the output of the AD5/AD5/ AD5 in response to a mv pulse. The circuit is configured in positive unity gain (worst case) with a load experience of 5 pf. VOLTAGE (mv/div) C L = 5pF R L =kω TIME (µs/div) Figure. Capacitive Load Drive Without Snubber When the snubber circuit is used, the overshoot is reduced from 55% to less than % with the same load capacitance. Ringing is virtually eliminated, as shown in Figure 7. VOLTAGE (mv/div) R L = kω C L = 5pF R S = Ω C S = nf 79- OPEN-LOOP GAIN AND PHASE RESPONSE In addition to their impressive low noise, low offset voltage, and offset current, the AD5/AD5/AD5 have excellent loop gain and phase response even when driving large resistive and capacitive loads. Compared with Competitor A (see Figure 9) under the same conditions, with a.5 kω load at the output, the AD5/AD5/ AD5 have more than MHz of bandwidth and a phase margin of more than 5. Competitor A, on the other hand, has only.5 MHz of bandwidth and of phase margin under the same test conditions. Even with a nf capacitive load in parallel with the kω load at the output, the AD5/AD5/AD5 show much better response than Competitor A, whose phase margin is degraded to less than, indicating oscillation. GAIN (db) 7 5 k k R L =.5kΩ C L = pf 5 M M 5M Figure. Frequency Response of the AD5/AD5/AD PHASE (Degrees) 79- TIME (µs/div) Figure 7. Capacitive Load with Snubber Network Optimum values for RS and CS depend on the load capacitance and input stray capacitance and are determined empirically. Table 5 shows a few values that can be used as starting points. Table 5. Optimum Values for Capacitive Loads CLOAD RS (Ω) CS 5 pf nf nf 7 pf 5 nf pf 79- GAIN (db) 7 5 k k R L =.5kΩ C L = pf M M 5M Figure 9. Frequency Response of Competitor A PHASE (Degrees) 79- Rev. H Page 5 of

16 AD5/AD5/AD5 PRECISION RECTIFIERS Rectifying circuits are used in a multitude of applications. One of the most popular uses is in the design of regulated power supplies, where a rectifier circuit is used to convert an input sinusoid to a unipolar output voltage. However, there are some potential problems with amplifiers used in this manner. When the input voltage (VIN) is negative, the output is zero, and the magnitude of VIN is doubled at the inputs of the op amp. If this voltage exceeds the power supply voltage, it may permanently damage some amplifiers. In addition, the op amp must come out of saturation when VIN is negative. This delays the output signal because the amplifier requires time to enter its linear region. Although the AD5/AD5/AD5 have a very fast overdrive recovery time, which makes them great choices for the rectification of transient signals, the symmetry of the positive and negative recovery times is also important to keep the output signal undistorted. VOLTAGE (V/DIV) TIME (ms/div) Figure 5. Half-Wave Rectifier Signal (OUT A in Figure 5) 79- Figure 5 shows the test circuit of the rectifier. The first stage of the circuit is a half-wave rectifier. When the sine wave applied at the input is positive, the output follows the input response. During the negative cycle of the input, the output tries to swing negative to follow the input, but the power supply restrains it to zero. In a similar fashion, the second stage is a follower during the positive cycle of the sine wave and an inverter during the negative cycle. R kω V R kω VOLTAGE (V/DIV) TIME (ms/div) Figure 5. Full-Wave Rectifier Signal (OUT B in Figure 5) 79-7 V IN V p-p R kω / AD5 / AD5 5 7 OUT B (FULL WAVE) V OUT A (HALF WAVE) Figure 5. Half-Wave and Full-Wave Rectifiers 79-5 Rev. H Page of

17 AD5/AD5/AD5 I-V CONVERSION APPLICATIONS Photodiode Circuits Common applications for I-V conversion include photodiode circuits where the amplifier is used to convert a current emitted by a diode placed at the positive input terminal into an output voltage. The AD5/AD5/AD5 s low input bias current, wide bandwidth, and low noise make them each an excellent choice for various photodiode applications, including fax machines, fiber optic controls, motion sensors, and bar code readers. The circuit shown in Figure 5 uses a silicon diode with zero bias voltage. This is known as a photovoltaic mode; this configuration limits the overall noise and is suitable for instrumentation applications. Rd Ct Cf R V EE AD5 7 V CC Figure 5. Equivalent Preamplifier Photodiode Circuit A larger signal bandwidth can be attained at the expense of additional output noise. The total input capacitance (Ct) consists of the sum of the diode capacitance (typically pf to pf) and the amplifier s input capacitance ( pf), which includes external parasitic capacitance. Ct creates a pole in the frequency response that can lead to an unstable system. To ensure stability and optimize the bandwidth of the signal, a capacitor is placed in the feedback loop of the circuit shown in Figure 5. It creates a zero and yields a bandwidth whose corner frequency is /(π(rcf)). The value of R can be determined by the ratio V/ID where: V is the desired output voltage of the op amp. ID is the diode current. For example, if ID is μa and a V output voltage is desired, R should be kω. Rd (see Figure 5) is a junction resistance that drops typically by a factor of for every C increase in temperature. 79- A typical value for Rd is MΩ. Because Rd >> R, the circuit behavior is not impacted by the effect of the junction resistance. The maximum signal bandwidth is ft f MAX = πrct where ft is the unity gain frequency of the amplifier. Cf can be calculated by Cf = Ct πr ft where ft is the unity gain frequency of the op amp, and it achieves a phase margin, φm, of approximately 5. A higher phase margin can be obtained by increasing the value of Cf. Setting Cf to twice the previous value yields approximately φm = 5 and a maximal flat frequency response, but it reduces the maximum signal bandwidth by 5%. Using the previous parameters with a Cf pf, the signal bandwidth is approximately. MHz. Signal Transmission Applications One popular signal transmission method uses pulse-width modulation. High data rates may require a fast comparator rather than an op amp. However, the need for sharp, undistorted signals may favor using a linear amplifier. The AD5/AD5/AD5 make excellent voltage comparators. In addition to a high slew rate, the AD5/ AD5/AD5 have a very fast saturation recovery time. In the absence of feedback, the amplifiers are in open-loop mode (very high gain). In this mode of operation, they spend much of their time in saturation. The circuit shown in Figure 5 was used to compare two signals of different frequencies, namely a Hz sine wave and a khz triangular wave. Figure 55 shows a scope plot of the resulting output waveforms. A pull-up resistor (typically 5 kω) can be connected from the output to VCC if the output voltage needs to reach the positive rail. The trade-off is that power consumption is higher. V +5V 7 5V V V OUT Figure 5. Pulse-Width Modulator 79-9 Rev. H Page 7 of

18 AD5/AD5/AD5 VOLTAGE (5V/DIV) TIME (ms/div) 79-5 The AD5 single has two additional active terminals that are not present on the AD5 dual or AD5 quad parts. These pins are labeled null and are used for fine adjustment of the input offset voltage. Although the guaranteed maximum offset voltage at room temperature is μv and over the C to +5 C range is mv maximum, this offset voltage can be reduced by adding a potentiometer to the null pins as shown in Figure 5. With the kω potentiometer shown, the adjustment range is approximately ±.5 mv. The potentiometer parallels low value resistors in the drain circuit of the JFET differential input pair and allows unbalancing of the drain currents to change the offset voltage. If offset adjustment is not required, these pins should be left unconnected. Figure 55. Pulse-Width Modulation Crosstalk Crosstalk, also known as channel separation, is a measure of signal feedthrough from one channel to another on the same IC. The AD5/AD5 have a channel separation of better than 9 db for frequencies up to khz and of better than 5 db for frequencies up to MHz. Figure 57 shows the typical channel separation behavior between Amplifier A (driving amplifier) and each of the following: Amplifier B, Amplifier C, and Amplifier D. +V S V OUT kω V p-p 7 5 5kΩ 5kΩ V IN V S CROSSTALK = log V OUT V IN Figure 5. Crosstalk Test Circuit.kΩ 79-5 Caution should be used when adding adjusting potentiometers to any op amp with this capability for several reasons. First, there is gain from these nodes to the output; therefore, capacitive coupling from noisy traces to these nodes will inject noise into the signal path. Second, the temperature coefficient of the potentiometer will not match the temperature coefficient of the internal resistors, so the offset voltage drift with temperature will be slightly affected. Third, this provision is for adjusting the offset voltage of the op amp, not for adjusting the offset of the overall system. Although it is tempting to decrease the value of the potentiometer to attain more range, this will adversely affect the dc and ac parameters. Instead, increase the potentiometer to 5 kω to decrease the range if needed. INPUT + 5 AD5 V kω 7 V+ OUTPUT V OS TRIM RANGE IS TYPICALLY ±.5mV Figure 5. Optional Offset Nulling Circuit 79-5 CHANNEL SEPARATION (db) CH B CH D CH C k k k M M Figure 57. Channel Separation 79-5 Rev. H Page of

19 AD5/AD5/AD5 OUTLINE DIMENSIONS 5. (.9). (.9) (.57). (.97).5 (.9). (.) COPLANARITY. SEATING PLANE 5.7 (.5) BSC. (.) 5. (.).75 (.).5 (.5).5 (.). (.).5 (.9).7 (.7).5 (.9).5 (.99).7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 59. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) 5 7-A PIN BSC BSC. MAX SEATING PLANE..9 COPLANARITY. COMPLIANT TO JEDEC STANDARDS MO-5-AB- Figure. -Lead Thin Shrink Small Outline Package [TSSOP] (RU-) Dimensions shown in millimeters (.575). (.9).75 (.5).55 (.) 7. (.) 5. (.) PIN.5 BSC.. COPLANARITY.. MAX SEATING PLANE.. COMPLIANT TO JEDEC STANDARDS MO-7-AA Figure. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters....5 (.9). (.9) COPLANARITY..7 (.5) BSC.5 (.). (.).75 (.9).5 (.5) SEATING PLANE.5 (.9).7 (.7).5 (.97).5 (.9).7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS--AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) 5 -A Rev. H Page 9 of

20 AD5/AD5/AD5 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD5ARM-REEL C to +5 C -Lead MSOP RM- B7A AD5ARM-R C to +5 C -Lead MSOP RM- B7A AD5ARMZ-REEL C to +5 C -Lead MSOP RM- B7A# AD5ARMZ-R C to +5 C -Lead MSOP RM- B7A# AD5AR C to +5 C -Lead SOIC_N R- AD5AR-REEL C to +5 C -Lead SOIC_N R- AD5AR-REEL7 C to +5 C -Lead SOIC_N R- AD5ARZ C to +5 C -Lead SOIC_N R- AD5ARZ-REEL C to +5 C -Lead SOIC_N R- AD5ARZ-REEL7 C to +5 C -Lead SOIC_N R- AD5BR C to +5 C -Lead SOIC_N R- AD5BR-REEL C to +5 C -Lead SOIC_N R- AD5BR-REEL7 C to +5 C -Lead SOIC_N R- AD5BRZ C to +5 C -Lead SOIC_N R- AD5BRZ-REEL C to +5 C -Lead SOIC_N R- AD5BRZ-REEL7 C to +5 C -Lead SOIC_N R- AD5ARM-REEL C to +5 C -Lead MSOP RM- BA AD5ARM-R C to +5 C -Lead MSOP RM- BA AD5ARMZ-REEL C to +5 C -Lead MSOP RM- BA# AD5ARMZ-R C to +5 C -Lead MSOP RM- BA# AD5AR C to +5 C -Lead SOIC_N R- AD5AR-REEL C to +5 C -Lead SOIC_N R- AD5AR-REEL7 C to +5 C -Lead SOIC_N R- AD5ARZ C to +5 C -Lead SOIC_N R- AD5ARZ-REEL C to +5 C -Lead SOIC_N R- AD5ARZ-REEL7 C to +5 C -Lead SOIC_N R- AD5BR C to +5 C -Lead SOIC_N R- AD5BR-REEL C to +5 C -Lead SOIC_N R- AD5BR-REEL7 C to +5 C -Lead SOIC_N R- AD5BRZ C to +5 C -Lead SOIC_N R- AD5BRZ-REEL C to +5 C -Lead SOIC_N R- AD5BRZ-REEL7 C to +5 C -Lead SOIC_N R- AD5AR C to +5 C -Lead SOIC_N R- AD5AR-REEL C to +5 C -Lead SOIC_N R- AD5AR-REEL7 C to +5 C -Lead SOIC_N R- AD5ARZ C to +5 C -Lead SOIC_N R- AD5ARZ-REEL C to +5 C -Lead SOIC_N R- AD5ARZ-REEL7 C to +5 C -Lead SOIC_N R- AD5ARU C to +5 C -Lead TSSOP RU- AD5ARU-REEL C to +5 C -Lead TSSOP RU- AD5ARUZ C to +5 C -Lead TSSOP RU- AD5ARUZ-REEL C to +5 C -Lead TSSOP RU- Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D79--/7(H) Rev. H Page of