Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers AD8605/AD8606/AD8608

Transcription

1 Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers AD865/AD866/AD868 FEATURES Low offset voltage: 65 μv maximum Low input bias currents: pa maximum Low noise: 8 nv/ Hz Wide bandwidth: V/mV High open-loop gain: db Unity gain stable Single-supply operation:.7 V to 5.5 V 5-ball WLCSP for single (AD865), and 8-ball WLCSP for dual (AD866) GENERAL DESCRIPTION The AD865, AD866, and AD868 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim trimming technique, which achieves superior precision without laser trimming. The combination of low offsets, low noise, very low input bias currents, and high speed makes these amplifiers useful in a wide variety of applications. Filters, integrators, photodiode amplifiers, and high impedance sensors all benefit from the combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion. Applications for these amplifiers include optical control loops, portable and loop-powered instrumentation, and audio amplification for portable devices. The AD865, AD866, and AD868 are specified over the extended industrial temperature range ( 4 C to +5 C). The AD865 single is available in 5-lead SOT-3 and 5-ball WLCSP packages. The AD866 dual is available in an 8-lead MSOP, an 8-ball WLSCP, and a narrow SOIC surface-mounted package. The AD868 quad is available in a 4-lead TSSOP package and a narrow 4-lead SOIC package. The 5-ball and 8-ball WLCSP offer the smallest available footprint for any surface-mounted operational amplifier. The WLCSP, SOT-3, MSOP, and TSSOP versions are available in tape-and-reel only. Protected by U.S. Patent No. 5,969,657; other patents pending. APPLICATIONS Photodiode amplification Battery-powered instrumentation Multipole filters Sensors Barcode scanners Audio FUNCTIONAL BLOCK DIAGRAMS OUT 5 V+ AD865 V TOP VIEW (Not to Scale) +IN 3 4 IN 73- Figure. 5-Lead SOT-3 (RJ Suffix) TOP VIEW (BUMP SIDE DOWN) OUT V+ 5 V +IN 3 IN AD865 ONLY Figure 3. 5-Ball WLCSP (CB Suffix) OUT A IN A +IN A V 4 8 AD866 TOP VIEW (Not to Scale) V+ OUT B IN B +IN B Figure 5. 8-Lead MSOP (RM Suffix) 8-Lead SOIC_N (R Suffix) 73-3 BALL A CORNER OUTA V+ OUTB A A A3 INA B INB B3 +INA V +INB C C C3 AD866 TOP VIEW (BALL SIDE DOWN) Figure. 8-Ball WLCSP (CB Suffix) OUT A IN A +IN A 3 V+ 4 +IN B 5 IN B 6 OUT B 7 AD868 TOP VIEW (Not to Scale) 4 OUT D 3 IN D +IN D V +IN C 9 IN C 8 OUT C Figure 4. 4-Lead SOIC_N (R Suffix) OUT A IN A +IN A V+ +IN B IN B OUT B 4 AD868 TOP VIEW (Not to Scale) OUT D IN D +IN D V +IN C IN C OUT C Figure 6. 4-Lead TSSOP (RU Suffix) 73- Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD865/AD866/AD868 TABLE OF CONTENTS Features... General Description... Applications... Functional Block Diagrams... Revision History... 5 V Electrical Specifications V Electrical Specifications... 5 Absolute Maximum Ratings... 7 ESD Caution... 7 Typical Performance Characteristics... 8 Applications Information... 4 Output Phase Reversal... 4 Maximum Power Dissipation... 4 Input Overvoltage Protection... 4 REVISION HISTORY /7 Rev. F to Rev. G Changes to Figure... Updated Outline Dimensions... 8/7 Rev. E to Rev. F Added 8-Ball WLCSP Package... Universal Changes to Features... Changes to Table... 3 Changes to Table... 5 Changes to Table Updated Outline Dimensions...9 Changes to Ordering Guide... /6 Rev. D to Rev. E Changes to Table... 3 Changes to Table... 5 Changes to Table Changes to Figure Caption... 8 Changes to Figure 6 and Figure 7 Captions... Changes to Figure 33 Caption... Changes to Figure Updated Outline Dimensions...9 Changes to Ordering Guide... 5/4 Rev. C to Rev. D Updated Format... Universal Edit to Light Sensitivity Section...6 Updated Outline Dimensions...9 Changes to Ordering Guide... THD + Noise... 4 Total Noise Including Source Resistors... 5 Channel Separation... 5 Capacitive Load Drive... 5 Light Sensitivity... 6 WLCSP Assembly Considerations... 6 I-V Conversion Applications... 7 Photodiode Preamplifier Applications... 7 Audio and PDA Applications... 7 Instrumentation Amplifiers... 8 DAC Conversion... 8 Outline Dimensions... 9 Ordering Guide... 7/3 Rev. B to Rev. C Changes to Features... Change to General Description... Addition to Functional Block Diagrams... Addition to Absolute Maximum Ratings... 4 Addition to Ordering Guide... 4 Change to Equation in Maximum Power Dissipation Section... Added Light Sensitivity Section... Added New Figure 8; Renumbered Subsequently... 3 Added New MicroCSP Assembly Considerations Section... 3 Changes to Figure Change to Equation in Photodiode Preamplifier Applications Section... 3 Changes to Figure... 4 Change to Equation in D/A Conversion Section... 4 Updated Outline Dimensions /3 Rev. A to Rev. B Changes to Functional Block Diagram... Changes to Absolute Maximum Ratings... 4 Changes to Ordering Guide... 4 Changes to Figure Updated Outline Dimensions... 5 / Rev. to Rev. A Change to Electrical Characteristics... Changes to Absolute Maximum Ratings... 4 Changes to Ordering Guide... 4 Change to TPC Updated Outline Dimensions / Revision : Initial Version Rev. G Page of 4

3 AD865/AD866/AD868 5 V ELECTRICAL SPECIFICATIONS VS = 5 V, VCM = VS/, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS AD865/AD866 (Except WLCSP) VS = 3.5 V, VCM = 3 V 65 μv AD868 VS = 3.5 V, VCM =.7 V 75 μv AD865/AD866/AD868 VS = 5 V, VCM = V to 5 V 8 3 μv 4 C < TA < +5 C 75 μv Input Bias Current IB. pa AD865/AD866 4 C < TA < +85 C 5 pa AD865/AD866 4 C < TA < +5 C 5 pa AD868 4 C < TA < +85 C pa AD868 4 C < TA < +5 C 3 pa Input Offset Current IOS..5 pa 4 C < TA < +85 C pa 4 C < TA < +5 C 75 pa Input Voltage Range 5 V Common-Mode Rejection Ratio CMRR VCM = V to 5 V 85 db 4 C < TA < +5 C 75 9 db Large Signal Voltage Gain AVO RL = kω, VO =.5 V to 4.5 V 3 V/mV Offset Voltage Drift AD865/AD866 ΔVOS/ΔT 4.5 μv/ C AD868 ΔVOS/ΔT.5 6. μv/ C INPUT CAPACITANCE Common-Mode Input Capacitance 8.8 pf Differential Input Capacitance.6 pf OUTPUT CHARACTERISTICS Output Voltage High VOH IL = ma V IL = ma V 4 C < TA < +5 C 4.6 V Output Voltage Low VOL IL = ma 4 mv IL= ma 7 mv 4 C < TA < +5 C 9 mv Output Current IOUT ±8 ma Closed-Loop Output Impedance ZOUT f = MHz, AV = Ω POWER SUPPLY Power Supply Rejection Ratio PSRR AD865/AD866 VS =.7 V to 5.5 V 8 95 db AD865/AD866 WLCSP VS =.7 V to 5.5 V 75 9 db AD868 VS =.7 V to 5.5 V 77 9 db 4 C < TA < +5 C 7 9 db Supply Current/Amplifier ISY VO = V. ma 4 C < TA < +5 C.4 ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω 5 V/μs Settling Time ts To.%, V to V step < μs Gain Bandwidth Product GBP MHz Phase Margin ΦM 65 Degrees Rev. G Page 3 of 4

4 AD865/AD866/AD868 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Peak-to-Peak Noise en p-p f =. Hz to Hz μv p-p Voltage Noise Density en f = khz 8 nv/ Hz en f = khz 6.5 nv/ Hz Current Noise Density in f = khz. pa/ Hz Rev. G Page 4 of 4

5 AD865/AD866/AD868.7 V ELECTRICAL SPECIFICATIONS VS =.7 V, VCM = VS/, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS AD865/AD866 (Except WLCSP) VS = 3.5 V, VCM = 3 V 65 μv AD868 VS = 3.5 V, VCM =.7 V 75 μv AD865/AD866/AD868 VS =.7 V, VCM = V to.7 V 8 3 μv 4 C < TA < +5 C 75 μv Input Bias Current IB. pa AD865/AD866 4 C < TA < +85 C 5 pa AD865/AD866 4 C < TA < +5 C 5 pa AD868 4 C < TA < +85 C pa AD868 4 C < TA < +5 C 3 pa Input Offset Current IOS..5 pa 4 C < TA < +85 C pa 4 C < TA < +5 C 75 pa Input Voltage Range.7 V Common-Mode Rejection Ratio CMRR VCM = V to.7 V 8 95 db 4 C < TA < +5 C 7 85 db Large Signal Voltage Gain AVO RL = kω, VO =.5 V to. V 35 V/mV Offset Voltage Drift AD865/AD866 ΔVOS/ΔT 4.5 μv/ C AD868 ΔVOS/ΔT.5 6. μv/ C INPUT CAPACITANCE Common-Mode Input Capacitance 8.8 pf Differential Input Capacitance.6 pf OUTPUT CHARACTERISTICS Output Voltage High VOH IL = ma.6.66 V 4 C < TA < +5 C.6 V Output Voltage Low VOL IL = ma 5 4 mv 4 C < TA < +5 C 5 mv Output Current IOUT ±3 ma Closed-Loop Output Impedance ZOUT f = MHz, AV =. Ω POWER SUPPLY Power Supply Rejection Ratio PSRR AD865/AD866 VS =.7 V to 5.5 V 8 95 db AD865/AD866 WLCSP VS =.7 V to 5.5 V 75 9 db AD868 VS =.7 V to 5.5 V 77 9 db 4 C < TA < +5 C 7 9 db Supply Current/Amplifier ISY VO = V.5.4 ma 4 C < TA < +5 C.5 ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω 5 V/μs Settling Time ts To.%, V to V step <.5 μs Gain Bandwidth Product GBP 9 MHz Phase Margin ΦM 5 Degrees Rev. G Page 5 of 4

6 AD865/AD866/AD868 Parameter Symbol Conditions Min Typ Max Unit NOISE PERFORMANCE Peak-to-Peak Noise en p-p f =. Hz to Hz μv p-p Voltage Noise Density en f = khz 8 nv/ Hz en f = khz 6.5 nv/ Hz Current Noise Density in f = khz. pa/ Hz Rev. G Page 6 of 4

7 AD865/AD866/AD868 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 6 V Input Voltage GND to VS Differential Input Voltage 6 V Output Short-Circuit Duration to GND Observe Derating Curves Storage Temperature Range All Packages 65 C to +5 C Operating Temperature Range All Packages 4 C to +5 C Junction Temperature Range All Packages 65 C to +5 C Lead Temperature (Soldering, 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Type θja θjc Unit 5-Ball WLCSP (CB) 7 C/W 5-Lead SOT-3 (RJ) 4 9 C/W 8-Ball WLCSP (CB) 5 C/W 8-Lead MSOP (RM) 6 44 C/W 8-Lead SOIC_N (R) C/W 4-Lead SOIC_N (R) 5 36 C/W 4-Lead TSSOP (RU) 48 3 C/W θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. ESD CAUTION Rev. G Page 7 of 4

8 AD865/AD866/AD868 TYPICAL PERFORMANCE CHARACTERISTICS NUMBER OF AMPLIFIERS V S = 5V T A = 5 C V CM = V TO 5V OFFSET VOLTAGE (µv) Figure 7. Input Offset Voltage Distribution V OS (mv) V CM (V) Figure. Input Offset Voltage vs. Common-Mode Voltage ( Units, 5 Wafer Lots, Including Process Skews) 73- NUMBER OF AMPLIFIERS V S = 5V T A = 4 C TO +5 C V CM =.5V TCVOS (µv/ C) Figure 8. AD868 Input Offset Voltage Drift Distribution INPUT BIAS CURRENT (pa) AD865/AD866 6 AD TEMPERATURE ( C) Figure. Input Bias Current vs. Temperature 73- NUMBER OF AMPLIFIERS V S = 5V T A = 4 C TO +5 C V CM =.5V TCVOS (µv/ C) OUTPUT SATURATION VOLTAGE (mv) k V S = 5V T A = 5 C SOURCE SINK.... LOAD CURRENT (ma) 73- Figure 9. AD865/AD866 Input Offset Voltage Drift Distribution Figure. Output Saturation Voltage vs. Load Current Rev. G Page 8 of 4

9 AD865/AD866/AD OUTPUT VOLTAGE (V) V ma LOAD 4.95 V S = 5V V ma LOAD TEMPERATURE ( C) Figure 3. Output Voltage Swing vs. Temperature 73-3 OUTPUT SWING (V p-p) V S = 5V V IN = 4.9V p-p T A = 5 C R L = kω A V = k k k M M FREQUENCY (Hz) Figure 6. Closed-Loop Output Voltage Swing V S = 5V V ma LOAD 9. 8 OUTPUT VOLTAGE (V).5. OUTPUT IMPEDANCE (Ω) A V = A V = A V = TEMPERATURE ( C) V ma LOAD 73-4 k k k M M M FREQUENCY (Hz) 73-7 Figure 4. Output Voltage Swing vs. Temperature Figure 7. Output Impedance vs. Frequency 8 6 R L = kω C L = pf Φ M = GAIN (db) PHASE (Degrees) CMRR (db) k 8 5 k M M M FREQUENCY (Hz) Figure 5. Open-Loop Gain and Phase vs. Frequency k k k M M FREQUENCY (Hz) Figure 8. Common-Mode Rejection Ratio (CMRR) vs. Frequency 73-8 Rev. G Page 9 of 4

10 AD865/AD866/AD868 4 V S = 5V..9 PSRR (db) SUPPLY CURRENT/AMPLIFIER (ma) k k k M FREQUENCY (Hz) Figure 9. PSRR vs. Frequency 73-9 M SUPPLY VOLTAGE (V) Figure. Supply Current/Amplifier vs. Supply Voltage 73- SMALL SIGNAL OVERSHOOT (%) V S = 5V R L = T A = 5 C A V = +OS OS VOLTAGE NOISE (µv/div) V S = 5V 5 k CAPACITANCE (pf) 73- TIME (s/div) 73-3 Figure. Small Signal Overshoot vs. Load Capacitance Figure 3.. Hz to Hz Input Voltage Noise SUPPLY CURRENT/AMPLIFIER (ma)..5 V S =.7V. V S = 5V TEMPERATURE ( C) 73- VOLTAGE (5mV/DIV) R L = kω C L = pf A V = TIME (ns/div) 73-4 Figure. Supply Current/Amplifier vs. Temperature Figure 4. Small Signal Transient Response Rev. G Page of 4

11 AD865/AD866/AD868 VOLTAGE (V/DIV) R L = kω C L = pf A V = TIME (4ns/DIV) 73-5 VOLTAGE NOISE DENSITY (nv/ Hz) FREQUENCY (khz) 73-8 Figure 5. Large Signal Transient Response Figure 8. Voltage Noise Density vs. Frequency V OUT V V V IN.5V 5mV TIME (4ns/DIV) R L = kω A V = V IN = 5mV 73-6 VOLTAGE NOISE DENSITY (nv/ Hz) FREQUENCY (khz) 73-9 Figure 6. Positive Overload Recovery Figure 9. Voltage Noise Density vs. Frequency V.5V 5mV V R L = kω A V = V IN = 5mV TIME (µs/div) 73-7 VOLTAGE NOISE DENSITY (nv/ Hz) FREQUENCY (Hz) 73-3 Figure 7. Negative Overload Recovery Figure 3. Voltage Noise Density vs. Frequency Rev. G Page of 4

12 AD865/AD866/AD868 NUMBER OF AMPLIFIERS V S =.7V T A = 5 C V CM = V TO.7V OFFSET VOLTAGE (µv) Figure 3. Input Offset Voltage Distribution OUTPUT VOLTAGE (V).68 V S =.7V V ma LOAD TEMPERATURE ( C) Figure 34. Output Voltage Swing vs. Temperature INPUT OFFSET VOLTAGE (µv) 3 V S =.7V T A = 5 C OUTPUT SATURATION VOLTAGE (mv) COMMON-MODE VOLTAGE (V) Figure 3. Input Offset Voltage vs. Common-Mode Voltage ( Units, 5 Wafer Lots, Including Process Skews) k V S =.7V T A = 5 C SOURCE SINK.... LOAD CURRENT (ma) Figure 33. Output Saturation Voltage vs. Load Current GAIN (db) OUTPUT VOLTAGE (V) V S =.7V 5 V ma LOAD TEMPERATURE ( C) Figure 35. Output Voltage Swing vs. Temperature V S = ±.35V R L = kω C L = pf Φ M = k k M M M FREQUENCY (Hz) Figure 36. Open-Loop Gain and Phase vs. Frequency PHASE (Degrees) Rev. G Page of 4

13 AD865/AD866/AD V S =.7V.5 OUTPUT SWING (V p-p)..5. V S =.7V V IN =.6V p-p T A = 5 C R L = kω A V = VOLTAGE NOISE (µv/div).5 k k k FREQUENCY (Hz) Figure 37. Closed-Loop Output Voltage Swing vs. Frequency M M TIME (s/div) Figure 4.. Hz to Hz Input Voltage Noise V S = ±.35V V S =.35V R L = kω C L = pf A V = OUTPUT IMPEDANCE (Ω) A V = A V = A V = VOLTAGE (5mV/DIV) k k k M M FREQUENCY (Hz) Figure 38. Output Impedance vs. Frequency M TIME (ns/div) Figure 4. Small Signal Transient Response 73-4 SMALL SIGNAL OVERSHOOT (%) V S =.7V T A = 5 C A V = OS +OS VOLTAGE (V/DIV) V S =.35V R L = kω C L = pf A V = k CAPACITANCE (pf) Figure 39. Small Signal Overshoot vs. Load Capacitance TIME (4ns/DIV) Figure 4. Large Signal Transient Response 73-4 Rev. G Page 3 of 4

14 AD865/AD866/AD868 APPLICATIONS INFORMATION OUTPUT PHASE REVERSAL Phase reversal is defined as a change in polarity at the output of the amplifier when a voltage that exceeds the maximum input common-mode voltage drives the input. Phase reversal can cause permanent damage to the amplifier; it can also cause system lockups in feedback loops. The AD865 does not exhibit phase reversal even for inputs exceeding the supply voltage by more than V. MAXIMUM POWER DISSIPATION Power dissipated in an IC causes the die temperature to increase, which can affect the behavior of the IC and the application circuit performance. The absolute maximum junction temperature of the AD865/ AD866/AD868 is 5 C. Exceeding this temperature could damage or destroy the device. The maximum power dissipation of the amplifier is calculated according to TJ TA PDISS = θ JA where: TJ is the junction temperature. TA is the ambient temperature. θja is the junction-to-ambient thermal resistance. Figure 44 compares the maximum power dissipation with temperature for the various AD86x family packages. INPUT OVERVOLTAGE PROTECTION The AD865 has internal protective circuitry. However, if the voltage applied at either input exceeds the supplies by more than.5 V, external resistors should be placed in series with the inputs. The resistor values can be determined by VIN VS 5mA R + Ω S The remarkable low input offset current of the AD865 (< pa) allows the use of larger value resistors. With a kω resistor at the input, the output voltage has less than nv of error voltage. A kω resistor has less than 3 nv/ Hz of thermal noise at room temperature. THD + NOISE Total harmonic distortion is the ratio of the input signal in V rms to the total harmonics in V rms throughout the spectrum. Harmonic distortion adds errors to precision measurements and adds unpleasant sonic artifacts to audio systems. The AD865 has a low total harmonic distortion. Figure 45 shows that the AD865 has less than.5% or 86 db of THD + N over the entire audio frequency range. The AD865 is configured in positive unity gain, which is the worst case, and with a load of kω. Rev. G Page 4 of 4 VOLTAGE (V/DIV) V IN = 6V p-p A V = R L = kω V IN V OUT TIME (4µs/DIV) Figure 43. No Phase Reversal SOIC TSSOP-4... SOIC MSOP-8.5 WLCSP LEAD SOT AMBIENT TEMPERATURE ( C) Figure 44. Maximum Power Dissipation vs. Ambient Temperature. V SY = ±.5V A V = B W = khz POWER DISSIPATION (W) THD + NOISE (%)... k k k FREQUENCY (Hz) Figure 45. THD + Noise vs. Frequency

15 AD865/AD866/AD868 TOTAL NOISE INCLUDING SOURCE RESISTORS The low input current noise and input bias current of the AD865 make it the ideal amplifier for circuits with substantial input source resistance, such as photodiodes. Input offset voltage increases by less than.5 nv per kω of source resistance at room temperature and increases to nv at 85 C. The total noise density of the circuit is ( inrs ) ktrs e 4 n, TOTAL = en + + where: en is the input voltage noise density of the AD865. in is the input current noise density of the AD865. RS is the source resistance at the noninverting terminal. k is Boltzmann s constant (.38 3 J/K). T is the ambient temperature in Kelvin (T = 73 + C). For example, with RS = kω, the total voltage noise density is roughly 5 nv/ Hz. For RS < 3.9 kω, en dominates and en, TOTAL en. The current noise of the AD865 is so low that its total density does not become a significant term unless RS is greater than 6 MΩ. The total equivalent rms noise over a specific bandwidth is expressed as E = ( e ) BW n n, TOTAL where BW is the bandwidth in hertz. Note that the previous analysis is valid for frequencies greater than Hz and assumes relatively flat noise, above khz. For lower frequencies, flicker noise (/f) must be considered. CHANNEL SEPARATION Channel separation, or inverse crosstalk, is a measure of the signal feed from one amplifier (channel) to another on the same IC. The AD866 has a channel separation of greater than 6 db up to frequencies of MHz, allowing the two amplifiers to amplify ac signals independently in most applications. CAPACITIVE LOAD DRIVE The AD86x can drive large capacitive loads without oscillation. Figure 47 shows the output of the AD866 in response to a mv input signal. In this case, the amplifier is configured in positive unity gain, worst case for stability, while driving a pf load at its output. Driving larger capacitive loads in unity gain can require the use of additional circuitry. A snubber network, shown in Figure 48, helps reduce the signal overshoot to a minimum and maintain stability. Although this circuit does not recover the loss of bandwidth induced by large capacitive loads, it greatly reduces the overshoot and ringing. This method does not reduce the maximum output swing of the amplifier. CHANNEL SEPARATION (db) k k k M M M FREQUENCY (Hz) Figure 46. Channel Separation vs. Frequency VOLTAGE (mv/div) A V = R L = kω C L = pf TIME (µs/div) Figure 47. AD866 Capacitive Load Drive Without Snubber mv V IN 3 4 V+ AD865 8 V R S C S Figure 48. Snubber Network Configuration R L C L Rev. G Page 5 of 4

16 B B AD865/AD866/AD868 Figure 49 shows a scope of the output at the snubber circuit. The overshoot is reduced from over 7% to less than 5%, and the ringing is eliminated by the snubber. Optimum values for RS and CS are determined experimentally. VOLTAGE (mv/div) A V = R L = kω R S = 9Ω C L = pf C S = 7pF TIME (µs/div) Figure 49. Capacitive Load Drive with Snubber Table 5 summarizes a few optimum values for capacitive loads. Table 5. CL (pf) RS (Ω) CS (pf) An alternate technique is to insert a series resistor inside the feedback loop at the output of the amplifier. Typically, the value of this resistor is approximately Ω. This method also reduces overshoot and ringing but causes a reduction in the maximum output swing. LIGHT SENSITIVITY The AD865ACB (WLCSP package option) is essentially a silicon die with additional postfabrication dielectric and intermetallic processing designed to contact solder bumps on the active side of the chip. With this package type, the die is exposed to ambient light and is subject to photoelectric effects. Light sensitivity analysis of the AD865ACB mounted on standard PCB material reveals that only the input bias current (IB) parameter is impacted when the package is illuminated directly by high intensity light. No degradation in electrical performance is observed due to illumination by low intensity (. mw/cm ) ambient light. Figure 5 shows that I B increases with increasing wavelength and intensity of incident light; IB can reach levels as high as 45 pa at a light intensity of 3 mw/cm and a wavelength of 85 nm. The light intensities shown in Figure 5 are not normal for most applications, that is, even though direct sunlight can have intensities of 5 mw/cm, office ambient light can be as low as. mw/cm INPUT BIAS CURRENT (pa) mw/cm 3mW/cm mw/cm WAVELENGTH (nm) Figure 5. AD865ACB Input Bias Current Response to Direct Illumination of Varying Intensity and Wavelength When the WLCSP package is assembled on the board with the bump side of the die facing the PCB, reflected light from the PCB surface is incident on active silicon circuit areas and results in the increased IB. No performance degradation occurs due to illumination of the backside (substrate) of the AD865ACB. The AD865ACB is particularly sensitive to incident light with wavelengths in the near infrared range (NIR, 7 nm to nm). Photons in this waveband have a longer wavelength and lower energy than photons in the visible (4 nm to 7 nm) and near ultraviolet (NUV, nm to 4 nm) bands; therefore, they can penetrate more deeply into the active silicon. Incident light with wavelengths greater than nm has no photo-electric effect on the AD865ACB because silicon is transparent to wavelengths in this range. The spectral content of conventional light sources varies. Sunlight has a broad spectral range, with peak intensity in the visible band that falls off in the NUV and NIR bands; fluorescent lamps have significant peaks in the visible but not the NUV or NIR bands. Efforts have been made at a product level to reduce the effect of ambient light; the under bump metal (UBM) has been designed to shield the sensitive circuit areas on the active side (bump side) of the die. However, if an application encounters any light sensitivity with the AD865ACB, shielding the bump side of the WLCSP package with opaque material should eliminate this effect. Shielding can be accomplished using materials such as silica-filled liquid epoxies that are used in flip-chip underfill techniques. WLCSP ASSEMBLY CONSIDERATIONS For detailed information on the WLCSP PCB assembly and reliability, see Application Note AN-67, MicroCSP Wafer Level Chip Scale Package Rev. G Page 6 of 4

17 AD865/AD866/AD868 I-V CONVERSION APPLICATIONS PHOTODIODE PREAMPLIFIER APPLICATIONS The low offset voltage and input current of the AD865 make it an excellent choice for photodiode applications. In addition, the low voltage and current noise make the amplifier ideal for application circuits with high sensitivity. PHOTODIODE R D I D C D 5pF V OS C F pf R F MΩ AD865 Figure 5. Equivalent Circuit for Photodiode Preamp V OUT The input bias current of the amplifier contributes an error term that is proportional to the value of RF. The offset voltage causes a dark current induced by the shunt resistance of the diode RD. These error terms are combined at the output of the amplifier. The error voltage is written as R + F E O = VOS + R D R F Typically, RF is smaller than RD, thus RF/RD can be ignored. I B V At room temperature, the AD865 has an input bias current of. pa and an offset voltage of μv. Typical values of RD are in the range of GΩ. For the circuit shown in Figure 5, the output error voltage is approximately μv at room temperature, increasing to about mv at 85 C. The maximum achievable signal bandwidth is f MAX f t = π R C F T where ft is the unity gain frequency of the amplifier. AUDIO AND PDA APPLICATIONS The low distortion and wide dynamic range of the AD86x make it a great choice for audio and PDA applications, including microphone amplification and line output buffering. Figure 5 shows a typical application circuit for headphone/ line-out amplification. R and R are used to bias the input voltage at half the supply, which maximizes the signal bandwidth range. C and C are used to ac couple the input signal. C and R form a high-pass filter whose corner frequency is /πrc. The high output current of the AD866 allows it to drive heavy resistive loads. The circuit in Figure 5 is tested to drive a 6 Ω headphone. The THD + N is maintained at approximately 6 db throughout the audio range. C µf V 5mV R kω R kω 3 8 / AD866 4 C3 µf R3 kω R4 Ω HEADPHONES 5V 5V C µf V 5mV kω kω / AD C4 µf R6 Ω R5 kω 73-5 Figure 5. Single-Supply Headphone/Speaker Amplifier Rev. G Page 7 of 4

18 AD865/AD866/AD868 INSTRUMENTATION AMPLIFIERS The low offset voltage and low noise of the AD865 make it an ideal amplifier for instrumentation applications. Difference amplifiers are widely used in high accuracy circuits to improve the common-mode rejection ratio. Figure 53 shows a simple difference amplifier. Figure 54 shows the commonmode rejection for a unity gain configuration and for a gain of. Making (R4/R3) = (R/R) and choosing.% tolerance yields a CMRR of 74 db and minimizes the gain error at the output. CMRR (db) V V R kω R4 R = R3 R R V OUT = (V V) R V SY = ±.5V R3 kω 5V AD865 R kω R4 kω Figure 53. Difference Amplifier, AV = A V = A V = V OUT k k k M M FREQUENCY (Hz) Figure 54. Difference Amplifier CMRR vs. Frequency DAC CONVERSION The low input bias current and offset voltage of the AD865 make it an excellent choice for buffering the output of a current output DAC. Figure 55 shows a typical implementation of the AD865 at the output of a -bit DAC. The DAC843 output current is converted to a voltage by the feedback resistor. The equivalent resistance at the output of the DAC varies with the input code, as does the output capacitance V REF R R R R R R V OS C F R F V+ AD865 Figure 55. Simplified Circuit of the DAC843 with AD865 Output Buffer To optimize the performance of the DAC, insert a capacitor in the feedback loop of the AD865 to compensate the amplifier for the pole introduced by the output capacitance of the DAC. Typical values for CF range from pf to 3 pf; it can be adjusted for the best frequency response. The total error at the output of the op amp can be computed by E O R = + F VOS Req where Req is the equivalent resistance seen at the output of the DAC. As previously mentioned, Req is code dependent and varies with the input. A typical value for Req is 5 kω. Choosing a feedback resistor of kω yields an error of less than μv. Figure 56 shows the implementation of a dual-stage buffer at the output of a DAC. The first stage is used as a buffer. Capacitor C with Req creates a low-pass filter, and thus, provides phase lead to compensate for frequency response. The second stage of the AD866 is used to provide voltage gain at the output of the buffer. Grounding the positive input terminals in both stages reduces errors due to the common-mode output voltage. Choosing R, R, and R3 to match within.% yields a CMRR of 74 db and maintains minimum gain error in the circuit. V IN R P 5V R CS C 33pF V DD R FB OUT VREF / AD7545 AGND DB V AD866 / AD866 R4 5kΩ% Figure 56. Bipolar Operation R kω R3 kω R kω V OUT Rev. G Page 8 of 4

19 AD865/AD866/AD868 OUTLINE DIMENSIONS REF SEATING PLANE BALL IDENTIFIER A B. C TOP VIEW (BALL SIDE DOWN) BOTTOM VIEW (BALL SIDE UP) Figure Ball Wafer Level Chip Scale Package [WLCSP] (CB-5) Dimensions shown in millimeters. 867-A.9 BSC BSC.8 BSC 3 PIN.95 BSC BSC.5 MAX MAX SEATING PLANE..8 COMPLIANT TO JEDEC STANDARDS MO-78-AA Figure Lead Small Outline Transistor Package [SOT-3] (RJ-5) Dimensions shown in millimeters PIN.65 BSC.38. COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. G Page 9 of 4

20 AD865/AD866/AD (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).35 (.53).5 (.).3 (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 6. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 47-A SEATING PLANE 3 BALL IDENTIFIER A B.5 BALL PITCH C TOP VIEW (BALL SIDE DOWN) Figure 6. 8-Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-) Dimensions shown in millimeters BOTTOM VIEW (BALL SIDE UP) 976-B 8.75 (.3445) 8.55 (.3366) 4. (.575) 3.8 (.496) (.44) 5.8 (.83).5 (.98). (.39) COPLANARITY..7 (.5) BSC.5 (.).3 (.).75 (.689).35 (.53) SEATING PLANE 8.5 (.98).7 (.67).5 (.97).5 (.98).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 6. 4-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-4) Dimensions shown in millimeters and (inches) 666-A Rev. G Page of 4

21 AD865/AD866/AD BSC PIN BSC.3.9. MAX SEATING PLANE..9 COPLANARITY. COMPLIANT TO JEDEC STANDARDS MO-53-AB- Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD865ACB-REEL 4 C to +5 C 5-Ball WLCSP CB-5 B3A AD865ACB-REEL7 4 C to +5 C 5-Ball WLCSP CB-5 B3A AD865ART-R 4 C to +5 C 5-Lead SOT-3 RJ-5 B3A AD865ART-REEL 4 C to +5 C 5-Lead SOT-3 RJ-5 B3A AD865ART-REEL7 4 C to +5 C 5-Lead SOT-3 RJ-5 B3A AD865ARTZ-R 4 C to +5 C 5-Lead SOT-3 RJ-5 B3A# AD865ARTZ-REEL 4 C to +5 C 5-Lead SOT-3 RJ-5 B3A# AD865ARTZ-REEL7 4 C to +5 C 5-Lead SOT-3 RJ-5 B3A# AD866ARM-R 4 C to +5 C 8-Lead MSOP RM-8 B6A AD866ARM-REEL 4 C to +5 C 8-Lead MSOP RM-8 B6A AD866ARMZ-R 4 C to +5 C 8-Lead MSOP RM-8 B6A# AD866ARMZ-REEL 4 C to +5 C 8-Lead MSOP RM-8 B6A# AD866AR 4 C to +5 C 8-Lead SOIC_N R-8 AD866AR-REEL 4 C to +5 C 8-Lead SOIC_N R-8 AD866AR-REEL7 4 C to +5 C 8-Lead SOIC_N R-8 AD866ARZ 4 C to +5 C 8-Lead SOIC_N R-8 AD866ARZ-REEL 4 C to +5 C 8-Lead SOIC_N R-8 AD866ARZ-REEL7 4 C to +5 C 8-Lead SOIC_N R-8 AD866ACBZ-REEL 4 C to +5 C 8-Ball WLCSP CB-8- B6A# AD866ACBZ-REEL7 4 C to +5 C 8-Ball WLCSP CB-8- B6A# AD868AR 4 C to +5 C 4-Lead SOIC_N R-4 AD868AR-REEL 4 C to +5 C 4-Lead SOIC_N R-4 AD868AR-REEL7 4 C to +5 C 4-Lead SOIC_N R-4 AD868ARZ 4 C to +5 C 4-Lead SOIC_N R-4 AD868ARZ-REEL 4 C to +5 C 4-Lead SOIC_N R-4 AD868ARZ-REEL7 4 C to +5 C 4-Lead SOIC_N R-4 AD868ARU 4 C to +5 C 4-Lead TSSOP RU-4 AD868ARU-REEL 4 C to +5 C 4-Lead TSSOP RU-4 AD868ARUZ 4 C to +5 C 4-Lead TSSOP RU-4 AD868ARUZ-REEL 4 C to +5 C 4-Lead TSSOP RU-4 Z = RoHS Compliant Part, # denotes RoHS compliant (except for CB-5). Product may be top or bottom marked. Rev. G Page of 4

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24 AD865/AD866/AD868 NOTES 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D73--/7(G) Rev. G Page 4 of 4