Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers AD8610/AD8620

Transcription

1 Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers AD8/AD8 FEATURES Low noise: nv/ Hz Low offset voltage: μv maximum Low input bias current: pa maximum Fast settling: ns to.% Low distortion Unity gain stable No phase reversal Dual-supply operation: ±5 V to ±3 V APPLICATIONS Photodiode amplifiers ATE Instrumentation Sensors and controls High performance filters Fast precision integrators High performance audio GENERAL DESCRIPTION The AD8/AD8 are very high precision JFET input amplifiers featuring ultralow offset voltage and drift, very low input voltage and current noise, very low input bias current, and wide bandwidth. Unlike many JFET amplifiers, the AD8/AD8 input bias current is low over the entire operating temperature range. The AD8/AD8 are stable with capacitive loads of over pf in noninverting unity gain; much larger capacitive loads can be driven easily at higher noise gains. The AD8/ AD8 swing to within. V of the supplies even with a kω load, maximizing dynamic range even with limited supply voltages. Outputs slew at 5 V/μs in either inverting or noninverting gain configurations, and settle to.% accuracy in less than ns. Combined with high input impedance, great precision, and very high output drive, the AD8/AD8 are ideal amplifiers for driving high performance ADC inputs and buffering DAC converter outputs. PIN CONFIGURATIONS NULL IN AD8 +IN 3 TOP VIEW V (Not to Scale) 8 NC 7 V+ OUT 5 NULL NC = NO CONNECT Figure. 8-Lead MSOP and 8-Lead SOIC_N OUTA INA AD8 +INA 3 TOP VIEW V (Not to Scale) 8 V+ 7 OUTB INB 5 +INB Figure. 8-Lead SOIC_N Applications for the AD8/AD8 include electronic instruments; ATE amplification, buffering, and integrator circuits; CAT/MRI/ultrasound medical instrumentation; instrumentation quality photodiode amplification; fast precision filters (including PLL filters); and high quality audio. The AD8/AD8 are fully specified over the extended industrial temperature range ( C to +5 C). The AD8 is available in the narrow 8-lead SOIC and the tiny 8-lead MSOP surface-mount packages. The AD8 is available in the narrow 8-lead SOIC package. The 8-lead MSOP packaged devices are avail-able only in tape and reel Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD8/AD8 TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... Specifications... 3 Electrical Specifications... Absolute Maximum Ratings...5 ESD Caution...5 Typical Performance Characteristics... Theory of Operation... 3 Functional Description... 3 Outline Dimensions... Ordering Guide... REVISION HISTORY 5/8 Rev. E to Rev. F Changes to Figure Changes to Functional Description Section... 3 Changes to THD Readings vs. Common-Mode Voltage Section... 7 Changes to Output Current Capability Section... 8 Changes to Figure and Figure Changes to Figure 8... Replaced Second-Order Low-Pass Filter Section... / Rev. D to Rev. E Updated Format... Universal Changes to Table... 3 Changes to Table... Changes to Outline Dimensions... Changes to Ordering Guide... / Rev. C to Rev. D. Changes to Specifications... Changes to Ordering Guide... Updated Outline Dimensions... 7 / Rev. B to Rev. C. Updated Ordering Guide... Edits to Figure 5... Updated Outline Dimensions... 5/ Rev. A to Rev. B Addition of Part Number AD8... Universal Addition of 8-Lead SOIC (R-8 Suffix) Drawing... Changes to General Description... Additions to Specifications... Change to Electrical Specifications... 3 Additions to Ordering Guide... Replace TPC Add Channel Separation Test Circuit Figure... 9 Add Channel Separation Graph... 9 Changes to Figure... 5 Addition of High-Speed, Low Noise Differential Driver section... Addition of Figure 3... Rev. F Page of

3 AD8/AD8 VS = ±5. V, VCM = V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (AD8B) VOS 5 μv C < TA < +5 C 8 μv Offset Voltage (AD8B) VOS 5 5 μv C < TA < +5 C 8 3 μv Offset Voltage (AD8A/AD8A) VOS 85 5 μv 5 C < TA < 5 C 9 35 μv C < TA < +5 C 5 85 μv Input Bias Current IB + + pa C < TA < +85 C pa C < TA < +5 C na Input Offset Current IOS + + pa C < TA < +85 C pa C < TA < +5 C pa Input Voltage Range +3 V Common-Mode Rejection Ratio CMRR VCM =.5 V to +.5 V 9 95 db Large Signal Voltage Gain AVO RL = kω, VO = 3 V to +3 V 8 V/mV Offset Voltage Drift (AD8B) ΔVOS/ΔT C < TA < +5 C.5 μv/ C Offset Voltage Drift (AD8B) ΔVOS/ΔT C < TA < +5 C.5.5 μv/ C Offset Voltage Drift (AD8A/AD8A) ΔVOS/ΔT C < TA < +5 C μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω, C < TA < +5 C 3.8 V Output Voltage Low VOL RL = kω, C < TA < +5 C 3.8 V Output Current IOUT VOUT > ± V ±3 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±5 V to ±3 V db Supply Current per Amplifier ISY VO = V.5 3. ma C < TA < +5 C ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω 5 V/μs Gain Bandwidth Product GBP 5 MHz Settling Time ts AV = +, V step, to.% 35 ns NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz.8 μv p-p Voltage Noise Density en f = khz nv/ Hz Current Noise Density in f = khz 5 fa/ Hz Input Capacitance CIN Differential Mode 8 pf Common Mode 5 pf Channel Separation CS f = khz 37 db f = 3 khz db Rev. F Page 3 of

4 AD8/AD8 ELECTRICAL VS = ±3 V, VCM = V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (AD8B) VOS 5 μv C < TA < +5 C 8 μv Offset Voltage (AD8B) VOS 5 5 μv C < TA < +5 C 8 3 μv Offset Voltage (AD8A/AD8A) VOS 85 5 μv 5 C < TA < 5 C 9 35 μv C < TA < +5 C 5 85 μv Input Bias Current IB +3 + pa C < TA < +85 C pa C < TA < +5 C na Input Offset Current IOS pa C < TA < +85 C pa C < TA < +5 C pa Input Voltage Range V Common-Mode Rejection Ratio CMRR VCM = V to + V 9 db Large Signal Voltage Gain AVO RL = kω, VO = V to + V V/mV Offset Voltage Drift (AD8B) ΔVOS/ΔT C < TA < +5 C.5 μv/ C Offset Voltage Drift (AD8B) ΔVOS/ΔT C < TA < +5 C.5.5 μv/ C Offset Voltage Drift (AD8A/AD8A) ΔVOS/ΔT C < TA < +5 C μv/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω, C < TA < +5 C V Output Voltage Low VOL RL = kω, C < TA < +5 C.8.75 V Output Current IOUT VOUT > V ±5 ma Short-Circuit Current ISC ±5 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±5 V to ±3 V db Supply Current per Amplifier ISY VO = V ma C < TA < +5 C 3.5. ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω V/μs Gain Bandwidth Product GBP 5 MHz Settling Time ts AV = +, V step, to.% ns NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz.8 μv p-p Voltage Noise Density en f = khz nv/ Hz Current Noise Density in f = khz 5 fa/ Hz Input Capacitance CIN Differential Mode 8 pf Common Mode 5 pf Channel Separation CS f = khz 37 db f = 3 khz db Rev. F Page of

5 AD8/AD8 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage 7.3 V Input Voltage VS to VS+ Differential Input Voltage ±Supply voltage Output Short-Circuit Duration to GND Indefinite Storage Temperature Range 5 C to +5 C Operating Temperature Range C to +5 C Junction Temperature Range 5 C to +5 C Lead Temperature (Soldering, sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table. Thermal Resistance Package Type θja θjc Unit 8-Lead MSOP (RM) 9 C/W 8-Lead SOIC (R) 58 3 C/W θja is specified for worst-case conditions, that is, θja is specified for a device soldered in circuit board for surface-mount packages. ESD CAUTION Rev. F Page 5 of

6 AD8/AD8 TYPICAL PERFORMANCE CHARACTERISTICS NUMBER OF AMPLIFIERS INPUT OFFSET VOLTAGE (µv) Figure 3. Input Offset Voltage 73-3 INPUT OFFSET VOLTAGE (µv) Figure. Input Offset Voltage vs. Temperature at ±5 V (3 Amplifiers) 73- OR ±3V INPUT OFFSET VOLTAGE (µv) NUMBER OF AMPLIFIERS T C V OS (µv/ C) 73-7 Figure. Input Offset Voltage vs. Temperature at ±3 V (3 Amplifiers) Figure 7. Input Offset Voltage Drift NUMBER OF AMPLIFIERS 8 INPUT BIAS CURRENT (pa) INPUT OFFSET VOLTAGE (µv) COMMON-MODE VOLTAGE (V) 73-8 Figure 5. Input Offset Voltage Figure 8. Input Bias Current vs. Common-Mode Voltage Rev. F Page of

7 AD8/AD8 SUPPLY CURRENT (ma) SUPPLY VOLTAGE (±V) 73-9 OUTPUT VOLTAGE TO SUPPLY RAIL (V) k k k M M M RESISTANCE LOAD (Ω) 73- Figure 9. Supply Current vs. Supply Voltage Figure. Output Voltage to Supply Rail vs. Resistance Load SUPPLY CURRENT (ma) OUTPUT VOLTAGE HIGH (V) R L = Figure. Supply Current vs. Temperature Figure 3. Output Voltage High vs. Temperature R L = SUPPLY CURRENT (ma) OUTPUT VOLTAGE LOW (V) Figure. Supply Current vs. Temperature Figure. Output Voltage Low vs. Temperature Rev. F Page 7 of

8 AD8/AD8 OUTPUT VOLTAGE HIGH (V) R L = CLOSED-LOOP GAIN (db) G = + G = + G = + C L = pf k k k M M M 73-8 FREQUENCY (Hz) Figure 5. Output Voltage High vs. Temperature Figure 8. Closed-Loop Gain vs. Frequency OUTPUT VOLTAGE LOW (V) R L = A VO (V/mV) 8 V O = ±V R L = Figure. Output Voltage Low vs. Temperature Figure 9. AVO vs. Temperature 9 GAIN AND PHASE (db AND DEGREES) 8 AD8 C L = pf khz khz khz MHz MHz 5MHz FREQUENCY 73-7 A VO (V/mV) V O = ±3V R L = 73- Figure 7. Open-Loop Gain and Phase vs. Frequency Figure. AVO vs. Temperature Rev. F Page 8 of

9 AD8/AD8 PSRR (db) 8 PSRR +PSRR CMRR (db) 8 k k k M M M FREQUENCY (Hz) Figure. PSRR vs. Frequency 73- k k k M M M FREQUENCY (Hz) Figure. CMRR vs. Frequency 73- V IN = 3mV p-p A V = R L = PSRR (db) 8 PSRR +PSRR VOLTAGE (3mV/DIV) V CH = 5V/DIV V IN V OUT k k k M M M FREQUENCY (Hz) Figure. PSRR vs. Frequency 73- V TIME (µs/div) Figure 5. Positive Overvoltage Recovery 73-5 V IN = 3mV p-p A V = R L = C L = pf PSRR (db) 9 8 VOLTAGE (3mV/DIV) V V IN V OUT V CH = 5V/DIV TIME (µs/div) 73- Figure 3. PSRR vs. Temperature Figure. Negative Overvoltage Recovery Rev. F Page 9 of

10 AD8/AD8 PEAK-TO-PEAK VOLTAGE NOISE (µv/div) TIME (s/div) V IN p-p =.8µV 73-7 Z OUT (Ω) k GAIN = + GAIN = + GAIN = + k k M M M FREQUENCY (Hz) 73-3 Figure 7.. Hz to Hz Input Voltage Noise Figure 3. ZOUT vs. Frequency 3 VOLTAGE NOISE DENSITY (nv/ Hz) I B (pa) k k k FREQUENCY (Hz) 73-8 M Figure 8. Input Voltage Noise Density vs. Frequency Figure 3. Input Bias Current vs. Temperature Z OUT (Ω) GAIN = + GAIN = + GAIN = + SMALL SIGNAL OVERSHOOT (%) V IN = mv p-p +OS OS k k k M FREQUENCY (Hz) M M k k CAPACITANCE (pf) 73-3 Figure 9. ZOUT vs. Frequency Figure 3. Small Signal Overshoot vs. Load Capacitance Rev. F Page of

11 AD8/AD8 SMALL SIGNAL OVERSHOOT (%) V IN = mv +OS k k CAPACITANCE (pf) OS TIME (ns/div) V IN p-p = V A V = + C L = pf 73-3 Figure 33. Small Signal Overshoot vs. Load Capacitance Figure 3. +Slew Rate at G = + V IN = ±V A V = + FREQ =.5kHz V IN V OUT 73-3 TIME (µs/div) Figure 3. No Phase Reversal V IN p-p = V A V = + C L = pf V IN p-p = V A V = + C L = pf TIME (ns/div) Figure 37. Slew Rate at G = + V IN p-p = V A V = C L = pf TIME (µs/div) Figure 35. Large Signal Response at G = + TIME (µs/div) Figure 38. Large Signal Response at G = Rev. F Page of

12 AD8/AD8 V IN p-p = V A V = SR = 55V/µs C L = pf V IN p-p = V A V = SR = 5V/µs C L = pf 73- TIME (ns/div) TIME (ns/div) Figure 39. +Slew Rate at G = Figure. Slew Rate at G = Rev. F Page of

13 AD8/AD8 THEORY OF OPERATION CS (db) = log (V OUT / V IN ) +3V 3 U + V+ V 5 R kω 3V V IN V p-p R kω R3 kω V V+ U R kω 7 Figure. Channel Separation Test Circuit FUNCTIONAL DESCRIPTION The AD8/AD8 are manufactured on the Analog Devices, Inc., XFCB (extra fast complementary bipolar) process. XFCB is fully dielectrically isolated (DI) and used in conjunction with N-channel JFET technology and thin film resistors (that can be trimmed) to create the JFET input amplifier. Dielectrically isolated NPN and PNP transistors fabricated on XFCB have an fτ > 3 GHz. Low TC thin film resistors enable very accurate offset voltage and offset voltage temperature coefficient trimming. These process breakthroughs allow Analog Devices IC designers to create an amplifier with faster slew rate and more than 5% higher bandwidth at half of the current consumed by its closest competition. The AD8/AD8 are unconditionally stable in all gains, even with capacitive loads well in excess of nf. The AD8B grade achieves less than μv of offset and μv/ C of offset drift, numbers usually associated with very high precision bipolar input amplifiers. The AD8 is offered in the tiny 8-lead MSOP as well as narrow 8-lead SOIC surface-mount packages and is fully specified with supply voltages from ±5. V to ±3 V. The very wide specified temperature range, up to 5 C, guarantees superior operation in systems with little or no active cooling. The unique input architecture of the AD8/AD8 features extremely low input bias currents and very low input offset voltage. Low power consumption minimizes the die temperature and maintains the very low input bias current. Unlike many competitive JFET amplifiers, the AD8/AD8 input bias currents are low even at elevated temperatures. Typical bias currents are less than pa at 85 C. The gate current of a JFET doubles every C, resulting in a similar increase in input bias current over temperature. Give special care to the PC board layout to minimize leakage currents between PCB traces. Improper layout and board handling generates a leakage current that exceeds the bias current of the AD8/AD CS (db) Power Consumption FREQUENCY (khz) Figure. AD8 Channel Separation Graph A major advantage of the AD8/AD8 in new designs is the power saving capability. Lower power consumption of the AD8/AD8 makes them much more attractive for portable instrumentation and for high density systems, simplifying thermal management, and reducing power-supply performance requirements. Compare the power consumption of the AD8 vs. the OPA7 in Figure 3. SUPPLY CURRENT (ma) OPA7 AD Figure 3. Supply Current vs. Temperature Rev. F Page 3 of

14 AD8/AD8 Driving Large Capacitive Loads The AD8/AD8 have excellent capacitive load driving capability and can safely drive up to nf when operating with a ±5. V supply. Figure and Figure 5 compare the AD8/ AD8 against the OPA7 in the noninverting gain configuration driving a kω resistor and, pf capacitor placed in parallel on its output, with a square wave input set to a frequency of khz. The AD8/AD8 have much less ringing than the OPA7 with heavy capacitive loads. +5V 3 7 V IN = 5mV 5V µf kω kω Figure. Capacitive Load Drive Test Circuit 73- VOLTAGE (mv/div) R L = C L =,pf VOLTAGE (5mV/DIV) R L = C L = µf TIME (µs/div) Figure 7. OPA7 Capacitive Load Drive, AV = + TIME (µs/div) Figure. OPA7 Driving CL =, pf VOLTAGE (mv/div) R L = C L =,pf VOLTAGE (5mV/DIV) R L = C L = µf TIME (µs/div) Figure 8. AD8/AD8 Capacitive Load Drive, AV = + TIME (µs/div) Figure 5. AD8/AD8 Driving CL =, pf The AD8/AD8 can drive much larger capacitances without any external compensation. Although the AD8/ AD8 are stable with very large capacitive loads, remember that this capacitive loading limits the bandwidth of the amplifier. Heavy capacitive loads also increase the amount of overshoot and ringing at the output. Figure 7 and Figure 8 show the AD8/AD8 and the OPA7 in a noninverting gain of + driving μf of capacitance load. The ringing on the OPA7 is much larger in magnitude and continues times longer than the AD8/AD8. Rev. F Page of

15 AD8/AD8 Slew Rate (Unity Gain Inverting vs. Noninverting) Amplifiers generally have a faster slew rate in an inverting unity gain configuration due to the absence of the differential input capacitance. Figure 9 through Figure 5 show the performance of the AD8/AD8 configured in a unity gain of compared to the OPA7. The AD8/AD8 slew rate is more symmetrical, and both the positive and negative transitions are much cleaner than in the OPA7. SR = 5V/µs G= SR = 5V/µs G= TIME (ns/div) Figure 5. Slew Rate of AD8/AD8 in Unity Gain of G= 73-5 TIME (ns/div) Figure 9. +Slew Rate of AD8/AD8 in Unity Gain of 73-9 SR = 5V/µs G= 73-5 SR =.V/µs TIME (ns/div) Figure 5. +Slew Rate of OPA7 in Unity Gain of 73-5 TIME (ns/div) Figure 5. Slew Rate of OPA7 in Unity Gain of The AD8/AD8 have a very fast slew rate of V/μs even when configured in a noninverting gain of +. This is the toughest condition to impose on any amplifier because the input commonmode capacitance of the amplifier generally makes its SR appear worse. The slew rate of an amplifier varies according to the voltage difference between its two inputs. To observe the maximum SR, a voltage difference of about V between the inputs must be ensured. This is required for virtually any JFET op amp so that one side of the op amp input circuit is completely off, thus maximizing the current available to charge and discharge the internal compensation capacitance. Lower differential drive voltages produce lower slew rate readings. A JFET input op amp with a slew rate of V/μs at unity gain with VIN = V may slew at V/μs if it is operated at a gain of + with VIN = mv. Rev. F Page 5 of

16 AD8/AD8 The slew rate of the AD8/AD8 is double that of the OPA7 when configured in a unity gain of + (see Figure 53 and Figure 5). SR = 85V/µs G= + TIME (ns/div) Figure 53. +Slew Rate of AD8/AD8 in Unity Gain of + SR = 3V/µs G= + TIME (ns/div) Figure 5. +Slew Rate of OPA7 in Unity Gain of + The slew rate of an amplifier determines the maximum frequency at which it can respond to a large signal input. This frequency (known as full power bandwidth or FPBW) can be calculated for a given distortion (for example, %) from the equation SR FPBW = π ( ) V PEAK CH =.8V p-p Input Overvoltage Protection When the input of an amplifier is driven below VEE or above VCC by more than one VBE, large currents flow from the substrate through the negative supply (V ) or the positive supply (V+), respectively, to the input pins and can destroy the device. If the input source can deliver larger currents than the maximum forward current of the diode (>5 ma), a series resistor can be added to protect the inputs. With its very low input bias and offset current, a large series resistor can be placed in front of the AD8/AD8 inputs to limit current to below damaging levels. Series resistance of kω generates less than 5 μv of offset. This kω allows input voltages more than 5 V beyond either power supply. Thermal noise generated by the resistor adds 7.5 nv/ Hz to the noise of the AD8/AD8. For the AD8/ AD8, differential voltages equal to the supply voltage do not cause any problems (see Figure 55). In this context, note that the high breakdown voltage of the input FETs eliminates the need to include clamp diodes between the inputs of the amplifier, a practice that is mandatory on many precision op amps. Unfortunately, clamp diodes greatly interfere with many application circuits, such as precision rectifiers and comparators. The AD8/ AD8 are free from these limitations. V V 3 +3V 7 AD8 3V Figure 5. Unity Gain Follower No Phase Reversal Many amplifiers misbehave when one or both of the inputs are forced beyond the input common-mode voltage range. Phase reversal is typified by the transfer function of the amplifier, effectively reversing its transfer polarity. In some cases, this can cause lockup and even equipment damage in servo systems and can cause permanent damage or no recoverable parameter shifts to the amplifier itself. Many amplifiers feature compensation circuitry to combat these effects, but some are only effective for the inverting input. The AD8/AD8 are designed to prevent phase reversal when one or both inputs are forced beyond their input common-mode voltage range V V IN VOLTAGE (V/DIV) V CH = 9.V p-p V OUT TIME (ns/div) Figure 55. AD8 FPBW Rev. F Page of TIME (µs/div) Figure 57. No Phase Reversal 73-57

17 AD8/AD8 THD Readings vs. Common-Mode Voltage Total harmonic distortion of the AD8/AD8 is well below.% with any load down to Ω. The AD8 outperforms the OPA7 for distortion, especially at frequencies above khz.. V IN = 5V rms BW = 8kHz Settling Time The AD8/AD8 have a very fast settling time, even to a very tight error band, as can be seen from Figure. The AD8/ AD8 are configured in an inverting gain of + with kω input and feedback resistors. The output is monitored with a, MΩ,. pf scope probe..k.k. THD + N (%). OPA7 AD8 SETTLING TIME (ns) 8. k k 8k FREQUENCY (Hz) Figure 58. AD8 vs. OPA7 THD + VCM = V. R L = Ω ERROR BAND (%) Figure. AD8/AD8 Settling Time vs. Error Band.k 73-.k THD + N (%). V rms V rms V rms SETTLING TIME (ns) 8. k k k FREQUENCY (Hz) Figure 59. THD + Noise vs. Frequency Noise vs. Common-Mode Voltage The AD8/AD8 noise density varies only % over the input range, as shown in Table 5. Table 5. Noise vs. Common-Mode Voltage VCM at f = khz (V) Noise Reading (nv/ Hz) OPA7... ERROR BAND (%) Figure. OPA7 Settling Time vs. Error Band 73- Rev. F Page 7 of

18 AD8/AD8 The AD8/AD8 maintain this fast settling time when loaded with large capacitive loads, as shown in Figure. SETTLING TIME (µs) SETTLING TIME (µs) ERROR BAND = ±.% 5 5 C L (pf) Figure. AD8/AD8 Settling Time vs. Load Capacitance ERROR BAND = ±.% 5 5 C L (pf) Figure 3. OPA7 Settling Time vs. Load Capacitance Output Current Capability The AD8/AD8 can drive very heavy loads due to its high output current. It is capable of sourcing or sinking 5 ma at ± V output. The short-circuit current is quite high and the part is capable of sinking about 95 ma and sourcing over ma while operating with supplies of ±3 V. Figure and Figure 5 compare the output voltage vs. load current of AD8/ AD8 and OPA DELTA FROM RESPECTIVE RAIL (V) DELTA FROM RESPECTIVE RAIL (V) V EE V CC LOAD CURRENT (A) Figure. AD8/AD8 Dropout from ±3 V vs. Load Current V CC V EE LOAD CURRENT (A) Figure 5. OPA7 Dropout from ±5 V vs. Load Current Although operating conditions imposed on the AD8/AD8 (±3 V) are less favorable than the OPA7 (±5 V), it can be seen that the AD8/AD8 have much better drive capability (lower headroom to the supply) for a given load current. Operating with Supplies Greater than ±3 V The AD8/AD8 maximum operating voltage is specified at ±3 V. When ±3 V is not readily available, an inexpensive LDO can provide ± V from a nominal ±5 V supply Rev. F Page 8 of

19 AD8/AD8 Input Offset Voltage Adjustment +5V Offset of AD8 is very small and normally does not require additional offset adjustment. However, the offset adjust pins can be used as shown in Figure to further reduce the dc offset. By using resistors in the range of 5 kω, offset trim range is ±3.3 mv. V IN Ω 3 7 AD8 5 V OUT 3 V+ 7 AD8 5 R V OUT V Figure. Offset Voltage Nulling Circuit Programmable Gain Amplifier (PGA) The combination of low noise, low input bias current, low input offset voltage, and low temperature drift make the AD8/ AD8 a perfect solution for programmable gain amplifiers. PGAs are often used immediately after sensors to increase the dynamic range of the measurement circuit. Historically, the large on resistance of switches (combined with the large IB currents of amplifiers) created a large dc offset in PGAs. Recent and improved monolithic switches and amplifiers completely remove these problems. A PGA discrete circuit is shown in Figure 7. In Figure 7, when the pa bias current of the AD8 is dropped across the (<5 Ω) RON of the switch, it results in a negligible offset error. When high precision resistors are used, as in the circuit of Figure 7, the error introduced by the PGA is within the ½ LSB requirement for a -bit system. 73- A A G A B Y Y Y Y 3 7HC39 5pF V IN IN IN3 IN 5V V L V DD 3 ADG5 V SS +5V S D S D S3 D3 S D GND V Figure 7. High Precision PGA 7 Ω Ω G = + G = + G = + G = +. Room temperature error calculation due to RON and IB ΔVOS = IB RON = pa 5 Ω = pv Total Offset = AD8 (Offset) + ΔVOS Total Offset = AD8 (Offset_Trimmed) + ΔVOS Total Offset = 5 μv + pv 5 μv Full temperature error calculation due to RON and IB ΔVOS (@ 85 C) = IB (@ 85 C) RON (@ 85 C) = 5 pa 5 Ω = 3.75 nv 3. The temperature coefficient of switch and AD8/AD8 combined is essentially the same as the TCVOS of the AD8/AD8. ΔVOS/ΔT(total) = ΔVOS/ΔT(AD8/AD8) + ΔVOS/ΔT(IB RON) ΔVOS/ΔT(total) =.5 μv/ C +. nv/ C.5 μv/ C Rev. F Page 9 of

20 AD8/AD8 High Speed Instrumentation Amplifier The 3-op-amp instrumentation amplifiers shown in Figure 8 can provide a range of gains from unity up to or higher. The instrumentation amplifier configuration features high commonmode rejection, balanced differential inputs, and stable, accurately defined gain. Low input bias currents and fast settling are achieved with the JFET input AD8/AD8. Most instrumentation amplifiers cannot match the high frequency performance of this circuit. The circuit bandwidth is 5 MHz at a gain of, and close to 5 MHz at a gain of. Settling time for the entire circuit is 55 ns to.% for a V step (gain = ). Note that the resistors around the input pins need to be small enough in value so that the RC time constant they form in combination with stray circuit capacitance does not reduce circuit bandwidth. +INB +INA RG 3 R kω V+ / AD8 U 5 V R7 kω R8 kω / AD8 U 8 R C5 pf R 7 C 5pF 3 V+ 7 AD8 U V R5 kω C3 5pF V OUT R kω In active filter applications using operational amplifiers, the dc accuracy of the amplifier is critical to optimal filter performance. The offset voltage and bias current of the amplifier contribute to output error. Input offset voltage is passed by the filter and can be amplified to produce excessive output offset. For low frequency applications requiring large value input resistors, bias and offset currents flowing through these resistors also generate an offset voltage. At higher frequencies, the dynamic response of the amplifier must be carefully considered. In this case, slew rate, bandwidth, and open-loop gain play a major role in amplifier selection. The slew rate must be both fast and symmetrical to minimize distortion. The bandwidth of the amplifier, in conjunction with the gain of the filter, dictates the frequency response of the filter. The use of high performance amplifiers, such as the AD8/AD8, minimizes both dc and ac errors in all active filter applications. Second-Order, Low-Pass Filter Figure 9 shows the AD8 configured as a second-order, Butterworth, low-pass filter. With the values as shown, the design corner was MHz, and the bench measurement was 97 khz. The wide bandwidth of the AD8/AD8 allows corner frequencies into the megahertz range, but the input capacitances should be taken into account by making C and C smaller than the calculated values. The following equations can be used for component selection: R = R = User Selected (Typical Values = kω to kω) C = C =. ( π )( f )( R) CUTOFF.77 ( π )( f )( R) CUTOFF where C and C are in farads. C pf Figure 8. High Speed Instrumentation Amplifier High Speed Filters The four most popular configurations are Butterworth, Elliptical, Bessel (Thompson), and Chebyshev. Each type has a response that is optimized for a given characteristic, as shown in Table V IN R Ω R Ω C pf 3 +3V 7 AD8 U 3V Figure 9. Second-Order, Low-Pass Filter C pf 5 VOUT 73-9 Table. Filter Types Type Sensitivity Overshoot Phase Amplitude (Pass Band) Butterworth Moderate Good Maximum flat Chebyshev Good Moderate Nonlinear Equal ripple Elliptical Best Poor Equal ripple Bessel (Thompson) Poor Best Linear Rev. F Page of

21 AD8/AD8 High Speed, Low Noise Differential Driver The AD8 is a perfect candidate as a low noise differential driver for many popular ADCs. There are also other applications (such as balanced lines) that require differential drivers. The circuit of Figure 7 is a unique line driver widely used in industrial applications. With ±3 V supplies, the line driver can deliver a differential signal of 3 V p-p into a kω load. The high slew rate and wide bandwidth of the AD8 combine to yield a full power bandwidth of 5 khz while the low noise front end produces a referred-to-input noise voltage spectral density of nv/ Hz. The design is a balanced transmission system without transformers, where output common-mode rejection of noise is of paramount importance. Like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of. This allows the design to be easily set to noninverting, inverting, or differential operation. 3 V+ V R AD8 R3 R8 R9 3 5 V+ / AD8 V U R V+ / AD8 U3 V R Figure 7. Differential Driver 7 R 5Ω R R 5Ω R3 V O V O = V IN V O R5 R R7 V O 73-7 Rev. F Page of

22 AD8/AD8 OUTLINE DIMENSIONS PIN BSC COPLANARITY MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure 7. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters.8... (.57) 3.8 (.97).5 (.98). (.) COPLANARITY. SEATING PLANE 5. (.98).8 (.89) (.5) BSC. (.) 5.8 (.8).75 (.88).35 (.53).5 (.).3 (.).5 (.98).7 (.7).5 (.9).5 (.99).7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 8 Figure 7. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 5 7-A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8AR C to +5 C 8-Lead SOIC_N R-8 AD8AR-REEL C to +5 C 8-Lead SOIC_N R-8 AD8AR-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8ARZ C to +5 C 8-Lead SOIC_N R-8 AD8ARZ-REEL C to +5 C 8-Lead SOIC_N R-8 AD8ARZ-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8ARM-REEL C to +5 C 8-Lead MSOP RM-8 BA AD8ARM-R C to +5 C 8-Lead MSOP RM-8 BA AD8ARMZ-REEL C to +5 C 8-Lead MSOP RM-8 BA# AD8ARMZ-R C to +5 C 8-Lead MSOP RM-8 BA# AD8BR C to +5 C 8-Lead SOIC_N R-8 AD8BR-REEL C to +5 C 8-Lead SOIC_N R-8 AD8BR-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8BRZ C to +5 C 8-Lead SOIC_N R-8 AD8BRZ-REEL C to +5 C 8-Lead SOIC_N R-8 AD8BRZ-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8AR C to +5 C 8-Lead SOIC_N R-8 AD8AR-REEL C to +5 C 8-Lead SOIC_N R-8 AD8AR-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8ARZ C to +5 C 8-Lead SOIC_N R-8 AD8ARZ-REEL C to +5 C 8-Lead SOIC_N R-8 AD8ARZ-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8BR C to +5 C 8-Lead SOIC_N R-8 AD8BR-REEL C to +5 C 8-Lead SOIC_N R-8 AD8BR-REEL7 C to +5 C 8-Lead SOIC_N R-8 AD8BRZ C to +5 C 8-Lead SOIC_N R-8 AD8BRZ-REEL C to +5 C 8-Lead SOIC_N R-8 AD8BRZ-REEL7 C to +5 C 8-Lead SOIC_N R-8 Z = RoHS Compliant Part, # denotes RoHs-compliant product can be top or bottom marked. Rev. F Page of

23 AD8/AD8 NOTES Rev. F Page 3 of

24 AD8/AD8 NOTES 8 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D73--5/8(F) Rev. F Page of