Dual Low Bias Current Precision Operational Amplifier OP297

Transcription

1 Dual Low Bias Current Precision Operational Amplifier FEATURES Low offset voltage: μv maximum Low offset voltage drift:. μv/ C maximum Very low bias current: pa maximum Very high open-loop gain: 2 V/mV minimum Low supply current (per amplifier): 2 μa maximum Operates from ±2 V to ±2 V supplies High common-mode rejection: 2 db minimum APPLICATIONS Strain gage and bridge amplifiers High stability thermocouple amplifiers Instrumentation amplifiers Photocurrent monitors High gain linearity amplifiers Long-term integrators/filters Sample-and-hold amplifiers Peak detectors Logarithmic amplifiers Battery-powered systems GENERAL DESCRIPTION The is the first dual op amp to pack precision performance into the space saving, industry-standard 8-lead SOIC package. The combination of precision with low power and extremely low input bias current makes the dual useful in a wide variety of applications. Precision performance of the includes very low offset (less than μv) and low drift (less than. μv/ C). Openloop gain exceeds 2 V/mV, ensuring high linearity in every application. Errors due to common-mode signals are eliminated by the common-mode rejection of over 2 db, which minimizes offset voltage changes experienced in battery-powered systems. The supply current of the is under 2 μa. The uses a super-beta input stage with bias current cancellation to maintain picoamp bias currents at all temperatures. This is in contrast to FET input op amps whose bias currents start in the picoamp range at 2 C, but double for every C rise in temperature, to reach the nanoamp range above 8 C. Input bias current of the is under pa at 2 C and is under 4 pa over the military temperature range per amplifier. This part can operate with supply voltages as low as ±2 V. INPUT CURRENT (pa) NUMBER OF UNITS PIN CONFIGURATION OUTA INA 2 INA 3 V 4 A B Figure. 8 V OUTB INB INB TEMPERATURE ( C) I OS I B I B Figure 2. Low Bias Current over Temperature 2 UNITS INPUT OFFSET VOLTAGE (µv) 3- V CM = V Figure 3. Very Low Offset T A = 2 C V CM = V Combining precision, low power, and low bias current, the is ideal for a number of applications, including instrumentation amplifiers, log amplifiers, photodiode preamplifiers, and long term integrators. For a single device, see the OP9; for a quad device, see the OP Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA 22-9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Configuration... Revision History... 2 Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution... 4 Typical Performance Characteristics... Applications Information... 9 AC Performance...9 Guarding and Shielding...9 Open-Loop Gain Linearity... Application Circuits... Precision Absolute Value Amplifier... Precision Current Pump... Precision Positive Peak Detector... Simple Bridge Conditioning Amplifier... Nonlinear Circuits... 2 Outline Dimensions... 3 Ordering Guide... 4 REVISION HISTORY 4/8 Rev. F to Rev. G Changes to Table 2 Conditions... 3 Changes to Table 2 Power Supply Rejection Parameter... 3 Changes to Figure, Figure, Figure... Changes to Figure... Updated Outline Dimensions... 3 Changes to Ordering Guide / Rev. E to Rev. F Updated Format... Universal Changes to Features... Deleted Spice Macro Model Section... 9 Updated Outline Dimensions... 3 Changes to Ordering Guide... 4 /2 Rev. C to Rev. D Edits to Figure... /2 Rev. B to Rev. C Edits to Specifications... 2 Deleted Wafer Test Limits... 3 Deleted Dice Characteristics... 3 Deleted Absolute Maximum Ratings... 4 Edits to Ordering Guide... 4 Updated Outline Dimensions... 2 /3 Rev. D to Rev. E Changes to TPCs 3 and... 4 Edits to Figures 2 and Changes to Nonlinear Circuits Section... 8 Rev. G Page 2 of

3 SPECIFICATIONS ELECTRICAL VS = ± V, TA = 2 C, unless otherwise noted. Table. E F G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Input Offset Voltage VOS μv Long-Term Input Voltage... μv/month Stability Input Offset Current IOS VCM = V pa Input Bias Current IB VCM = V 2 ± 3 ± ±2 pa Input Noise Voltage en p-p. Hz to Hz... μv p-p Input Noise Voltage Density en fout = Hz nv/ Hz fout = Hz nv/ Hz Input Noise Current Density in fout = Hz fa/ Hz Input Resistance Differential Mode RIN MΩ Common-Mode RINCM GΩ Large Signal Voltage Gain AVO VOUT = ± V, V/mV RL = 2 kω Input Voltage Range VCM ±3 ±4 ±3 ±4 ±3 ±4 V Common-Mode Rejection CMRR VCM = ±3 V db Power Supply Rejection PSRR VS = ±2 V to db ±2 V Output Voltage Swing VOUT RL = kω ±3 ±4 ±3 ±4 ±3 ±4 V RL = 2 kω ±3 ±3. ±3 ±3. ±3 ±3. V Supply Current per Amplifier ISY No load μa Supply Voltage VS Operating range ±2 ±2 ±2 ±2 ±2 ±2 V Slew Rate SR V/μs Gain Bandwidth Product GBWP AV = khz Channel Separation CS VOUT = 2 V p-p, db fout = Hz Input Capacitance CIN pf Guaranteed by CMR VS = ± V, 4 C TA 8 C, unless otherwise noted. Table 2. E F G Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit Input Offset Voltage VOS μv Average Input Offset Voltage Drift TCVOS μv/ C Input Offset Current IOS VCM = V pa Input Bias Current IB VCM = V ±4 8 ± 8 ± pa Large Signal Voltage Gain AVO VOUT = ± V, V/mV RL = 2 kω Input Voltage Range VCM ±3 ±3. ±3 ±3. ±3 ±3. V Common-Mode Rejection CMRR VCM = ± db Power Supply Rejection PSRR VS = ±2. V to db ±2 V Output Voltage Swing VOUT RL = kω ±3 ±3.4 ±3 ±3.4 ±3 ±3.4 V Supply Current per Amplifier ISY No load μa Supply Voltage VS Operating range ±2. ±2 ±2. ±2 ±2. ±2 V Guaranteed by CMR test. Rev. G Page 3 of

4 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±2 V Input Voltage ±2 V Differential Input Voltage 4 V Output Short-Circuit Duration Indefinite Storage Temperature Range Z-Suffix C to C P-Suffix, S-Suffix C to C Operating Temperature Range E (Z-Suffix) 4 C to 8 C F, G (P-Suffix, S-Suffix) 4 C to 8 C Junction Temperature Z-Suffix C to C P-Suffix, S-Suffix C to C Lead Temperature (Soldering, sec) 3 C THERMAL RESISTANCE θja is specified for worst-case mounting conditions, that is, θja is specified for device in socket for CERDIP and PDIP packages; θja is specified for device soldered to printed circuit board for the SOIC package. Table 4. Thermal Resistance Package Type θja θjc Unit 8-Lead CERDIP (Z-Suffix) 34 2 C/W 8-Lead PDIP (P-Suffix) 9 3 C/W 8-Lead SOIC (S-Suffix) 4 C/W ESD CAUTION For supply voltages less than ±2 V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. /2 2kΩ V 2V Hz kω Ω /2 V 2 CHANNEL SEPARATION = 2 log V V 2 / Figure 4. Channel Separation Test Circuit 3-4 Rev. G Page 4 of

5 TYPICAL PERFORMANCE CHARACTERISTICS 4 2 UNITS T A = 2 C V CM = V 4 V CM = V 3 NUMBER OF UNITS 2 INPUT CURRENT (pa) 2 2 I OS I B I B INPUT OFFSET VOLTAGE (µv) Figure. Typical Distribution of Input Offset Voltage TEMPERATURE ( C) Figure 8. Input Bias, Offset Current vs. Temperature UNITS T A = 2 C V CM = V 4 V CM = V NUMBER OF UNITS INPUT CURRENT (pa) 2 I B I B I OS INPUT BIAS CURRENT (pa) Figure. Typical Distribution of Input Bias Current 3-4 COMMON-MODE VOLTAGE (V) Figure 9. Input Bias, Offset Current vs. Common-Mode Voltage 3-9 NUMBER OF UNITS UNITS T A = 2 C V CM = V DEVIATION FROM FINAL VALUE (µv) ±3 ±2 ± T A = 2 C V CM = V INPUT OFFSET CURRENT (pa) Figure. Typical Distribution of Input Offset Current TIME AFTER POWER APPLIED (Minutes) Figure. Input Offset Voltage Warm-Up Drift 3- Rev. G Page of

6 EFFECTIVE OFFSET VOLTAGE (µv) k k BALANCED OR UNBALANCED V CM = V C T A 2 C TOTAL SUPPLY CURRENT (µa) NO LOAD T A = 2 C T A = 2 C T A = C T A = 2 C k k k M M SOURCE RESISTANCE (Ω) Figure. Effective Offset Voltage vs. Source Resistance 3-8 ± ± ± ±2 SUPPLY VOLTAGE (V) Figure 4. Total Supply Current vs. Supply Voltage 3-4 EFFECTIVE OFFSET VOLTAGE DRIFT (µv/ C) BALANCED OR UNBALANCED V CM = V. k k k M M M SOURCE RESISTANCE (Ω) Figure 2. Effective TCVOS vs. Source Resistance 3-2 COMMON-MODE REJECTION (db) T A = 2 C k k k M FREQUENCY (Hz) Figure. Common-Mode Rejection vs. Frequency 3- SHORT-CIRCUIT CURRENT (ma) 3 3 T A = C 2 2 T A = 2 C T A = 2 C OUTPUT SHORTED TO GROUND T A = 2 C 2 T A = 2 C 2 3 T A = C TIME FROM OUTPUT SHORT (Minutes) Figure 3. Short-Circuit Current vs. Time, Temperature 3-3 POWER SUPPLY REJECTION (db) T A = 2 C ΔV S = V p-p k k k M FREQUENCY (Hz) Figure. Power Supply Rejection vs. Frequency 3- Rev. G Page of

7 VOLTAGE NOISE DENSITY (nv/ Hz) k T A = 2 C V S = ±2V TO ±V CURRENT NOISE VOLTAGE NOISE k CURRENT NOISE DENSITY (fa/ Hz) DIFFERENTIAL INPUT VOLTAGE (µv/div) R L = kω V CM = V T A = 2 C T A = 2 C T A = C k FREQUENCY (Hz) Figure. Voltage Noise Density and Current Noise Density vs. Frequency 3- OUTPUT VOLTAGE (V) Figure 2. Differential Input Voltage vs. Output Voltage 3-2 TOTAL NOISE DENSITY (nv/ Hz). T A = 2 C V S = ±2V TO ±2V Hz khz OUTPUT SWING (V p-p) T A = 2 C A VCL = % THD f OUT = khz khz Hz. k k k M SOURCE RESISTANCE (Ω) Figure 8. Total Noise Density vs. Source Resistance M 3-8 k k LOAD RESISTANCE (Ω) Figure 2. Output Swing vs. Load Resistance 3-2 OPEN-LOOP GAIN (V/mV) k k T A = 2 C T A = C T A = 2 C V OUT = ±V OUTPUT SWING (V p-p) T A = 2 C A VCL = % THD f OUT = khz R L = kω LOAD RESISTANCE (kω) Figure 9. Open-Loop Gain vs. Load Resistance 3-9 k k k FREQUENCY (Hz) Figure 22. Maximum Output Swing vs. Frequency 3-22 Rev. G Page of

8 8 GAIN C L = 3pF R L = MΩ k T A = 2 C OPEN-LOOP GAIN (db) 4 2 PHASE T A = C PHASE SHIFT (Degrees) OUTPUT IMPEDANCE (Ω) T A = 2 C 2 k k k M M FREQUENCY (Hz) Figure 23. Open-Loop Gain, Phase vs. Frequency k k k M FREQUENCY (Hz) Figure 2. Open-Loop Output Impedance vs. Frequency 3-2 T A = 2 C A VCL = V OUT = mv p-p EDGE OVERSHOOT (%) EDGE k k LOAD CAPACITANCE (pf) Figure 24. Small Signal Overshoot vs. Load Capacitance 3-24 Rev. G Page 8 of

9 APPLICATIONS INFORMATION Extremely low bias current over a wide temperature range makes the attractive for use in sample-and-hold amplifiers, peak detectors, and log amplifiers that must operate over a wide temperature range. Balancing input resistances is unnecessary with the. Offset voltage and TCVOS are degraded only minimally by high source resistance, even when unbalanced. The input pins of the are protected against large differential voltage by back-to-back diodes and current-limiting resistors. Common-mode voltages at the inputs are not restricted and can vary over the full range of the supply voltages used. The requires very little operating headroom about the supply rails and is specified for operation with supplies as low as 2 V. Typically, the common-mode range extends to within V of either rail. The output typically swings to within V of the rails when using a kω load. AC PERFORMANCE The ac characteristics of the are highly stable over its full operating temperature range. Unity gain small signal response is shown in Figure 2. Extremely tolerant of capacitive loading on the output, the displays excellent response with pf loads (see Figure 2). 9 9 % 2mV µs Figure 28. Large Signal Transient Response (AVCL = ) GUARDING AND SHIELDING To maintain the extremely high input impedances of the, care is taken in circuit board layout and manufacturing. Board surfaces must be kept scrupulously clean and free of moisture. Conformal coating is recommended to provide a humidity barrier. Even a clean PCB can have pa of leakage currents between adjacent traces, therefore guard rings should be used around the inputs. Guard traces operate at a voltage close to that on the inputs, as shown in Figure 29, to minimize leakage currents. In noninverting applications, the guard ring should be connected to the common-mode voltage at the inverting input. In inverting applications, both inputs remain at ground, so the guard trace should be grounded. Guard traces should be placed on both sides of the circuit board. UNITY-GAIN FOLLOWER 3-28 NONINVERTING AMPLIFIER % 2mV µs Figure 2. Small Signal Transient Response (CL = pf, AVCL = ) 3-2 /2 /2 INVERTING AMPLIFIER MINI-DIP BOTTOM VIEW 8 9 /2 B A % Figure 29. Guard Ring Layout and Considerations mV µs Figure 2. Small Signal Transient Response (CL = pf, AVCL = ) 3-2 Rev. G Page 9 of

10 OPEN-LOOP GAIN LINEARITY The has both an extremely high gain of 2 V/mV minimum and constant gain linearity. This enhances the precision of the and provides for very high accuracy in high closed-loop gain applications. Figure 3 illustrates the typical open-loop gain linearity of the over the military temperature range. DIFFERENTIAL INPUT VOLTAGE (µv/div) R L = kω V CM = V T A = 2 C T A = 2 C T A = C OUTPUT VOLTAGE (V) Figure 3. Open-Loop Linearity of the 3-3 Rev. G Page of

11 APPLICATION CIRCUITS PRECISION ABSOLUTE VALUE AMPLIFIER The circuit in Figure 3 is a precision absolute value amplifier with an input impedance of 3 MΩ. The high gain and low TCVOS of the ensure accurate operation with microvolt input signals. In this circuit, the input always appears as a common-mode signal to the op amps. The CMR of the exceeds 2 db, yielding an error of less than 2 ppm. V IN V C2.µF 2 8 /2 3 4 V C 3pF C3.µF R kω D N448 D2 N448 R3 kω /2 R2 2kΩ Figure 3. Precision Absolute Value Amplifier V < V OUT < V PRECISION CURRENT PUMP Maximum output current of the precision current pump shown in Figure 32 is ± ma. Voltage compliance is ± V with ± V supplies. Output impedance of the current transmitter exceeds 3 MΩ with linearity better than bits. R through R4 should be matched resistors. V IN R kω R2 kω R3 kω 2 /2 3 R4 kω V 8 V /2 R kω Figure 32. Precision Current Pump I OUT ma MAX V IN V IN I OUT = = = ma/v R Ω PRECISION POSITIVE PEAK DETECTOR In Figure 33, the CH must be of polystyrene, Teflon, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the. kω V N448.µF 2 /2 kω V 3 /2 IN kω C H.µF RESET kω 2N93 V Figure 33. Precision Positive Peak Detector V OUT SIMPLE BRIDGE CONDITIONING AMPLIFIER Figure 34 shows a simple bridge conditioning amplifier using the. The transfer function is V OUT = V REF ΔR RF R ΔR R The REF43 provides an accurate and stable reference voltage for the bridge. To maintain the highest circuit accuracy, RF should be.% or better with a low temperature coefficient. V REF43 4 V REF R ΔR 8 /2 4 2 /2 3 R F V OUT = V REF ΔR R ΔR V OUT Figure 34. Simple Bridge Condition Amplifier Using the R F R Rev. G Page of

12 NONLINEAR CIRCUITS Due to its low input bias currents, the is an ideal log amplifier in nonlinear circuits such as the square and square root circuits shown in Figure 3 and Figure 3. Using the squaring circuit of Figure 3 as an example, the analysis begins by writing a voltage loop equation across Transistor Q, Transistor Q2, Transistor Q3, and Transistor Q4. V T I ln I IN S V T2 I ln I IN S2 = V T3 I ln I OUT S3 V T4 I ln I All the transistors of the MAT4 are precisely matched and at the same temperature, so the IS and VT terms cancel, where 2lnIIN = lniout lniref = ln(iout IREF) Exponentiating both sides of the equation leads to I OUT = ( I ) I IN REF 2 Op Amp A2 forms a current-to-voltage converter, which gives VOUT = R2 IOUT. Substituting (VIN/R) for IIN and the previous equation for IOUT yields V OUT = R2 I REF 2 V IN R A similar analysis made for the square root circuit of Figure 3 leads to its transfer function V OUT = R2 ( V )( I ) IN R REF C2 pf R2 33kΩ REF S4 V IN R 33kΩ C pf V 2 8 /2 3 4 V Q /2 I OUT 3 Q2 R2 33kΩ MAT4E Q3 Figure 3. Square Root Amplifier 8 C2 pf 9 R3 kω 4 3 Q4 2 V R4 kω V OUT In these circuits, IREF is a function of the negative power supply. To maintain accuracy, the negative supply should be well regulated. For applications where very high accuracy is required, a voltage reference can be used to set IREF. An important consideration for the squaring circuit is that a sufficiently large input voltage can force the output beyond the operating range of the output op amp. Resistor R4 can be changed to scale IREF or R; R2 can be varied to keep the output voltage within the usable range. Unadjusted accuracy of the square root circuit is better than.% over an input voltage range of mv to V. For a similar input voltage range, the accuracy of the squaring circuit is better than.%. I REF Q 3 Q2 /2 IOUT MAT4E V OUT V IN R 33kΩ C pf V 2 8 /2 3 4 V 8 9 Q3 R3 kω V Figure 3. Squaring Amplifier I REF R4 kω 4 Q Rev. G Page 2 of

13 OUTLINE DIMENSIONS.4 (.).3 (9.2).3 (9.2).2 (.33) MAX. (3.8).3 (3.3). (2.92).22 (.).8 (.4).4 (.3) 8. (2.4) BSC.28 (.).2 (.3) 4.24 (.). (.38) MIN SEATING PLANE. (.3) MIN. (.2) MAX. (.38) GAUGE PLANE.32 (8.2).3 (.8).3 (.2).43 (.92) MAX.9 (4.9).3 (3.3). (2.92).4 (.3). (.2).8 (.2). (.8). (.2).4 (.4) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 3. 8-Lead Plastic Dual In-Line Package [PDIP] P-Suffix (N-8) Dimensions shown in inches and (millimeters) -A. (.3) MIN. (.4) MAX (.8).22 (.9). (2.4) BSC.2 (.8) MAX.4 (.29) MAX. (.2). (.38).32 (8.3).29 (.3).2 (.8).2 (3.8).23 (.8).4 (.3). (.8).3 (.). (3.8) MIN SEATING PLANE. (.38).8 (.2) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Ceramic Dual In-Line Package [CERDIP] Z-Suffix (Q-8) Dimensions shown in inches and (millimeters) Rev. G Page 3 of

14 . (.98) 4.8 (.89) 4. (.4) 3.8 (.49) (.244).8 (.2284).2 (.98). (.4) COPLANARITY. SEATING PLANE.2 (.) BSC. (.88).3 (.32). (.2).3 (.22) 8.2 (.98). (.). (.9).2 (.99).2 (.).4 (.) 4 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) 24-A ORDERING GUIDE Model Temperature Range Package Description Package Options EZ 4 C to 8 C 8-Lead CERDIP Q-8 (Z-Suffix) FP 4 C to 8 C 8-Lead PDIP N-8 (P-Suffix) FPZ 4 C to 8 C 8-Lead PDIP N-8 (P-Suffix) FS 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) FS-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) FS-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) FSZ 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) FSZ-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) FSZ-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) GP 4 C to 8 C 8-Lead PDIP N-8 (P-Suffix) GPZ 4 C to 8 C 8-Lead PDIP N-8 (P-Suffix) GS 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) GS-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) GS-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) GSZ 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) GSZ-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) GSZ-REEL 4 C to 8 C 8-Lead SOIC_N R-8 (S-Suffix) Z = RoHS Compliant Part. Rev. G Page 4 of

15 NOTES Rev. G Page of

16 NOTES 28 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D3--4/8(G) Rev. G Page of