Precision Picoampere Input Current Quad Operational Amplifier OP497

Transcription

1 Precision Picoampere Input Current Quad Operational Amplifier FEATURES Low offset voltage: 7 μv maximum Low offset voltage drift:. μv/ C maximum Very low bias current C: pa maximum 4 C to +8 C: pa maximum Very high open-loop gain: V/mV minimum Low supply current (per amplifier): 6 μa maximum Operates from ± V to ± V supplies High common-mode rejection: 4 db minimum APPLICATIONS Strain gage and bridge amplifiers High stability thermocouple amplifiers Instrumentation amplifiers Photocurrent monitors High gain linearity amplifiers Long-term integrators/filters Sample-and-hold amplifiers Peak detectors Logarithmic amplifiers Battery-powered systems k PIN CONNECTIONS OUT A 6 OUT D IN A IN D +IN A 4 +IN D V+ 4 V +IN B +IN C IN B 6 IN C OUT B 7 OUT C NC 8 9 NC NC = NO CONNECT Figure. 6-Lead Wide Body SOIC (RW-6) OUT A IN A +IN A V+ 4 +IN B IN B 6 OUT B 7 4 OUT D IN D +IN D V +IN C 9 IN C 8 OUT C Figure. 4-Lead PDIP (N-4) 9-9- V CM = V GENERAL DESCRIPTION The is a quad op amp with precision performance in the space-saving, industry standard 6-lead SOlC package. Its combination of exceptional precision with low power and extremely low input bias current makes the quad useful in a wide variety of applications. Precision performance of the includes very low offset (< μv) and low drift (<. μv/ C). Open-loop gain exceeds V/mV ensuring high linearity in every application. Errors due to common-mode signals are eliminated by its commonmode rejection of > db. The has a power supply rejection of > db which minimizes offset voltage changes experienced in battery-powered systems. The supply current of the is <6 μa per amplifier, and it can operate with supply voltages as low as ± V. The uses a superbeta input stage with bias current cancellation to maintain picoamp bias currents at all temperatures. This is in contrast to FET input op amps whose bias currents start in the picoamp range at C but double for every C rise in temperature to reach the nanoamp range above 8 C. The input bias current of the is < pa at C. INPUT CURRENT (pa) I OS 7 7 TEMPERATURE ( C) Figure. Input Bias, Offset Current vs. Temperature Combining precision, low power, and low bias current, the is ideal for a number of applications, including instrumentation amplifiers, log amplifiers, photodiode preamplifiers, and longterm integrators. For a single device, see the OP97 data sheet, and for a dual device, see the OP97 data sheet. I B +I B 9- Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Connections... Revision History... Specifications... Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution... 4 Typical Performance Characteristics... Applications Information... AC Performance... Guarding And Shielding... Open-Loop Gain Linearity... Applications Circuit... Precision Absolute Value Amplifier... Precision Current Pump... Precision Positive Peak Detector... Simple Bridge Conditioning Amplifier... Nonlinear Circuits... Outline Dimensions... 4 Ordering Guide... REVISION HISTORY /9 Rev. D to Rev. E Deleted 4-Lead CERDIP... Throughout Changes to Features Section and General Description Section... Delete Military Processed Devices Text, SMD Part Number, ADI Part Number Table, and Dice Characteristics Figure... Changes to Table... Changes to Absolute Maximum Ratings Section... 4 Changes to Figure... 6 Changes to Figure 8 and Figure Changes to Figure 6 and Figure Deleted Spice Macro-Model Section... Changes to Applications Information Section... Moved Figure... Deleted Table I. SPICE Net-List... Changes to Open-Loop Gain Linearity Section and Figure... Changes to Figure 4... Updated Outline Dimensions... 4 Changes to Ordering Guide... / Rev. C to Rev. D Edits to Pin Connection Headings... Deleted Wafer Test Limits... Edits to Absolute Maximum Ratings... Edits to Outline Dimensions... 6 Edits to Ordering Guide... 7 Rev. E Page of 6

3 SPECIFICATIONS TA = C, VS = ± V, unless otherwise noted. Table. F Grade G Grade Parameter Symbol Condition Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS μv 4 C +8 C 7 μv Average Input Offset Voltage Drift TCVOS TMIN TMAX μv/ C Long-Term Input Offset Voltage.. μv/month Stability Input Bias Current IB VCM = V 4 6 pa 4 TA +8 C 6 8 pa Average Input Bias Current Drift TCIB 4 TA +8 C.. pa/ C Input Offset Current IOS VCM = V pa 4 TA +8 C 8 pa Average Input Offset Current Drift TCIOS..4 pa/ C Input Voltage Range IVR ± ±4 ± ±4 V TMIN TMAX ± ±. ± ±. V Common-Mode Rejection CMR VCM = ± V 4 4 db TMIN TMAX 8 8 db Large Signal Voltage Gain AVO VO = ± V, RL = kω 4 4 V/mV 4 TA +8 C 8 8 V/mV Input Resistance Differential Mode RIN MΩ Input Resistance Common Mode RINCM GΩ Input Capacitance CIN pf OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = kω ± ±.7 ± ±.7 V RL = kω, TMIN TMAX ± ±4 ± ±4 V RL = kω ± ±. ± ±. V Short Circuit ISC ± ± ma POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ± V to ± V 4 4 db VS = ±. V to ± V, TMIN TMAX 8 8 db Supply Current (per Amplifier) ISY No load 6 6 μa TMIN TMAX μa Supply Voltage Range VS Operating range ± ± ± ± V TMIN TMAX ±. ± ±. ± V DYNAMIC PERFORMANCE Slew Rate SR.... V/μs Gain Bandwidth Product GBW khz Channel Separation CS VO = V p-p, fo = Hz db NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz.. μv/p-p Voltage Noise Density en en = Hz 7 7 nv/ Hz en = khz nv/ Hz Current Noise Density in in = Hz fa/ Hz Guaranteed by CMR test. Rev. E Page of 6

4 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply to packaged parts. Table. Parameter Rating Supply Voltage ± V Input Voltage V Differential Input Voltage 4 V Output Short-Circuit Duration Indefinite Storage Temperature Range 6 C to + C Operating Temperature Range 4 C to +8 C Junction Temperature Range 6 C to + C Lead Temperature (Soldering, 6 sec) C THERMAL RESISTANCE θja is specified for the worst-case mounting conditions, that is, θja is specified for a device in socket for the PDIP package, and θja is specified for a device soldered to the printed circuit board (PCB) for the SOIC package. Table. Package Type θja θjc Unit 4-Lead PDIP (N-4) 76 C/W 6-Lead SOIC (RW-6) 9 C/W For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. /4 V V Hz + kω kω Ω /4 + V CHANNEL SEPARATION = log ( ) V /, Figure 4. Channel Separation Test Circuit V 9-4 ESD CAUTION Rev. E Page 4 of 6

5 TYPICAL PERFORMANCE CHARACTERISTICS TA = C, VS = ± V, unless otherwise noted. 4 V CM = V 4 V CM = V PERCENTAGE OF UNITS PERCENTAGE OF UNITS INPUT OFFSET VOLTAGE (µv) Figure. Typical Distribution of Input Offset Voltage TCV OS (µv/ C) Figure 8. Typical Distribution of TCVOS V CM = V k V CM = V PERCENTAGE OF UNITS INPUT CURRENT (pa) I B +I B INPUT BIAS CURRENT (pa) Figure 6. Typical Distribution of Input Bias Current 9-7 I OS 7 7 TEMPERATURE ( C) Figure 9. Input Bias, Offset Current vs. Temperature 9-6 V CM = V 7 6 PERCENTAGE OF UNITS 4 INPUT BIAS CURRENT (pa) 4 I B +I B 4 INPUT OFFSET CURRENT (pa) Figure 7. Typical Distribution of Input Offset Current COMMON-MODE VOLTAGE (V) Figure. Input Bias Current vs. Common-Mode Voltage 9- Rev. E Page of 6

6 DEVIATION FROM FINAL VALUE (µv) ± ± ± V CM = V VOLTAGE NOISE DENSITY (nv/ Hz) k V S = ±V TO ±V CURRENT NOISE VOLTAGE NOISE CURRENT NOISE DENSITY (fa/ Hz) 4 TIME AFTER POWER APPLIED (Minutes) Figure. Input Offset Voltage Warm-Up Drift 9- k FREQUENCY (Hz) Figure 4. Voltage Noise Density vs. Frequency 9- EFFECTIVE OFFSET VOLTAGE (µv) k k BALANCED OR UNBALANCED V CM = V TOTAL NOISE DENSITY (µv/ Hz). V S = ±V TO ±V Hz khz k k k M M SOURCE RESISTANCE (Ω) Figure. Effective Offset Voltage vs. Source Resistance 9-. k k k M M SOURCE RESISTANCE (Ω) Figure. Total Noise Density vs. Source Resistance 9-6 EFFECTIVE OFFSET VOLTAGE (µv/ C) BALANCED OR UNBALANCED V CM = V NOISE VOLTAGE (mv/div) 9 % mv s. k k k M M M SOURCE RESISTANCE (Ω) Figure. Effective TCVOS vs. Source Resistance TIME (Seconds) Figure 6.. Hz to Hz Noise Voltage 9-7 Rev. E Page 6 of 6

7 OPEN-LOOP GAIN (db) PHASE GAIN C L = pf R L = MΩ 9 8 PHASE (Degrees) COMMON-MODE REJECTION (db) k k k M M FREQUENCY (Hz) Figure 7. Open-Loop Gain and Phase vs. Frequency 9-8 k k k FREQUENCY (Hz) Figure. Common-Mode Rejection vs. Frequency M 9- k 6 4 OPEN-LOOP GAIN (V/mV) k T A = C V O = ±V LOAD RESISTANCE (kω) Figure 8. Open-Loop Gain vs. Load Resistance 9-9 POWER SUPPLY REJECTION (db) PSR PSR k k k FREQUENCY (Hz) Figure. Power Supply Rejection vs. Frequency M 9- DIFFERENTIAL INPUT VOLTAGE (µv/div) R L = kω V CN = ±V T A = C OUTPUT SWING (V p-p) A VCL = + % THD R L = kω OUTPUT VOLTAGE (V) Figure 9. Open-Loop Gain Linearity 9- k k FREQUENCY (Hz) Figure. Maximum Output Swing vs. Frequency k 9- Rev. E Page 7 of 6

8 +V S 7 NO LOAD INPUT COMMON-MODE VOLTAGE (V) (REFERRED TO SUPPLY VOLTAGES) SUPPLY CURRENT (PER AMPLIFIER) (µa) 6 4 C C V S ± ± ± ± SUPPLY VOLTAGE (V) Figure. Input Common-Mode Voltage Range vs. Supply Voltage 9-4 ± ± ± ± SUPPLY VOLTAGE (V) Figure 6. Supply Current (per Amplifier) vs. Supply Voltage 9-7 OUTPUT SWING (V p-p) A VCL = + % THD f O = khz IMPEDANCE (Ω) k. A V = +. k k LOAD RESISTANCE (Ω) Figure 4. Maximum Output Swing vs. Load Resistance 9-. k k k FREQUENCY (Hz) Figure 7. Closed-Loop Output Impedance vs. Frequency 9-8 OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES) +V S R L = kω SHORT-CIRCUIT CURRENT (ma) OUTPUT SHORTED TO GROUND T A = C T A = C V S ± ± ± ± SUPPLY VOLTAGE (V) Figure. Output Voltage Swing vs. Supply Voltage TIME FROM OUTPUT SHORT (Minutes) Figure 8. Short-Circuit Current vs. Time at Various Temperatures 9-9 Rev. E Page 8 of 6

9 7 6 A VCL = + V OUT = mv p-p OVERSHOOT (%) 4 k k LOAD CAPACITANCE (pf) Figure 9. Small-Signal Overshoot vs. Load Capacitance 9- Rev. E Page 9 of 6

10 APPLICATIONS INFORMATION Extremely low bias current makes the attractive for use in sample-and-hold amplifiers, peak detectors, and log amplifiers that must operate over a wide temperature range. Balancing input resistances is not necessary with the. High source resistance, even when unbalanced, only minimally degrades the offset voltage and TCVOS. The input pins of the are protected against large differential voltage by back-to-back diodes and current-limiting resistors. Common-mode voltages at the inputs are not restricted and may vary over the full range of the supply voltages used. The requires very little operating headroom about the supply rails and is specified for operation with supplies as low as ± V. Typically, the common-mode range extends to within V of either rail. When using a kω load, the output typically swings to within V of the rails. AC PERFORMANCE The ac characteristics of the are highly stable over its full operating temperature range. Figure shows the unity-gain small signal response. Extremely tolerant of capacitive loading on the output, the displays excellent response even with pf loads (see Figure ). 9 9 % mv µs Figure. Small Signal Transient Response (CLOAD = pf, AVCL = +) 9 % V µs Figure. Large Signal Transient Response (AVCL = +) % mv µs Figure. Small Signal Transient Response (CLOAD = pf, AVCL = +) 9- V+ V OUT IN.kΩ +IN.kΩ Figure. Simplified Schematic Showing One Amplifier V 9- Rev. E Page of 6

11 GUARDING AND SHIELDING To maintain the extremely high input impedances of the, care must be taken in circuit board layout and manufacturing. Board surfaces must be kept scrupulously clean and free of moisture. Conformal coating is recommended to provide a humidity barrier. Even a clean PCB can have pa of leakage currents between adjacent traces; therefore, use guard rings around the inputs. Guard traces are operated at a voltage close to that on the inputs, as shown in Figure 4, so that leakage currents become minimal. In noninverting applications, connect the guard ring to the common-mode voltage at the inverting input. In inverting applications, both inputs remain at ground; therefore, the guard trace should be grounded. Place guard traces on both sides of the circuit board. UNITY-GAIN FOLLOWER /4 + INVERTING AMPLIFIER NONINVERTING AMPLIFIER /4 + PDIP BOTTOM VIEW OPEN-LOOP GAIN LINEARITY The has both an extremely high gain of V/mV typical and constant gain linearity. This enhances the precision of the and provides for very high accuracy in high closed-loop gain applications. Figure illustrates the typical open-loop gain linearity of the. DIFFERENTIAL INPUT VOLTAGE (µv/div) R L = kω V CM = V T A = C OUTPUT VOLTAGE (V) Figure. Open-Loop Gain Linearity /4 + B Figure 4. Guard Ring Layout and Connections A 9- Rev. E Page of 6

12 + APPLICATIONS CIRCUIT PRECISION ABSOLUTE VALUE AMPLIFIER The circuit in Figure 6 is a precision absolute value amplifier with an input impedance of MΩ. The high gain and low TCVOS of the ensure accurate operation with microvolt input signals. In this circuit, the input always appears as a commonmode signal to the op amps. The CMR of the exceeds db, yielding an error of less than ppm. V IN +V C.µF C pf 8 /4 C 4.µF R kω D N448 D N448 R kω R kω 6 /4 7 V < V OUT < V V Figure 6. Precision Absolute Value Amplifier PRECISION CURRENT PUMP Maximum output current of the precision current pump shown in Figure 7 is ± ma. Voltage compliance is ± V with ± V supplies. Output impedance of the current transmitter exceeds MΩ with linearity better than 6 bits. R kω /4 V IN R kω + R4 kω V IN V IN I OUT = = = ma/v R Ω R kω 7 +V 8 /4 4 V R kω Figure 7. Precision Current Pump 6 I OUT ±ma PRECISION POSITIVE PEAK DETECTOR In Figure 8, the CH must be of polystyrene, Teflon, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the. V IN +V.µF N448 6 /4 8 N9 /4 7 kω kω RESET C H kω kω + 4 V.µF Figure 8. Precision Positive Peak Detector SIMPLE BRIDGE CONDITIONING AMPLIFIER + V OUT Figure 9 shows a simple bridge conditioning amplifier using the. The transfer function is V OUT = V REF R RF R R Δ + Δ R The REF4 provides an accurate and stable reference voltage for the bridge. To maintain the highest circuit accuracy, RF should be.% or better with a low temperature coefficient. +V REF4 6 4.V V REF R R +V R 6 8 /4 4 V R + ΔR 7 RF /4 V OUT = V REF ( ) ΔR R + ΔR V OUT R F R Figure 9. Simple Bridge Conditioning Amplifier Using the Rev. E Page of 6

13 NONLINEAR CIRCUITS Due to its low input bias currents, the is an ideal log amplifier in nonlinear circuits, such as the squaring amplifier and square root amplifier circuits shown in Figure 4 and Figure 4. Using the squaring amplifier circuit in Figure 4 as an example, the analysis begins by writing a voltage loop equation across Transistors Q, Q, Q, and Q4. I V TIn I IN S + V T I In I IN S = V T I In I I O S + V T4 I In I All the transistors in the MAT4 are precisely matched and at the same temperature; therefore, the IS and VT terms cancel, giving InIIN = InIO + InIREF = In (IO IREF) Exponentiating both sides of the thick equation lead to I O = ( I ) I IN REF Op amp A forms a current-to-voltage converter which results in VOUT = R IO. Substituting (VIN/R) for IIN and the previous equation for IO yields V IN V OUT R kω = I IN R I REF VIN R Q V+ C A pf 8 /4 4 6 Q 7 I O V V Figure 4. Squaring Amplifier 6 MAT4 8 9 Q C pf R kω A /4 R kω I REF R4 kω 7 4 REF S4 Q4 V OUT 9-4 A similar analysis made for the square root amplifier circuit in Figure 4 leads to its transfer function ( V )( I ) IN REF V = OUT R R In these circuits, IREF is a function of the negative power supply. To maintain accuracy, the negative supply should be well regulated. For applications where very high accuracy is required, a voltage reference can be used to set IREF. An important consideration for the squaring circuit is that a sufficiently large input voltage can force the output beyond the operating range of the output op amp. Resistor R4 can be changed to scale IREF, or R and R can be varied to keep the output voltage within the usable range. V IN R kω C pf I IN V+ 8 /4 4 R kω Q I O R kω 6 MAT4 6 7 Q 8 Q 9 C pf /4 7 R kω V Figure 4. Square Root Amplifier 4 Q4 V I REF R4 kω V OUT Unadjusted accuracy of the square root circuit is better than.% over an input voltage range of mv to V. For a similar input voltage range, the accuracy of the squaring circuit is better than.%. 9-4 Rev. E Page of 6

14 OUTLINE DIMENSIONS.77 (9.69).7 (9.).7 (8.67). (.) MAX. (.8). (.). (.79). (.6).8 (.46).4 (.6) 4. (.4) BSC.7 (.78). (.7).4 (.4) (7.). (6.).4 (6.). (.8) MIN SEATING PLANE. (.) MIN.6 (.) MAX. (.8) GAUGE PLANE. (8.6). (7.87). (7.6).4 (.9) MAX.9 (4.9). (.). (.9).4 (.6). (.).8 (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 4. 4-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-4) Dimensions shown in inches and (millimeters) 766-A. (.44). (.976) (.99) 7.4 (.9) 8.6 (.49). (.97). (.8). (.9) COPLANARITY.7 (.) BSC.6 (.4). (.9).. (.) SEATING PLANE. (.). (.). (.79) 8.7 (.9). (.98) 4.7 (.).4 (.7) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 4. 6-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-6) Dimensions shown in millimeters and (inches) 77-B Rev. E Page 4 of 6

15 ORDERING GUIDE Model Temperature Range Package Description Package Option FP 4 C to +8 C 4-Lead Plastic Dual In-Line Package [PDIP] N-4 FPZ 4 C to +8 C 4-Lead Plastic Dual In-Line Package [PDIP] N-4 GP 4 C to +8 C 4-Lead Plastic Dual In-Line Package [PDIP] N-4 GPZ 4 C to +8 C 4-Lead Plastic Dual In-Line Package [PDIP] N-4 FS 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 FS-REEL 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 FSZ 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 FSZ-REEL 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 GS 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W RW-6 GS-REEL 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 GSZ 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 GSZ-REEL 4 C to +8 C 6-Lead Standard Small Outline Package [SOIC_W] RW-6 Z = RoHS Compliant Part. Rev. E Page of 6

16 NOTES 99 9 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9--/9(E) Rev. E Page 6 of 6