Precision Instrumentation Amplifier AD524

Transcription

1 Precision Instrumentation Amplifier AD54 FEATURES Low noise: 0.3 μv p-p at 0. Hz to 0 Hz Low nonlinearity: 0.003% (G = ) High CMRR: 0 db (G = 000) Low offset voltage: 50 μv Low offset voltage drift: 0.5 μv/ C Gain bandwidth product: 5 MHz Pin programmable gains of, 0, 00, 000 Input protection, power-on/power-off No external components required Internally compensated MIL-STD-883B and chips available 6-lead ceramic DIP and SOIC packages and 0-terminal leadless chip carrier available Available in tape and reel in accordance with EIA-48A standard Standard military drawing also available FUNCTIONAL BLOCK DIAGRAM G = 0 G = 00 G = 000 RG RG PROTECTION 4.44kΩ AD54 404Ω 40Ω V b 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ 0kΩ PROTECTION Figure. SENSE REFERENCE GENERAL DESCRIPTION The AD54 is a precision monolithic instrumentation amplifier designed for data acquisition applications requiring high accuracy under worst-case operating conditions. An outstanding combination of high linearity, high common-mode rejection, low offset voltage drift, and low noise makes the AD54 suitable for use in many data acquisition systems. The AD54 has an output offset voltage drift of less than 5 μv/ C, input offset voltage drift of less than 0.5 μv/ C, CMR above 90 db at unity gain (0 db at G = 000), and maximum nonlinearity of 0.003% at G =. In addition to the outstanding dc specifications, the AD54 also has a 5 khz bandwidth (G = 000). To make it suitable for high speed data acquisition systems, the AD54 has an output slew rate of 5 V/μs and settles in 5 μs to 0.0% for gains of to 00. As a complete amplifier, the AD54 does not require any external components for fixed gains of, 0, 00 and 000. For other gain settings between and 000, only a single resistor is required. The AD54 input is fully protected for both power-on and power-off fault conditions. The AD54 IC instrumentation amplifier is available in four different versions of accuracy and operating temperature range. The economical A grade, the low drift B grade, and lower drift, higher linearity C grade are specified from 5 C to +85 C. The S grade guarantees performance to specification over the extended temperature range 55 C to +5 C. The AD54 is available in a 6-lead ceramic DIP, 6-lead SBDIP, 6-lead SOIC wide packages, and 0-terminal leadless chip carrier. PRODUCT HIGHLIGHTS. The AD54 has guaranteed low offset voltage, offset voltage drift, and low noise for precision high gain applications.. The AD54 is functionally complete with pin programmable gains of, 0, 00, and 000, and single resistor programmable for any gain. 3. Input and output offset nulling terminals are provided for very high precision applications and to minimize offset voltage changes in gain ranging applications. 4. The AD54 is input protected for both power-on and power-off fault conditions. 5. The AD54 offers superior dynamic performance with a gain bandwidth product of 5 MHz, full power response of 75 khz and a settling time of 5 μs to 0.0% of a 0 V step (G = 00). Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

2 VS = ±5 V, RL = kω and TA = +5 C, unless otherwise noted. AD54 All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table. AD54A AD54B GAIN Gain Equation (External Resistor Gain Programming) 40,000 40,000 + ± 0% + ± 0% R G R G Gain Range (Pin Programmable) to 000 to 000 Gain Error G = ±0.05 ±0.03 % G = 0 ±0.5 ±0.5 % G = 00 ±0.5 ±0.35 % G = 000 ±.0 ±.0 % Nonlinearity G = ±0.0 ±0.005 % G = 0, G = 00 ±0.0 ±0.005 % G = 000 ±0.0 ±0.0 % Gain vs. Temperature G = 5 5 ppm/ C G = ppm/ C G = ppm/ C G = ppm/ C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage μv vs. Temperature 0.75 μv/ C Output Offset Voltage 5 3 mv vs. Temperature μv Offset Referred to the Input vs. Supply G = db G = db G = db G = db CURRENT Input Bias Current ±50 ±5 na vs. Temperature ±00 ±00 pa/ C Input Offset Current ±35 ±5 na vs. Temperature ±00 ±00 pa/ C Rev. F Page 3 of 8

3 AD54A AD54B Input Impedance Differential Resistance Ω Differential Capacitance 0 0 pf Common-Mode Resistance Ω Common-Mode Capacitance 0 0 pf Input Voltage Range Maximum Differential Input Linear (VDL) ±0 ±0 V Maximum Common-Mode Linear (VCM) G G V V VD V VD Common-Mode Rejection DC to 60 Hz with kω Source Imbalance V G = db G = db G = db G = db RATING VOUT, RL = kω ±0 ±0 V DYNAMIC RESPONSE Small Signal 3 db G = MHz G = khz G = khz G = khz Slew Rate V/μs Settling Time to 0.0%, 0 V Step G = to μs G = μs NOISE Voltage Noise, khz RTI 7 7 nv/ Hz RTO nv Hz RTI, 0. Hz to 0 Hz G = 5 5 μv p-p G = 0 μv p-p G = 00, μv p-p Current Noise 0. Hz to 0 Hz pa p-p SENSE RIN 0 0 kω ± 0% IIN 5 5 μa Voltage Range ±0 ±0 V Gain to Output % REFERENCE RIN kω ± 0% IIN 5 5 μa Voltage Range ±0 ±0 V Gain to Output % Rev. F Page 4 of 8

4 AD54A AD54B TEMPERATURE RANGE Specified Performance C Storage C POWER SUPPLY Power Supply Range ±6 ±5 ±8 ±6 ±5 ±8 V Quiescent Current ma Does not include effects of external resistor, RG. VOL is the maximum differential input voltage at G = for specified nonlinearity. VDL at the maximum = 0 V/G. VD = actual differential input voltage. Example: G = 0, VD = VCM = V (0/ 0.50 V) = 9.5 VS = ±5 V, RL = kω and TA = +5 C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table. AD54C AD54S GAIN Gain Equation (External Resistor Gain Programming) 40,000 40,000 + ± 0% + ± 0% R G R G Gain Range (Pin Programmable) to 000 to 000 Gain Error G = ±0.0 ±0.05 % G = 0 ±0. ±0.5 % G = 00 ±0.5 ±0.5 % G = 000 ±0.5 ±.0 % Nonlinearity G = ±0.003 ±0.0 % G = 0, G = 00 ±0.003 ±0.0 % G = 000 ±0.0 ±0.0 % Gain vs. Temperature G = 5 5 ppm/ C G = ppm/ C G = ppm/ C G = ppm/ C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage μv vs. Temperature μv/ C Output Offset Voltage mv vs. Temperature 5 50 μv Offset Referred to the Input vs. Supply G = db G = db G = db G = db Rev. F Page 5 of 8

5 AD54C AD54S CURRENT Input Bias Current ±5 ±50 na vs. Temperature ±00 ±00 pa/ C Input Offset Current ±0 ±35 na vs. Temperature ±00 ±00 pa/ C Input Impedance Differential Resistance Ω Differential Capacitance 0 0 pf Common-Mode Resistance Ω Common-Mode Capacitance 0 0 pf Input Voltage Range Maximum Differential Input Linear (VDL) ±0 ±0 V Maximum Common-Mode Linear (VCM) G G V V VD V VD Common-Mode Rejection DC to 60 Hz with kω Source Imbalance V G = db G = db G = db G = db RATING VOUT, RL = kω ±0 ±0 V DYNAMIC RESPONSE Small Signal 3 db G = MHz G = khz G = khz G = khz Slew Rate V/μs Settling Time to 0.0%, 0 V Step G = to μs G = μs NOISE Voltage Noise, khz RTI 7 7 nv/ Hz RTO nv Hz RTI, 0. Hz to 0 Hz G = 5 5 μv p-p G = 0 μv p-p G = 00, μv p-p Current Noise 0. Hz to 0 Hz pa p-p SENSE RIN 0 0 kω ± 0% IIN 5 5 μa Voltage Range ±0 ±0 V Gain to Output % Rev. F Page 6 of 8

6 AD54C AD54S REFERENCE RIN kω ± 0% IIN 5 5 μa Voltage Range 0 0 V Gain to Output % TEMPERATURE RANGE Specified Performance C Storage C POWER SUPPLY Power Supply Range ±6 ±5 ±8 ±6 ±5 ±8 V Quiescent Current ma Does not include effects of external resistor RG. VOL is the maximum differential input voltage at G = for specified nonlinearity. VDL at the maximum = 0 V/G. VD = actual differential input voltage. Example: G = 0, VD = VCM = V (0/ 0.50 V) = 9.5 V. Rev. F Page 7 of 8

7 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Internal Power Dissipation Input Voltage (Either Input Simultaneously) VIN + VS Output Short-Circuit Duration Storage Temperature Range (R) (D, E) Operating Temperature Range AD54A/AD54B/AD54C AD54S Lead Temperature (Soldering, 60 sec) Rating ±8 V 450 mw <36 V Indefinite 65 C to +5 C 65 C to +50 C 5 C to +85 C 55 C to +5 C +300 C Maximum input voltage specification refers to maximum voltage to which either input terminal may be raised with or without device power applied. For example, with ±8 volt supplies maximum, VIN is ±8 V; with zero supply voltage maximum, VIN is ±36 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NULL 4 NULL 5 RG 6 + G = 0 3 G = 00 G = 000 SENSE V S 7 V S 0.03 (.6) CONNECTION DIAGRAMS + RG 3 NULL 4 NULL 5 REFERENCE 6 V S 7 +V S 8 +V S OFFSET NULL RG 4 NULL 5 NC 6 NULL 7 REFERENCE 8 AD54 TOP VIEW (Not to Scale) RG 5 NULL 4 NULL 3 G = 0 G = 00 G = SENSE 9 V S 5 4 OFFSET NULL Figure 3. Ceramic (D) and SOIC (RW-6 and D-6) Packages + NC RG NULL AD54 TOP VIEW (Not to Scale) NC = NO CONNECT V S +V S NC SENSE 7 9 +V S V S OFFSET NULL ESD CAUTION 5 8 SHORT TO RG FOR DESIRED GAIN NULL 7 G = 0 SHORT TO 6 NC RG FOR 5 G = 00 DESIRED GAIN 4 G = 000 OFFSET NULL Figure 4. Leadless Chip Carrier (E) RG 3 4 NULL 5 NULL 6 REFERENCE 0.70 (4.33) PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE D-6 AND RW-6 6-LEAD CERAMIC PACKAGES. Figure. Metallization Photograph Contact factory for latest dimensions; Dimensions shown in inches and (mm) Rev. F Page 8 of 8

8 Table 5. Error Budget Analysis Error Source AD54C Specifications Calculation Effect on Absolute Accuracy at TA = 5 C Effect on Absolute Accuracy at TA = 85 C Effect on Resolution Gain Error ±0.5% ±0.5% = 500 ppm 500 ppm 500 ppm Gain Instability 5 ppm (5 ppm/ C)(60 C) = 500 ppm 500 ppm Gain Nonlinearity ±0.003% ±0.003% = 30 ppm 30 ppm Input Offset Voltage ±50 μv, RTI ±50 μv/0 mv = ±500 ppm 500 ppm 500 ppm Input Offset Voltage Drift ±0.5 μv/ C (±0.5 μv/ C)(60 C) = 30 μv 30 μv/0 mv = 500 ppm 500 ppm Output Offset Voltage ±.0 mv ±.0 mv/0 mv = 000 ppm 000 ppm 000 ppm Output Offset Voltage Drift ±5 μv/ C (±5 μv/ C)(60 C)= 500 μv 750 ppm 500 μv/0 mv = 750 ppm Bias Current-Source Imbalance Error ±5 na (±5 na)(00 Ω ) =.5 μv.5 μv/0 mv = 75 ppm 75 ppm 75 ppm Bias Current-Source Imbalance Drift Offset Current-Source Imbalance Error Offset Current-Source Imbalance Drift Offset Current-Source Resistance-Error Offset Current-Source Resistance-Drift ±00 pa/ C (±00 pa/ C)(00 Ω )(60 C) = 0.6 μv 0.6 μv/0 mv = 30 ppm ±0 na (±0 na)(00 Ω ) = μv μv/0 mv = 50 ppm ±00 pa/ C (00 pa/ C)(00 Ω )(60 C) = 0.6 μv 0.6 μv/0 mv = 30 ppm ±0 na (0 na)(75 Ω ) = 3.5 μv 3.5 μv/0 mv = 87.5 ppm ±00 pa/ C (00 pa/ C)(75 Ω )(60 C) = μv μv/0 mv = 50 ppm 30 ppm 50 ppm 50 ppm 30 ppm 87.5 ppm 87.5 ppm 50 ppm Common Mode Rejection 5 V DC 5 db 5 db =.8 ppm 5 V = 8.8 μv 444 ppm 444 ppm 8.8 μv/0 mv = 444 ppm Noise, RTI (0. Hz to 0 Hz) 0.3 μv p-p 0.3 μv p-p/0 mv = 5 ppm 5 ppm Total Error ppm ppm 45 ppm Output offset voltage and output offset voltage drift are given as RTI figures. Rev. F Page of 8

9 OUTLINE DIMENSIONS (0.3) MIN (.03) MAX PIN 0.00 (5.08) MAX 0.00 (5.08) 0.5 (3.8) (0.58) 0.04 (0.36) (.34) MAX 0.30 (7.87) 0.0 (5.59) (.5) 0.05 (0.38) 0.50 (3.8) MIN (.78) SEATING (.54) PLANE (0.76) BSC 0.30 (8.3) 0.90 (7.37) 0.05 (0.38) (0.0) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Side-Brazed Ceramic Dual In-Line [SBDIP] (D-6) Dimensions shown in inches and (millimeters) (9.09) 0.34 (8.69) SQ 0.00 (.54) (.63) (9.09) MAX SQ (.4) (.37) (.9) REF (.4) (.90) 0.0 (0.8) (0.8) R TYP (.9) REF (.40) (.4) BOTTOM VIEW (5.08) REF 0.00 (.54) REF (3.8) BSC 0.05 (0.38) MIN 0.08 (0.7) 0.0 (0.56) (.7) BSC 45 TYP CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Terminal Ceramic Leadless Chip Carrier [LCC] (E-0) Dimensions shown in inches and (millimeters) 006-A 0.50 (0.434) 0.0 (0.3976) (0.99) 7.40 (0.93) (0.493) 0.00 (0.3937) 0.30 (0.08) 0.0 (0.0039) COPLANARITY.7 (0.0500) BSC.65 (0.043).35 (0.095) (0.00) SEATING PLANE 0.33 (0.030) 0.3 (0.0) 0.0 (0.0079) (0.095) 0.5 (0.0098) 45.7 (0.0500) 0.40 (0.057) COMPLIANT TO JEDEC STANDARDS MS-03- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-6) Dimensions shown in millimeters and (inches) B Rev. F Page 4 of 8

10 ORDERING GUIDE Model Temperature Range Package Description Package Option AD54AD 40 C to +85 C 6-Lead SBDIP D-6 AD54ADZ 40 C to +85 C 6-Lead SBDIP D-6 AD54AE 40 C to +85 C 0-Terminal LCC E-0 AD54AR-6 40 C to +85 C 6-Lead SOIC_W RW-6 AD54AR-6-REEL 40 C to +85 C 6-Lead SOIC_W, 3" Tape and Reel RW-6 AD54AR-6-REEL7 40 C to +85 C 6-Lead SOIC_W, 7" Tape and Reel RW-6 AD54ARZ-6 40 C to +85 C 6-Lead SOIC_W RW-6 AD54ARZ-6-REEL7 40 C to +85 C 6-Lead SOIC_W, 7 Tape and Reel RW-6 AD54BD 40 C to +85 C 6-Lead SBDIP D-6 AD54BDZ 40 C to +85 C 6-Lead SBDIP D-6 AD54BE 40 C to +85 C 0-Terminal LCC E-0 AD54CD 40 C to +85 C 6-Lead SBDIP D-6 AD54CDZ 40 C to +85 C 6-Lead SBDIP D-6 AD54SD 55 C to +5 C 6-Lead SBDIP D-6 AD54SD/883B 55 C to +5 C 6-Lead SBDIP D EA 55 C to +5 C 6-Lead SBDIP D-6 AD54SE/883B 55 C to +5 C 0-Terminal LCC E-0 AD54SCHIPS 55 C to +5 C Die Z = RoHS Compliant Part. Refer to the official DESC drawing for tested specifications. Rev. F Page 5 of 8