Next Generation OP07 Ultralow Offset Voltage Operational Amplifier OP77

Transcription

1 Next Generation OP Ultralow Offset Voltage Operational Amplifier FEATURES Outstanding gain linearity Ultrahigh gain, 5 V/mV min Low VOS over temperature, 55 μv max Excellent TCVOS,. μv/ C max High PSRR, μv/v max Low power consumption, mw max Fits OP, 5,8A/8A, sockets Available in die form PIN CONNECTIONS V OS TRIM 8 V OS TRIM IN V+ +IN OUT V TOP VIEW 5 NC (Not to Scale) NC = NO CONNECT Figure. 8-Pin Hermetic DIP_Q-8 (Z Suffix) - V OS TRIM V OS TRIM 8 V+ IN OUT +IN 5 NC GENERAL DESCRIPTION The significantly advances the state-of-the-art in precision op amps. The outstanding gain of,, or more for the is maintained over the full V output range. This exceptional gain-linearity eliminates incorrectable system nonlinearities common in previous monolithic op amps and provides superior performance in high closed-loop gain applications. Low initial VOS drift and rapid stabilization time, combined with only 5 mw of power consumption, are significant improvements over previous designs. These characteristics, plus the exceptional TCVOS of. μv/ C maximum and the low VOS of 5 μv maximum, eliminates the V (CASE) TOP VIEW (Not to Scale) NC = NO CONNECT Figure. TO-99 (J Suffix) need for VOS adjustment and increases system accuracy over temperature. A PSRR of μv/v ( db) and CMRR of. μv/v maximum virtually eliminate errors caused by power supply drifts and common-mode signals. This combination of outstanding characteristics makes the ideally suited for high resolution instrumentation and other tight error budget systems. - Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: 8.. Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Pin Connections... General Description... Revision History... Electrical Specifications... Wafer Test Limits... Typical Electrical Characteristics... 5 Absolute Maximum Ratings... Thermal Resistance... ESD Caution... Typical Performance Characteristics... Test Circuits... Applications... Precision Current Sinks... Outline Dimensions... 5 Ordering Guide... REVISION HISTORY / Rev. D to Rev. E Removed Figure and Two Subsequent Paragraphs... /9 Rev. C to Rev. D Changes to Figure and Figure... Changes to Table... Removed Endnote and Endnote in Table... Changes to Figure... 9 Changes to Figure and Figure... Changes to Figure 8... Moved Figure 9... / Rev. B to Rev. C Edits to Specifications... Figure Caption Changed... Figure Caption Changed... Edits to Figure... Updated Outline Dimensions... 5 / Rev. A to Rev. B Remove 8-Lead SO PIN Connection Diagrams... Changes to Absolute Maximum Rating... Remove B column from Specifications... Remove B column from Electrical Characteristics..., 5 Remove G column from Wafer Test Limits... Remove G column from Typical Electrical Characteristics Rev. E Page of

3 ELECTRICAL VS = ±5 V, TA = 5 C, unless otherwise noted. Table. E F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE VOS 5 μv LONG-TERM STABILITY VOS/time.. μv/mo INPUT OFFSET CURRENT IOS na INPUT BIAS CURRENT IB na INPUT NOISE VOLTAGE enp-p. Hz to Hz μvp-p INPUT NOISE VOLTAGE DENSITY en fo = Hz nv/ Hz fo = Hz....5 fo = Hz INPUT NOISE CURRENT inp-p. Hz to Hz 5 5 pap-p INPUT NOISE CURRENT DENSITY in fo = Hz pa Hz fo = Hz...5. fo = Hz....8 INPUT RESISTANCE Differential Mode RIN MΩ Common Mode RINCM GΩ INPUT VOLTAGE RANGE IVR ± ± ± ± V COMMON-MODE REJECTION RATIO CMRR VCM = ± V.... μv/v POWER SUPPLY REJECTION RATIO PSRR VS = ± V to ±8 V.... μv/v LARGE-SIGNAL VOLTAGE GAIN AVO RL kω 5, V/mV VO = ± V OUTPUT VOLTAGE SWING VO RL kω ±.5 ±. ±.5 ±. V RL kω ±.5 ±. ±.5 ±. RL kω ±. ±.5 ±. ±.5 SLEW RATE SR RL kω.... V/μs CLOSED-LOOP BANDWIDTH BW AVCL MHz OPEN-LOOP OUTPUT RESISTANCE RO Ω POWER CONSUMPTION Pd VS = ±5 V, no load 5 5 mw VS = ± V, no load OFFSET ADJUSTMENT RANGE Rp = kn ± ± mv Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first days of operation. Excluding the initial hour of operation, changes in VOS during the first operating days are typically.5 μv. Sample tested. Guaranteed by design. Rev. E Page of

4 @ VS = ±5 V, 5 C TA +85 C for FJ and E/F, unless otherwise noted. Table. E F Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE VOS 5 μv AVERAGE INPUT OFFSET VOLTAGE DRIFT TCVOS.... μv/ C INPUT OFFSET CURRENT IOS na AVERAGE INPUT OFFSET CURRENT DRIFT TCIOS pa/ C INPUT BIAS CURRENT IB na AVERAGE INPUT BIAS CURRENT DRIFT TCIB 8 5 pa/ C INPUT VOLTAGE RANGE IVR ±. ±.5 ±. ±.5 V COMMON-MODE REJECTION RATIO CMRR VCM = ± V.... pv/v POWER SUPPLY REJECTION RATIO PSRR VS = ± V to ±8 V μv/v LARGE-SIGNAL VOLTAGE GAIN AVO RL kω V/mV VO = ± V OUTPUT VOLTAGE SWING VO RL kω ± ±. ± ±. V POWER CONSUMPTION Pd VS = ±5 V, no load 5 5 mw E: TCVOS is % tested on J and Z packages. Guaranteed by end-point limits. WAFER TEST VS = ±5 V, TA = 5 C, for NBC devices, unless otherwise noted. Table. Parameter Symbol Conditions NBC Limit Unit INPUT OFFSET VOLTAGE VOS μv max INPUT OFFSET CURRENT IOS. na max INPUT BIAS CURRENT IB ± na max INPUT RESISTANCE Differential Mode RIN MΩ min INPUT VOLTAGE RANGE IVR ± V min COMMON-MODE REJECTION RATIO CMRR VCM = ± V μv/v max POWER SUPPLY REJECTION RATIO PSRR VS = ± V to ±8 V μv/v max OUTPUT VOLTAGE SWING VO RL = kω ±.5 V min RL = kω ±.5 RL = kω ±. LARGE-SIGNAL VOLTAGE GAIN AVO RL = kω V/mV min VO = ± V DIFFERENTIAL INPUT VOLTAGE ± V max POWER CONSUMPTION Pd VO = V mw max Rev. E Page of

5 TYPICAL ELECTRICAL VS = ±5 V, TA = 5 C, unless otherwise noted. Table. Parameter Symbol Conditions NBC Limit Unit AVERAGE INPUT OFFSET VOLTAGE DRIFT TCVOS RS = 5 Ω. μv/ C NULLED INPUT OFFSET VOLTAGE DRIFT TCVOSn RS = 5 Ω, RP = kω. μv/ C AVERAGE INPUT OFFSET CURRENT DRIFT TCIOS.5 pa/ C SLEW RATE SR RL kω. V/μs BANDWIDTH BW AVCL +. MHz Rev. E Page 5 of

6 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage ± V Differential Input Voltage ± V Input Voltage ± V Output Short-Circuit Duration Indefinite Storage Temperature Range 5 C to +5 C Operating Temperature Range 5 C to +85 C Junction Temperature (TJ) 5 C to +5 C Lead Temperature (Soldering, sec) C Absolute Maximum Ratings apply to both dice and packaged parts, unless otherwise noted. For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table. Package Type θja θjc Unit 8-Pin TO-99 H-8 (J Suffix) 5 8 C/W 8-Lead Hermetic CERDIP Q-8 (Z Suffix) 8 C/W θja is specified for worst-case mounting conditions, i.e., θja is specified for a device in socket for the TO-99 and CERDIP packages. ESD CAUTION Rev. E Page of

7 TYPICAL PERFORMANCE CHARACTERISTICS INPUT VOLTAGE (µv) (NULLED TO V OUT = V) V S = ±5V T A = 5 C R L = kω CHANGE IN OFFSET VOLTAGE (µv) J, Z PACKAGES +.µv/ C.µV/ C S.D. MEAN 5 5 OUTPUT VOLTAGE (V) Figure. Gain Linearity (Input Voltage vs. Output Voltage) TEMPERATURE ( C) Figure. Untrimmed Offset Voltage vs. Temperature - OPEN-LOOP GAIN (V/µV) V S = ±5V CHANGE IN INPUT OFFSET VOLTAGE (µv) V S = ±5V T A = 5 C TEMPERATURE ( C) Figure. Open-Loop Gain vs. Temperature TIME AFTER POWER SUPPLY TURN-ON (Minutes) Figure. Warm-Up Drift -8 T A = 5 C R L = kω 5 V S = ±5V OPEN-LOOP GAIN (V/µV) 8 ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µv) 5 5 DEVICE IMMERSED IN C OIL BATH ( UNITS) AVERAGE MAXIMUM MIMIMUM ±5 ± ±5 ± POWER SUPPLY VOLTAGE (V) Figure 5. Open-Loop Gain vs. Power Supply Voltage - 5 TIME (Seconds) Figure 8. Offset Voltage Change Due to Thermal Shock -9 Rev. E Page of

8 8 V S = ±5V T A = 5 C T A = 5 C CLOSED-LOOP GAIN (db) PSRR (db) 9 8 k k k M M FREQUENCY (Hz) Figure 9. Closed-Loop Response for Various Gain Configurations -. k k FREQUENCY (Hz) Figure. PSRR vs. Frequency - V S = ±5V T A = 5 C V S = ±5V OPEN-LOOP GAIN (db) PHASE (Degrees) INPUT BIAS CURRENT (na) 8.. k k k M FREQUENCY (Hz) Figure. Open-Loop Gain/Phase Response TEMPERATURE ( C) Figure. Input Bias Current vs. Temperature - 5 T A = 5 C. V S = ±5V CMMR (db) 9 INPUT OFFSET CURRENT (na) k k k FREQUENCY (Hz) Figure. CMRR vs. Frequency TEMPERATURE ( C) Figure. Input Offset Current vs. Temperature -5 Rev. E Page 8 of

9 V S = ±5V T A = 5 C T A = 5 C RMS NOISE (mv) POWER CONSUMPTION (mw). k k k FREQUENCY (Hz) Figure 5. Input Wideband Noise vs. Bandwidth (. Hz to Frequency Indicated) - TOTAL SUPPLY VOLTAGE V+ TO V (V) Figure 8. Power Consumption vs. Power Supply -9 INPUT NOISE VOLTAGE (nv/ Hz) k RS = RS = kω THERMAL NOISE OF SOURCE V S = ±5V T A = 5 C R S = EXCLUDED RESISTORS INCLUDED k FREQUENCY (Hz) Figure. Total Input Noise Voltage vs. Frequency - MAXIMUM OUTPUT (V) 5 5 V S = ±5V T A = 5 C = ±mv POSITIVE SWING NEGATIVE SWING k k LOAD RESISTANCE TO GROUND (Ω) Figure 9. Maximum Output Voltage vs. Load Resistance - PEAK-TO-PEAK AMPLITUDE (V) 8 8 V S = ±5V T A = 5 C OUTPUT SHORT-CIRCUIT CURRENT (ma) 5 5 V S = ±5V T A = 5 C k k k M FREQUENCY (Hz) Figure. Maximum Output Swing vs. Frequency -8 5 TIME FROM OUTPUT BEING SHORTENED (Minutes) Figure. Output Short-Circuit Current vs. Time - Rev. E Page 9 of

10 TEST CIRCUITS 5Ω kω V O V OS = V O Figure. Typical Offset Voltage Test Circuit - kω = ±V MΩ Ω kω R L V X TYPICAL PRECISION OP AMP V Y V V +V V X Ω Ω.5MΩ V+.kΩ V V O INPUT REFERRED NOISE = 5, OUTPUT.µF ( Hz FILTER) Figure. Typical Low-Frequency Noise Test Circuit INPUT + 8 V kω V+ OUTPUT Figure. Optional Offset Nulling Circuit - - A VO 5V/mV R L = kω NOTES. GAIN NOT CONSISTANT. CAUSES NONLINEAR ERRORS.. A VO SPEC IS ONLY PART OF THE SOLUTION.. CHECK SPECIFICATION TABLE AND TABLE FOR PERFORMANCE. Figure 5. Open-Loop Gain Linearity Actual open-loop voltage gain can vary greatly at various output voltages. All automated testers use endpoint testing and therefore only show the average gain. This causes errors in high closedloop gain circuits. Because this is difficult for manufacturers to test, users should make their own evaluations. This simple test circuit makes it easy. An ideal op amp would show a horizontal scope trace. V V +V V Y V X - kω +8V kω * + µf Ω kω Ω Figure. Output Gain Linearity Trace This is the output gain linearity trace for the new. The output trace is virtually horizontal at all points, assuring extremely high gain accuracy. The average open-loop gain is truly impressive approximately,,. - * NOTES * PER BOARD + µf 8V Figure. Burn-In Circuit -5 Rev. E Page of

11 APPLICATIONS R kω R kω R MΩ +5V E R MΩ 5V Figure. Precision High-Gain Differential Amplifier The high gain, gain linearity, CMRR, and low TCVOS of the make it possible to obtain performance not previously available in single-stage, very high-gain amplifier applications. R R For best CMR, must equal. In this example, with a R R mv differential signal, the maximum errors are as listed in Table. Table. Maximum Errors Type Amount Common-Mode Voltage.%/V Gain Linearity, Worst Case.% TCVOS.%/ C TCIOS.8%/ C -8 R R R R +5V 5V N N9 I OUT = ( R R R5) GIVEN R = R + R5, R = R Figure. ma Current Source R5 I OUT < ma These current sources can supply both positive and negative current into a grounded load. Note that R R5 + R Z O = R5 + R R R R And that for ZO to be infinite R 5 + R R must = R R - R F µf +5V INPUT R S Ω C LOAD OUTPUT 5V Figure 8. Isolating Large Capacitive Loads This circuit reduces maximum slew rate but allows driving capacitive loads of any size without instability. Because the boon resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open-loop gain of the. -9 R kω R kω R kω R 99Ω I OUT < 5mA R5 Ω Figure 9. Basic Current Source - Rev. E Page of

12 PRECISION CURRENT SINKS Ω V+ R L I O IRF5 R Ω W Figure. Positive Current Sink I O = R > V FULL SCALE OF V. I O = A/V - Ω R L R IRF5 I O V Figure. Positive Current Source I O = R > V The simple high-current sinks, shown Figure and Figure, require the load to float between the power supply and the sink. In these circuits, the high gain, high CMRR, and low TCVOS of the ensure high accuracy. The high gain and low TCVOS ensure accurate operation with inputs from microvolts to volts. In Figure, the signal always appears as a common-mode signal to the op amps. The EZ CMRR of μv/v ensures errors of less than ppm. - kω kω +5V +5V E 5V C pf D N8 N9 D R kω E 5V Figure. Precision Absolute Value Amplifier V OUT < V OUT < V -5 5V + µf REF- V O REF- V O REF- V O Ω V OUT Ω Ω Figure. Low Noise Precision Reference - Rev. E Page of

13 Figure relies upon low TCVOS of the and noise combined with very high CMRR to provide precision buffering of the averaged REF- voltage outputs. In Figure 5, CH must be of polystyrene, Teflon*, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the AD8. *Teflon is a registered trademark of the Dupont Company kω +5V N8 +5V kω N9 C H kω AD8 V OUT 5V RESET 5V Figure 5. Precision Positive Peak Detector - Rev. E Page of

14 C C +5V V TH R S kω R kω +5V R F kω D N8 V OUT V O 5 TRIM REF- TEMP GND R a 5kΩ.5kΩ R b R c V OUT 5V Figure. Precision Threshold Detector/Amplifier When VIN < VTH, amplifier output swings negative, reversing the biasing diode D. VO = VTH if RL= when VIN > VTH, the loop closes, V V + + R ( ) F V IN VTH R O = TH S CC is selected to smooth the response of the loop. -8 R bp Table 8. Resistor Values 5V Figure. Precision Temperature Sensor TCVOUT Slope (S) mv/ C mv/ C mv/ F Temperature Range Output Voltage Range 55 C to +5 C.55 V to +.5 V C to +5 C 5.5 V to +.5V F to +5 C. V to +.5V Zero-Scale C C F Ra (±% Resistor) 9.9 kω 5 kω.5 kω Rb (±% Resistor).5 kω.8 kω. kω Rbp (Potentiometer) Ω 5 Ω Ω Rc (±% Resistor) 5. kω 8.5 kω 8.5 kω V+ RA RA (OPTIONAL NULL) 8 RB RB C R Q9 Q9 Q NONINVERTING INPUT INVERTING INPUT R R Q5 Q Q Q Q Q Q Q Q Q8 Q Q Q Q Q5 C R5 Q Q C Q Q Q Q5 R9 R Q Q8 OUTPUT V RA AND RB ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY. Q R R8 - Figure 8. Simplified Schematic Rev. E Page of

15 OUTLINE DIMENSIONS.5 (.) MIN.55 (.) MAX 8 5. (.8). (5.59). (.5) BSC. (5.8) MAX.5 (.9) MAX. (.5).5 (.8). (8.).9 (.). (5.8).5 (.8). (.58). (.). (.8). (.).5 (.8) MIN SEATING PLANE 5.5 (.8).8 (.) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 9. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters). (9.).5 (8.5).5 (8.5).5 (.5).85 (.).5 (.9) REFERENCE PLANE.5 (.) MIN.5 (.5) MIN.5 (.) MAX. (5.8) BSC. (.5) BSC 8..9 (.8) (.5). (.) BSC. (.) MAX. (.8). (.5).8 (.). (.). (.). (.5) 5 BSC BASE & SEATING PLANE 5. (.). (.5).5 (.). (.9) COMPLIANT TO JEDEC STANDARDS MO--AK CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Pin Metal Header [TO-99] (H-8) Dimensions shown in inches and (millimeters) -A Rev. E Page 5 of

16 ORDERING GUIDE Model Temperature Range Package Description Package Option FJ 5 C to +85 C 8-Pin Metal Header [TO-99] H-8 (J Suffix) FJZ 5 C to +85 C 8-Pin Metal Header [TO-99] H-8 (J Suffix) EZ 5 C to +85 C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 (Z Suffix) FZ 5 C to +85 C 8-Lead Ceramic Dual In-Line Package [CERDIP] Q-8 (Z Suffix) NBC Die Z = RoHS Compliant Part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D--/(E) Rev. E Page of