Ultraprecision Operational Amplifier OP177

Transcription

1 Ultraprecision Operational Amplifier FEATURES Ultralow offset voltage TA = 5 C, 5 μv maximum Outstanding offset voltage drift. μv/ C maximum Excellent open-loop gain and gain linearity V/μV typical CMRR: db minimum PSRR: 5 db minimum Low supply current. ma maximum Fits industry-standard precision op amp sockets GENERAL DESCRIPTION The features one of the highest precision performance of any op amp currently available. Offset voltage of the is only 5 μv maximum at room temperature. The ultralow VOS of the combines with its exceptional offset voltage drift (TCVOS) of. μv/ C maximum to eliminate the need for external VOS adjustment and increases system accuracy over temperature. The open-loop gain of V/μV is maintained over the full ± V output range. CMRR of db minimum, PSRR of db minimum, and maximum supply current of ma are just a few examples of the excellent performance of this PIN CONFIGURATION V OS TRIM IN IN V TOP VIEW (Not to Scale) 8 V OS TRIM 7 V OUT 5 NC NC = NO CONNECT Figure. 8-Lead PDIP (P-Suffix), 8-Lead SOIC (S-Suffix) operational amplifier. The combination of outstanding specifications of the ensures accurate performance in high closed-loop gain applications. This low noise, bipolar input op amp is also a cost effective alternative to chopper-stabilized amplifiers. The provides chopper-type performance without the usual problems of high noise, low frequency chopper spikes, large physical size, limited common-mode input voltage range, and bulky external storage capacitors. The is offered in the C to 85 C extended industrial temperature ranges. This product is available in 8-lead PDIP, as well as the space saving 8-lead SOIC. 89- FUNCTIONAL BLOCK DIAGRAM V R A * (OPTIONAL NULL) R B * C R7 R A R B B Q 9 Q 9 Q NONINVERTING INPUT INVERTING INPUT R R Q 5 Q Q Q 7 Q Q Q Q Q Q 8 Q Q Q 7 Q Q 5 Q Q C C R 5 Q Q 7 Q Q 5 Q 8 R 9 Q R OUTPUT Q R R 8 V *R A AND R B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY. 89- Figure. Simplified Schematic Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Pin Configuration... General Description... Functional Block Diagram... Revision History... Specifications... Electrical Characteristics... Test Circuits... Absolute Maximum Ratings... 5 Thermal Resistance... 5 ESD Caution... 5 Typical Performance Characteristics... Applications Information...9 Gain Linearity...9 Thermocouple Amplifier with Cold-Junction Compensation... 9 Precision High Gain Differential Amplifier... Isolating Large Capacitive Loads... Bilateral Current Source... Precision Absolute Value Amplifier... Precision Positive Peak Detector... Precision Threshold Detector/Amplifier... Outline Dimensions... Ordering Guide... REVISION HISTORY /9 Rev. E to Rev. F Added Figure, Renumbered Sequentially... 8 Updated Outline Dimensions... 5/ Rev. D to Rev. E Changes to Figure... Change to Specifications Table... Changes to Specifications Table... Changes to Table... 5 Changes to Figure and Figure... 9 Changes to Figure... Updated the Ordering Guide... / Rev. C to Rev. D Change to Pin Configuration Caption... Changes to Features... Change to Table... Change to Figure... Changes to Figure and Figure... Changes to Figure through Figure Changes to Figure 8 through Figure... 8 Change to Figure 7... Changes to Figure and Figure... Updated Outline Dimensions... Changes to Ordering Guide... /5 Rev. B to Rev. C Edits to Features... Edits to General Description... Edits to Pin Connections... Edits to Electrical Characteristics..., Global deletion of references to E...,, Edits to Absolute Maximum Ratings... 5 Edits to Package Type... 5 Edits to Ordering Guide... 5 Edit to Outline Dimensions... /95 Rev. : Initial Version Rev. F Page of

3 SPECIFICATIONS ELECTRICAL VS = ±5 V, TA = 5 C, unless otherwise noted. Table. F G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE VOS 5 μv LONG-TERM INPUT OFFSET Voltage Stability ΔVOS/time.. μv/mo INPUT OFFSET CURRENT IOS na INPUT BIAS CURRENT IB na INPUT NOISE VOLTAGE en fo = Hz to Hz nv rms INPUT NOISE CURRENT in fo = Hz to Hz 8 8 pa rms INPUT RESISTANCE Differential Mode RIN MΩ INPUT RESISTANCE COMMON MODE RINCM GΩ INPUT VOLTAGE RANGE IVR ± ± ± ± V COMMON-MODE REJECTION RATIO CMRR VCM = ± V 5 db POWER SUPPLY REJECTION RATIO PSRR VS = ± V to ±8 V 5 5 db LARGE SIGNAL VOLTAGE GAIN AVO RL kω, VO = ± V 5 5, V/mV OUTPUT VOLTAGE SWING VO RL kω ±.5 ±. ±.5 ±. V RL kω ±.5 ±. ±.5 ±. V RL kω ±. ±.5 ±. ±.5 V SLEW RATE SR RL kω.... V/μs CLOSED-LOOP BANDWIDTH BW AVCL =.... MHz OPEN-LOOP OUTPUT RESISTANCE RO Ω POWER CONSUMPTION PD VS = ±5 V, no load 5 5 mw VS = ± V, no load mw SUPPLY CURRENT ISY VS = ±5 V, no load.. ma OFFSET ADJUSTMENT RANGE RP = kω ± ± mv Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first days of operation. Excluding the initial hour of operation, changes in VOS during the first operating days are typically less than. μv. Sample tested. Guaranteed by design. Guaranteed by CMRR test condition. 5 To ensure high open-loop gain throughout the ± V output range, AVO is tested at V VO V, V VO V, and V VO V. Rev. F Page of

4 @ VS = ±5 V, C TA 85 C, unless otherwise noted. Table. F G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT Input Offset Voltage VOS 5 μv Average Input Offset Voltage Drift TCVOS...7. μv/ C Input Offset Current IOS na Average Input Offset Current Drift TCIOS pa/ C Input Bias Current IB... ± na Average Input Bias Current Drift TCIB 8 5 pa/ C Input Voltage Range IVR ± ±.5 ± ±.5 V COMMON-MODE REJECTION RATIO CMRR VCM = ± V db POWER SUPPLY REJECTION RATIO PSRR VS = ± V to ±8 V 5 db LARGE-SIGNAL VOLTAGE GAIN AVO RL kω, VO = ± V V/mV OUTPUT VOLTAGE SWING VO RL kω ± ± ± ± V POWER CONSUMPTION PD VS = ±5 V, no load mw SUPPLY CURRENT ISY VS = ±5 V, no load.5.5 ma TCVOS is sample tested. Guaranteed by endpoint limits. Guaranteed by CMRR test condition. To ensure high open-loop gain throughout the ± V output range, AVO is tested at V VO V, V VO V, and V VO V. TEST CIRCUITS kω 5Ω V OS = V O V O Figure. Typical Offset Voltage Test Circuit 89- kω V INPUT V OUTPUT V OS TRIM RANGE IS TYPICALLY ±.mv Figure. Optional Offset Nulling Circuit 89- kω V PINOUTS SHOWN FOR P AND Z PACKAGES V Figure 5. Burn-In Circuit 89-5 Rev. F Page of

5 ABSOLUTE MAXIMUM RATINGS Table. Parameter Ratings Supply Voltage ± V Internal Power Dissipation 5 mw Differential Input Voltage ± V Input Voltage ± V Output Short-Circuit Duration Indefinite Storage Temperature Range 5 C to 5 C Operating Temperature Range C to 85 C Lead Temperature (Soldering, sec) C DICE Junction Temperature (TJ) 5 C to 5 C For supply voltages less than ± V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for worst-case mounting conditions, that is, θja is specified for device in socket for PDIP; θja is specified for device soldered to printed circuit board for SOIC package. Table. Thermal Resistance Package Type θja θjc Unit 8-Lead PDIP (P-Suffix) C/W 8-Lead SOIC (S-Suffix) 58 C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F Page 5 of

6 TYPICAL PERFORMANCE CHARACTERISTICS INPUT VOLTAGE (µv) (NULLED TO V OUT = V) V S = ±5V R L = kω 5 5 OUTPUT VOLTAGE (V) Figure. Gain Linearity (Input Voltage vs. Output Voltage) 89- ABSOLUTE CHANGE IN INPUT OFFSET VOLTAGE (µv) DEVICE IMMERSED IN 7 OIL BATH ( UNITS) V S = ±5V 5 7 TIME (Seconds) Figure 9. Offset Voltage Change Due to Thermal Shock V S = ±5V POWER CONSUMPTION (mw) OPEN-LOOP GAIN (V/µV) 5 5 TOTAL SUPPLY VOLTAGE, V TO V (V) Figure 7. Power Consumption vs. Power Supply TEMPERATURE ( C) Figure. Open-Loop Gain vs. Temperature 89-5 R L = kω V OS (µv) LOT A LOT B LOT C LOT D OPEN-LOOP GAIN (V/µV) TIME (Seconds) Figure 8. Warm-Up VOS Drift (Normalized) Z Package 89-8 ±5 ± ±5 POWER SUPPLY VOLTAGE (V) Figure. Open-Loop Gain vs. Power Supply Voltage 89- ± Rev. F Page of

7 V S = ±5V V S = ±5V INPUT BIAS CURRENT (na) OPEN-LOOP GAIN (db) TEMPERATURE ( C) Figure. Input Bias Current vs. Temperature k k k FREQUENCY (Hz) Figure 5. Open-Loop Frequency Response 89-5 M. V S = ±5V 5 INPUT OFFSET CURRENT (na).5..5 CMRR (db) 5 5 TEMPERATURE ( C) Figure. Input Offset Current vs. Temperature k k k FREQUENCY (Hz) Figure. CMRR vs. Frequency 89-8 V S = ±5V CLOSED-LOOP GAIN (db) PSRR (db) 9 8 k k k M M k k 89-7 FREQUENCY (Hz) Figure. Closed-Loop Response for Various Gain Configurations FREQUENCY (Hz) Figure 7. PSRR vs. Frequency Rev. F Page 7 of

8 INPUT NOISE VOLTAGE (nv Hz) V S = ±5V R S = R S = R S = kω THERMAL NOISE OF SOURCE RESISTORS INCLUDED EXCLUDED k FREQUENCY (Hz) Figure 8. Total Input Noise Voltage vs. Frequency 89-8 MAXIMUM OUTPUT (V) 5 5 V S = 5V V IN = ±mv POSITIVE SWING NEGATIVE SWING k k LOAD RESISTANCE TO GROUND (Ω) Figure. Maximum Output Voltage vs. Load Resistance 89- RMS NOISE (µv) V S = ±5V. k k k BANDWIDTH (Hz) Figure 9. Input Wideband Noise vs. Bandwidth (. Hz to Frequency Indicated) 89-9 OUTPUT SHORT-CIRCUIT CURRENT (ma) 5 5 I SC I SC V S = ±5V 5 TIME FROM OUTPUT BEING SHORTED (Minutes) Figure. Output Short-Circuit Current vs. Time 89- PEAK-TO-PEAK AMPLITUDE (V) 8 8 k V S = ±5V k k M FREQUENCY (Hz) 89- I B (na) V S = ±5V I B (na) I B (na) I B (na) I B (na) I B (na) I B (na) V CM (V) 89- Figure. Maximum Output Swing vs. Frequency Figure. Input Bias (IB) vs. Common-Mode Voltage (VCM) Rev. F Page 8 of

9 APPLICATIONS INFORMATION GAIN LINEARITY The actual open-loop gain of most monolithic op amps varies at different output voltages. This nonlinearity causes errors in high closed-loop gain circuits. It is important to know that the manufacturer s AVO specification is only a part of the solution because all automated testers use endpoint testing and, therefore, show only the average gain. For example, Figure shows a typical precision op amp with a respectable open-loop gain of 5 V/mV. However, the gain is not constant through the output voltage range, causing nonlinear errors. An ideal op amp shows a horizontal scope trace. Figure 5 shows the output gain linearity trace with its truly impressive average AVO of, V/mV. The output trace is virtually horizontal at all points, assuring extremely high gain accuracy. Analog Devices also performs additional testing to ensure consistent high open-loop gain at various output voltages. Figure is a simple open-loop gain test circuit. V X THERMOCOUPLE AMPLIFIER WITH COLD- JUNCTION COMPENSATION An example of a precision circuit is a thermocouple amplifier that must accurately amplify very low level signals without introducing linearity and offset errors to the circuit. In this circuit, an S-type thermocouple with a Seebeck coefficient of. μv/ C produces. mv of output voltage at a temperature of C. The amplifier gain is set at 97., thus, it produces an output voltage of. V. Extended temperature ranges beyond 5 C are accomplished by reducing the amplifier gain. The circuit uses a low cost diode to sense the temperature at the terminating junctions and, in turn, compensates for any ambient temperature change. The, with its high openloop gain plus low offset voltage and drift, combines to yield a precise temperature sensing circuit. Circuit values for other thermocouple types are listed in Table 5. Table 5. Thermocouple Type Seebeck Coefficient R R R7 R9 K 9. μv/ C Ω 5.7 kω kω 9 kω J 5. μv/ C Ω. kω 8. kω kω S. μv/ C Ω.5 kω 9 kω.7 MΩ V V V 5V.V REF A VO 5V/mV R L = kω 89-.µF R 7kΩ % R 7 9kΩ % R 9.7MΩ.5% Figure. Typical Precision Op Amp µf 5V V Y V V V A VO V/mV R L = kω Figure 5. Output Gain Linearity Trace V Y V X 89- TYPES ISOTHERMAL COLD- JUNCTIONS ISOTHERMAL BLOCK COLD-JUNCTION COMPENSATION R.5kΩ % COPPER COPPER R Ω % R 8.kΩ.5% R 5 Ω (ZERO ADJUST- MENT) R 5Ω % ANALOG GROUND 5V µf µf µf ANALOG GROUND Figure 7. Thermocouple Amplifier with Cold Junction Compensation V OUT 89- kω kω V IN = ±V MΩ Ω R L V X Figure. Open-Loop Gain Linearity Test Circuit 89-5 Rev. F Page 9 of

10 PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER The high gain, gain linearity, CMRR, and low TCVOS of the make it possible to obtain performance not previously available in single stage, very high gain amplifier applications. See Figure 8. R R For best CMR, must equal R R In this example, with a mv differential signal, the maximum errors are listed in Table. R kω R kω R MΩ 5V 5V R MΩ 7 Figure 8. Precision High Gain Differential Amplifier Table. High Gain Differential Amp Performance Type Amount Common-Mode Voltage.%/V Gain Linearity, Worst Case.% TCVOS.%/ C TCIOS.8%/ C 89-7 ISOLATING LARGE CAPACITIVE LOADS The circuit shown in Figure 9 reduces maximum slew rate but allows driving capacitive loads of any size without instability. Because the Ω resistor is inside the feedback loop, its effect on output impedance is reduced to insignificance by the high open loop gain of the. INPUT R S pf 5V R F 7 5V Ω Figure 9. Isolating Capacitive Loads BILATERAL CURRENT SOURCE C LOAD OUTPUT The current sources shown in Figure supply both positive and negative currents into a grounded load. Note that Z O = R R5 R R5 R R R R and that for ZO to be infinite R5 R must = R R R 89-8 PRECISION ABSOLUTE VALUE AMPLIFIER The high gain and low TCVOS assure accurate operation with inputs from microvolts to volts. In this circuit, the signal always appears as a common-mode signal to the op amps (for details, see Figure ). Rev. F Page of

11 BASIC CURRENT SOURCE ma CURRENT SOURCE R kω R 5V R kω V IN R kω R 99Ω R 5 Ω I OUT 5mA V IN R R R 5Ω N N97 5V R 5 I OUT ma Figure. Bilateral Current Source I OUT = V IN R R R 5 GIVEN R = R R 5, R = R 89-9 kω kω 5V V IN 5V 7 C pf D N8 N9 R kω 7 V OUT < V OUT < V 5V 5V Figure. Precision Absolute Value Amplifier 89- kω 5V N8 5V 7 NC N9 kω V kω IN C H 7 AD8 V OUT 5V 5V RESET kω Figure. Precision Positive Peak Detector 89- Rev. F Page of

12 PRECISION POSITIVE PEAK DETECTOR In Figure, CH must be polystyrene, Teflon, or polyethylene to minimize dielectric absorption and leakage. The droop rate is determined by the size of CH and the bias current of the AD8. PRECISION THRESHOLD DETECTOR/AMPLIFIER In Figure, when VIN < VTH, amplifier output swings negative, reverse biasing diode D. VOUT = VTH if RL =. When VIN VTH, the loop closes. R VOUT = VTH S ( V ) F IN VTH R V TH V IN R S kω R kω 5V 7 5V C C R F kω D N8 Figure. Precision Threshold Detector/Amplifier V OUT 89- CC is selected to smooth the response of the loop. Rev. F Page of

13 OUTLINE DIMENSIONS. (.).5 (9.7).55 (9.) PIN. (5.) MAX.5 (.8). (.).5 (.9). (.5).8 (.). (.) 8. (.5) BSC.7 (.78). (.5).5 (.) 5.8 (7.).5 (.5). (.).5 (.8) MIN SEATING PLANE.5 (.) MIN. (.5) MAX.5 (.8) GAUGE PLANE.5 (8.). (7.87). (7.). (.9) MAX.95 (.95). (.).5 (.9). (.). (.5).8 (.) COMPLIANT TO JEDEC STANDARDS MS--BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure. 8-Lead Plastic Dual In-Line Package (PDIP) P-Suffix (N-8) Dimensions show in inches and (millimeters) 5. (.98).8 (.89). (.57).8 (.97) 8 5. (.) 5.8 (.8).5 (.98). (.) COPLANARITY..7 (.5) BSC SEATING PLANE.75 (.88).5 (.5).5 (.). (.).5 (.98).7 (.7) 8.5 (.9).5 (.99) 5.7 (.5). (.57) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 5. 8-Lead Standard Small Outline Package (SOIC_N) S-Suffix (R-8) Dimensions shown in millimeters and( inches) Rev. F Page of

14 ORDERING GUIDE Model Temperature Range Package Description Package Option FP C to 85 C 8-Lead PDIP P-Suffix (N-8) FPZ C to 85 C 8-Lead PDIP P-Suffix (N-8) GP C to 85 C 8-Lead PDIP P-Suffix (N-8) GPZ C to 85 C 8-Lead PDIP P-Suffix (N-8) FS C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FS-REEL C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FS-REEL7 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FSZ C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FSZ-REEL C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FSZ-REEL7 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GS C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GS-REEL C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GS-REEL7 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GSZ C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GSZ-REEL C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GSZ-REEL7 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) Z = RoHS Compliant Part. Rev. F Page of

15 NOTES Rev. F Page 5 of

16 NOTES 9959 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D89--/9(F) Rev. F Page of