Dual/Quad Low Power, High Speed JFET Operational Amplifiers OP282/OP482

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1 Dual/Quad Low Power, High Speed JFET Operational Amplifiers OP282/OP482 FEATURES High slew rate: 9 V/μs Wide bandwidth: 4 MHz Low supply current: 2 μa/amplifier maximum Low offset voltage: 3 mv maximum Low bias current: pa maximum Fast settling time Common-mode range includes V+ Unity-gain stable APPLICATIONS Active filters Fast amplifiers Integrators Supply current monitoring GENERAL DESCRIPTION The OP282/OP482 dual and quad operational amplifiers feature excellent speed at exceptionally low supply currents. The slew rate is typically 9 V/μs with a supply current under 2 μa per amplifier. These unity-gain stable amplifiers have a typical gain bandwidth of 4 MHz. The JFET input stage of the OP282/OP482 ensures bias current is typically a few picoamps and below pa over the full temperature range. Offset voltage is under 3 mv for the dual and under 4 mv for the quad. With a wide output swing, within. V of each supply, low power consumption, and high slew rate, the OP282/OP482 are ideal for battery-powered systems or power restricted applications. An input common-mode range that includes the positive supply makes the OP282/OP482 an excellent choice for highside signal conditioning. The OP282/OP482 are specified over the extended industrial temperature range. The OP282 is available in the standard 8-lead narrow SOIC and MSOP packages. The OP482 is available in PDIP and narrow SOIC packages. OUT A PIN CONNECTIONS IN A 2 7 OP282 +IN A V 3 4 OP V+ OUT B IN B +IN B Figure. 8-Lead Narrow-Body SOIC (S-Suffix) [R-8] OUT A IN A 2 +IN A 3 V 4 OUT A IN A +IN A V+ +IN B IN B OUT B OP282 TOP VIEW (Not to Scale) 3-8 V+ 7 OUT B 6 IN B +IN B Figure 2. 8-Lead MSOP [RM-8] OP OUT D 3 IN D 2 +IN D V +IN C 9 IN C 8 OUT C Figure 3. 4-Lead PDIP (P-Suffix) [N-4] OUT A IN A +IN A V+ +IN B IN B OUT B OP482 4 OUT D 3 IN D 2 +IN D V +IN C 9 IN C 8 OUT C Figure 4. 4-Lead Narrow-Body SOIC (S-Suffix) [R-4] Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Connections... Revision History... 2 Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 4 Thermal Resistance... 4 ESD Caution...4 Typical Performance Characteristics... Applications Information... 2 High-Side Signal Conditioning... 2 Phase Inversion... 2 Active Filters... 2 Programmable State Variable Filter... 3 Outline Dimensions... 4 Ordering Guide... 6 REVISION HISTORY 7/8 Rev. F to Rev. G Changes to Phase Inversion Section... 2 Deleted Figure Added Figure 4 and Figure Updated Outline Dimensions... 4 Changes to Ordering Guide... 6 /4 Rev. E to Rev. F Deleted 8-Lead PDIP... Universal Added 8-Lead MSOP... Universal Changes to Format and Layout... Universal Changes to Features... Changes to Pin Configurations... Changes to General Description... Changes to Specifications... 3 Changes to Absolute Maximum Ratings... 4 Changes to Table Added Figure through Figure 2; Renumbered Successive Figures... Updated Figure 2 and Figure Updated Figure 23 and Figure Updated Figure Updated Figure 3 and Figure Updated Figure Changes to Applications Information... 2 Changes to Figure Deleted OP282/OP482 Spice Macro Model Section... 9 Deleted Figure Deleted OP282 Spice Marco Model... Updated Outline Dimensions... 4 Changes to Ordering Guide... 4 /2 Rev. D to Rev. E Edits to 8-Lead Epoxy DIP (P-Suffix) Pin... Edits to Ordering Guide... 3 Edits to Outline Dimensions... 9/2 Rev. C to Rev. D Edits to 4-Lead SOIC (S-Suffix) Pin... Replaced 8-Lead SOIC (S-Suffix)... 4/2 Rev. B to Rev. C Wafer Test Limits Deleted... 2 Edits to Absolute Maximum Ratings... 3 Dice Characteristics Deleted... 3 Edits to Ordering Guide... 3 Edits to Figure... 7 Edits to Figure Position Chip Carrier (RC Suffix) Deleted... Rev. G Page 2 of 6

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS At VS = ±. V, TA = 2 C, unless otherwise noted; applies to both A and G grades. Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS OP mv OP282, 4 C TA +8 C 4. mv OP mv OP482, 4 C TA +8 C 6 mv Input Bias Current IB VCM = V 3 pa VCM = V pa Input Offset Current IOS VCM = V pa VCM = V 2 pa Input Voltage Range + V Common-Mode Rejection Ratio CMRR V VCM + V, 4 C TA +8 C 7 9 db Large Signal Voltage Gain AVO RL = kω 2 V/mV RL = kω, 4 C TA +8 C V/mV Offset Voltage Drift ΔVOS/ΔT μv/ C Bias Current Drift ΔIB/ΔT 8 pa/ C OUTPUT CHARACTERISTICS Output Voltage High VOH RL = kω V Output Voltage Low VOL RL = kω V Short-Circuit Limit ISC Source 3 ma Sink 2 8 ma Open-Loop Output Impedance ZOUT f = MHz 2 Ω POWER SUPPLY Power Supply Rejection Ratio PSRR VS = ±4. V to ±8 V, 4 C TA +8 C 2 36 μv/v Supply Current/Amplifier ISY VO = V, 4 C TA 8 C 2 2 μa Supply Voltage Range VS ±4. ±8 V DYNAMIC PERFORMANCE Slew Rate SR RL = kω 7 9 V/μs Full-Power Bandwidth BWP % distortion 2 khz Settling Time ts To.%.6 μs Gain Bandwidth Product GBP 4 MHz Phase Margin ØM Degrees NOISE PERFORMANCE Voltage Noise en p-p. Hz to Hz.3 μv p-p Voltage Noise Density en f = khz 36 nv/ Hz Current Noise Density in. pa/ Hz The input bias and offset currents are characterized at TA = TJ = 8 C. Bias and offset currents are guaranteed but not tested at 4 C. Rev. G Page 3 of 6

4 ABSOLUTE MAXIMUM RATINGS Table 2. Parameters Ratings Supply Voltage ±8 V Input Voltage ±8 V Differential Input Voltage 36 V Output Short-Circuit Duration Indefinite Storage Temperature Range P-Suffix (N), S-Suffix (R), RM Packages 6 C to + C Operating Temperature Range OP282G, OP282A, OP482G 4 C to +8 C Junction Temperature Range P-Suffix (N), S-Suffix (R), RM Packages 6 C to + C Lead Temperature (Soldering 6 sec) 3 C For supply voltages less than ±8 V, the absolute maximum input voltage is equal to the supply voltage. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device in socket for CERDIP and PDIP. θja is specified for device soldered in circuit board for SOIC_N or MSOP packages. Table 3. Package Type θja θjc Unit 8-Lead MSOP [RM] C/W 8-Lead SOIC_N (S-Suffix) [R] 7 6 C/W 4-Lead PDIP (P-Suffix) [N] C/W 4-Lead SOIC_N (S-Suffix) [R] 4 36 C/W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. G Page 4 of 6

5 TYPICAL PERFORMANCE CHARACTERISTICS OPEN-LOOP GAIN (db) k k k M M Figure. OP282 Open-Loop Gain and Phase vs. Frequency 9 4 PHASE (Degree) 3- CLOSED-LOOP GAIN (db) k A VCL = A VCL = A VCL = OP282/OP482 k k M M Figure 8. OP282 Closed-Loop Gain vs. Frequency R L = kω 3 2 SR R L = kω C L = pf OPEN-LOOP GAIN (V/mV) Figure 6. OP282 Open-Loop Gain vs. Temperature 3-6 SLEW RATE (V/µs) 2 7 +SR Figure 9. OP282 Slew Rate vs. Temperature 3-9 OVERSHOOT (%) R L = 2kΩ V IN = mv p-p A VCL = +OS OS INPUT BIAS CURRENT (pa) V CM = V LOAD CAPACITANCE (pf) Figure 7. OP282 Small Signal Overshoot vs. Load Capacitance Figure. OP282 Input Bias Current vs. Temperature 3- Rev. G Page of 6

6 VOLTAGE NOISE DENSITY (nv/ Hz) k k Figure. OP282 Voltage Noise Density vs. Frequency 3- OUTPUT VOLTAGE SWING (V) 2 2 R L = kω ± ± V OH V OL SUPPLY VOLTAGE (V) ± Figure 4. OP282 Output Voltage Swing vs. Supply Voltage 3-4 ±2 INPUT BIAS CURRENT (pa) OUTPUT IMPEDANCE (Ω) A VCL = A VCL = A VCL =. COMMON-MODE VOLTAGE (V) Figure 2. OP282 Input Bias Current vs. Common-Mode Voltage 3-2. k k k Figure. OP282 Closed-Loop Output Impedance vs. Frequency M SUPPLY CURRENT (µa) SUPPLY CURRENT (µa) ± ± SUPPLY VOLTAGE (V) ± Figure 3. OP282 Supply Current vs. Supply Voltage 3-3 ± Figure 6. OP282 Supply Current vs. Temperature Rev. G Page 6 of 6

7 ABSOLUTE OUTPUT VOLTAGE (V) V OL V OH k LOAD RESISTANCE (Ω) Figure 7. OP282 Absolute Output Voltage vs. Load Resistance 3-7 k MAXIMUM OUTPUT SWING (V p-p) R L = kω A VCL = k k k M Figure 2. OP282 Maximum Output Swing vs. Frequency PSRR 8 PSRR (db) PSRR CMRR (db) k k k Figure 8. OP282 PSRR vs. Frequency M k k k Figure 2. OP282 CMRR vs. Frequency M 3-2 SHORT-CIRCUIT CURRENT (ma) SOURCE SINK UNITS V OS (µv) 3 OP282 (6 OP AMPS) Figure 9. OP282 Short-Circuit Current vs. Temperature Figure 22. OP282 VOS Distribution SOIC_N Package Rev. G Page 7 of 6

8 OP282 (6 OP AMPS) 7 6 R L = 2kΩ V IN = mv p-p A VCL = NEGATIVE EDGE UNITS OVERSHOOT (%) A VCL = POSITIVE EDGE TCV OS (µv/ C) Figure 23. OP282 TCVOS Distribution SOIC_N Package LOAD CAPACITANCE (pf) Figure 26. OP482 Small Signal Overshoot vs. Load Capacitance 3-26 OPEN-LOOP GAIN (db) k k k M M M Figure 24. OP482 Open-Loop Gain, Phase vs. Frequency PHASE (Degrees) 3-24 CLOSED-LOOP GAIN (db) A VCL = A VCL = A VCL = 2 k k k M M M Figure 27. OP482 Closed-Loop Gain vs. Frequency 3-27 OPEN-LOOP GAIN (V/mV) R L = kω SLEW RATE (V/µs) 2 2 SR +SR R L = kω C L = pf Figure 2. OP482 Open-Loop Gain (V/mV) Figure 28. OP482 Slew Rate vs. Temperature 3-28 Rev. G Page 8 of 6

9 V CM = V INPUT BIAS CURRENT (pa). INPUT BIAS CURRENT (pa) Figure 29. OP482 Input Bias Current vs. Temperature COMMON-MODE VOLTAGE (V) Figure 32. OP482 Input Bias Current vs. Common-Mode Voltage 3-32 PHASE MARGIN (Degrees) 6 4 GBW Ø M R L = kω GAIN BANDWIDTH PRODUCT (MHz) REL ATIVE SUPPLY CURRENT (I SY ) Figure 3. OP482 Phase Margin and Gain Bandwidth Product vs. Temperature ± ± ± ± 2 SUPPLY VOLTAGE (V) Figure 33. OP482 Relative Supply Current vs. Supply Voltage 3-33 VOLTAGE NOISE DENSITY (nv/ Hz) k k Figure 3. OP482 Voltage Noise Density vs. Frequency 3-3 OUTPUT VOLTAGE SWING (V) 2 R L = kω 2 ± ± ± ±2 SUPPLY VOLTAGE (V) Figure 34. OP482 Output Voltage Swing vs. Supply Voltage 3-34 Rev. G Page 9 of 6

10 6 8 +PSRR ΔV = mv IMPEDANCE (Ω) PSRR (db) PSRR A VCL = A VCL = A VCL = k k k M Figure 3. OP482 Closed-Loop Output Impedance vs. Frequency k k k M Figure 38. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency 3-38 RELATIVE SUPPLY CURRENT (I SY ) Figure 36. OP482 Relative Supply Current vs. Temperature 3-36 SHORT-CIRCUIT CURRENT (ma) 2 SINK SOURCE Figure 39. OP482 Short-Circuit Current vs. Temperature 3-39 ABSOLUTE OUTPUT VOLTAGE (V) POSITIVE SWING LOAD RESISTANCE (Ω) Figure 37. OP482 Maximum Output Voltage vs. Load Resistance k NEGATIVE SWING 3-37 k MAXIMUM OUTPUT SWING (V) K K K A VCL = R L = kω Figure 4. OP482 Maximum Output Swing vs. Frequency M 3-4 Rev. G Page of 6

11 CMRR (db) UNITS V CM = mv 2 k k k M TCV OS (µv/ C) Figure 4. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency Figure 43. OP482 TCVOS Distribution P Package OP482 (2 OP AMPS) UNITS V OS (µv) Figure 42. OP482 VOS Distribution P Package Rev. G Page of 6

12 APPLICATIONS INFORMATION The OP282 and OP482 are dual and quad JFET op amps that are optimized for high speed at low power. This combination makes these amplifiers excellent choices for battery-powered or low power applications that require above average performance. Applications benefiting from this performance combination include telecommunications, geophysical exploration, portable medical equipment, and navigational instrumentation. HIGH-SIDE SIGNAL CONDITIONING Many applications require the sensing of signals near the positive rail. OP282s and OP482s were tested and are guaranteed over a common-mode range ( V VCM + V) that includes the positive supply. One application where this is commonly used is in the sensing of power supply currents. This enables it to be used in current sensing applications, such as the partial circuit shown in Figure 44. In this circuit, the voltage drop across a low value resistor, such as the. Ω shown here, is amplified and compared to 7. V. The output can then be used for current limiting. V kω kω.ω kω kω /2 OP282 Figure 44. High-Side Signal Conditioning PHASE INVERSION Most JFET input amplifiers invert the phase of the input signal if either input exceeds the input common-mode range. For the OP282/OP482, a negative signal in excess of V causes phase inversion. This is caused by saturation of the input stage leading to the forward-biasing of a gate-drain diode. Phase reversal in OP282/OP482 can be prevented by using Schottky diodes to clamp the input terminals to each other and to the supplies. In the simple buffer circuit in Figure 4, D protects the op amp R L 3-46 against phase reversal. R, D2, and D3 limit the input current when the input exceeds the supply rail. The resistor should be selected to limit the amount of input current below the absolute maximum rating. VOLTAGE (V/DIV) 2 V+ R D2 kω IN7 OP282/ V OP482 IN D V+ IN7 V D3 IN7 V Figure 4. Phase Reversal Solution Circuit TIME (2µs/DIV) Figure 46. No Phase Reversal V IN V OUT 3-42 V OUT ACTIVE FILTERS The wide bandwidth and high slew rates of the OP282/OP482 make either one an excellent choice for many filter applications. There are many active filter configurations, but the four most popular configurations are Butterworth, elliptic, Bessel, and Chebyshev. Each type has a response that is optimized for a given characteristic as shown in Table Table 4. Type Selectivity Overshoot Phase Amplitude (Pass Band) Amplitude (Stop Band) Butterworth Moderate Good Maximum flat Chebyshev Good Moderate Nonlinear Equal ripple Elliptic Best Poor Equal ripple Equal ripple Bessel (Thompson) Poor Best Linear Rev. G Page 2 of 6

13 PROGRAMMABLE STATE VARIABLE FILTER The circuit shown in Figure 47 can be used to accurately program the Q, the cutoff frequency (fc), and gain of a two-pole state variable filter. OP482s have been used in this design because of their high bandwidths, low power, and low noise. This circuit takes only three packages to build because of the quad configuration of the op amps and DACs. The DACs shown are used in the voltage mode; therefore, many values are dependent on the accuracy of the DAC only and not on the absolute values of the DAC s resistive ladders. This makes this circuit unusually accurate for a programmable filter. Adjusting DAC changes the signal amplitude across R; therefore, the DAC attenuation times R determines the amount of signal current that charges the integrating capacitor, C. This cutoff frequency can now be expressed as D fc = 2πRC 26 where D is the digital code for the DAC. The gain of this circuit is set by adjusting D3. The gain equation is Gain = R4 R D3 26 DAC 2 is used to set the Q of the circuit. Adjusting this DAC controls the amount of feedback from the band-pass node to the input summing node. Note that the digital value of the DAC is in the numerator; therefore, zero code is not a valid operating point. R2 26 Q = R3 D2 R7 2kΩ R4 2kΩ V IN /4 DAC848 /4 OP482 R 2kΩ /4 OP482 HIGH PASS C pf R /4 /4 2kΩ DAC848 OP482 /4 OP482 C pf R /4 /4 2kΩ DAC848 OP482 /4 OP482 LOW PASS R6 2kΩ BAND PASS R3 2kΩ /4 OP482 R2 2kΩ /4 OP482 /4 DAC848 Figure 47. Programmable State Variable Filter 3-47 Rev. G Page 3 of 6

14 OUTLINE DIMENSIONS PIN.6 BSC COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters. (.968) 4.8 (.89) 4. (.74) 3.8 (.497) (.244).8 (.2284).2 (.98). (.4) COPLANARITY. SEATING PLANE.27 (.) BSC.7 (.688).3 (.32). (.2).3 (.22) 8.2 (.98).7 (.67). (.96).2 (.99).27 (.).4 (.7) 4 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-8) Dimensions shown in millimeters and (inches) 247-A Rev. G Page 4 of 6

15 .77 (9.69).7 (9.).73 (8.67).2 (.33) MAX. (3.8).3 (3.3). (2.79).22 (.6).8 (.46).4 (.36) 4. (2.4) BSC.7 (.78). (.27).4 (.4) (7.).2 (6.3).24 (6.). (.38) MIN SEATING PLANE. (.3) MIN.6 (.2) MAX. (.38) GAUGE PLANE.32 (8.26).3 (7.87).3 (7.62).43 (.92) MAX.9 (4.9).3 (3.3). (2.92).4 (.36). (.2).8 (.2) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure. 4-Lead Plastic Dual In-Line Package [PDIP] P-Suffix (N-4) Dimension shown in inches and (millimeters) 766-A 8.7 (.344) 8. (.3366) 4. (.7) 3.8 (.496) (.244).8 (.2283).2 (.98). (.39) COPLANARITY..27 (.) BSC. (.2).3 (.22).7 (.689).3 (.3) SEATING PLANE 8.2 (.98).7 (.67). (.97).2 (.98).27 (.).4 (.7) 4 COMPLIANT TO JEDEC STANDARDS MS-2-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 4-Lead Standard Small Outline Package [SOIC_N] Narrow Body S-Suffix (R-4) Dimensions shown in millimeters and (inches) 666-A Rev. G Page of 6

16 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding OP282ARMZ-R2 4 C to +8 C 8-Lead MSOP RM-8 AB OP282ARMZ-REEL 4 C to +8 C 8-Lead MSOP RM-8 AB OP282GS 4 C to +8 C 8-Lead SOIC_N S-Suffix (R-8) OP282GS-REEL 4 C to +8 C 8-Lead SOIC_N S-Suffix (R-8) OP282GS-REEL7 4 C to +8 C 8-Lead SOIC_N S-Suffix (R-8) OP282GSZ 4 C to +8 C 8-Lead SOIC_N S-Suffix (R-8) OP282GSZ-REEL 4 C to +8 C 8-Lead SOIC_N S-Suffix (R-8) OP282GSZ-REEL7 4 C to +8 C 8-Lead SOIC_N S-Suffix (R-8) OP482GP 4 C to +8 C 4-Lead PDIP P-Suffix (N-4) OP482GPZ 4 C to +8 C 4-Lead PDIP P-Suffix (N-4) OP482GS 4 C to +8 C 4-Lead SOIC_N S-Suffix (R-4) OP482GS-REEL 4 C to +8 C 4-Lead SOIC_N S-Suffix (R-4) OP482GS-REEL7 4 C to +8 C 4-Lead SOIC_N S-Suffix (R-4) OP482GSZ 4 C to +8 C 4-Lead SOIC_N S-Suffix (R-4) OP482GSZ-REEL 4 C to +8 C 4-Lead SOIC_N S-Suffix (R-4) OP482GSZ-REEL7 4 C to +8 C 4-Lead SOIC_N S-Suffix (R-4) Z = RoHS Compliant Part. 28 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D3--7/8(G) Rev. G Page 6 of 6

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