Ultraprecision Operational Amplifier OP177

Transcription

1 Ultraprecision Operational Amplifier FEATURES Ultralow offset voltage TA = 25 C, 25 μv maximum Outstanding offset voltage drift 0. μv/ C maximum Excellent open-loop gain and gain linearity 2 V/μV typical CMRR: 30 db minimum PSRR: 5 db minimum Low supply current 2.0 ma maximum Fits industry-standard precision op amp sockets GENERAL DESCRIPTION The features one of the highest precision performance of any op amp currently available. Offset voltage of the is only 25 μv maximum at room temperature. The ultralow VOS of the combines with its exceptional offset voltage drift (TCVOS) of 0. μv/ C maximum to eliminate the need for external VOS adjustment and increases system accuracy over temperature. The open-loop gain of 2 V/μV is maintained over the full ±0 V output range. CMRR of 30 db minimum, PSRR of 20 db minimum, and maximum supply current of 2 ma are just a few examples of the excellent performance of this PIN CONFIGURATION V OS TRIM IN 2 IN 3 V 4 TOP VIEW (Not to Scale) 8 V OS TRIM 7 V 6 OUT 5 NC NC = NO CONNECT Figure. 8-Lead PDIP (P-Suffix), 8-Lead SOIC (S-Suffix) operational amplifier. The combination of outstanding specifications of the ensures accurate performance in high closed-loop gain applications. This low noise, bipolar input op amp is also a cost effective alternative to chopper-stabilized amplifiers. The provides chopper-type performance without the usual problems of high noise, low frequency chopper spikes, large physical size, limited common-mode input voltage range, and bulky external storage capacitors. The is offered in the 40 C to 85 C extended industrial temperature ranges. This product is available in 8-lead PDIP, as well as the space saving 8-lead SOIC FUNCTIONAL BLOCK DIAGRAM V R 2A * (OPTIONAL NULL) R 2B * C R7 R A R B 2B Q 9 Q 9 Q 0 NONINVERTING INVERTING R 3 R 4 Q 5 Q 2 Q 22 Q 7 Q 23 Q 24 Q 3 Q Q 6 Q 8 Q 4 Q 2 Q 27 Q 26 Q 25 Q Q 2 C 3 C 2 R 5 Q 4 Q 7 Q 6 Q 5 Q 8 R 9 Q 20 R 0 OUTPUT Q 3 R 6 R 8 V *R 2A AND R 2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY Figure 2. Simplified Schematic Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners Analog Devices, Inc. All rights reserved.

2 SPECIFICATIONS ELECTRICAL VS = ±5 V, TA = 25 C, unless otherwise noted. Table. F G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit OFFSET VOLTAGE VOS μv LONG-TERM OFFSETT Voltage Stability ΔVOS/time μv/mo OFFSET CURRENT IOS na BIAS CURRENT IB na NOISE VOLTAGE en fo = Hz to 00 Hz nv rms NOISE CURRENT in fo = Hz to 00 Hz pa rms RESISTANCE Differential Mode 3 RIN MΩ RESISTANCE COMMON MODE RINCM GΩ VOLTAGE RANGE 4 IVR ±3 ±4 ±3 ±4 V COMMON-MODE REJECTION RATIO CMRR VCM = ±3 V db POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±8 V db LARGE SIGNAL VOLTAGE GAIN AVO RL 2 kω, VO = ±0 V , V/mV OUTPUT VOLTAGE SWING VO RL 0 kω ±3.5 ±4.0 ±3.5 ±4.0 V RL 2 kω ±2.5 ±3.0 ±2.5 ±3.0 V RL kω ±2.0 ±2.5 ±2.0 ±2.5 V SLEW RATE 2 SR RL 2 kω V/μs CLOSED-LOOP BANDWIDTH 2 BW AVCL = MHz OPEN-LOOP OUTPUT RESISTANCE RO Ω POWER CONSUMPTION PD VS = ±5 V, no load mw VS = ±3 V, no load mw SUPPLY CURRENT ISY VS = ±5 V, no load ma OFFSET ADJUSTMENT RANGE RP = 20 kω ±3 ±3 mv Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μv. 2 Sample tested. 3 Guaranteed by design. 4 Guaranteed by CMRR test condition. 5 To ensure high open-loop gain throughout the ±0 V output range, AVO is tested at 0 V VO 0 V, 0 V VO 0 V, and 0 V VO 0 V. Rev. E Page 3 of 6

3 @ VS = ±5 V, 40 C TA 85 C, unless otherwise noted. Table 2. F G Parameter Symbol Conditions Min Typ Max Min Typ Max Unit Input Offset Voltage VOS μv Average Input Offset Voltage Drift TCVOS μv/ C Input Offset Current IOS na Average Input Offset Current Drift 2 TCIOS pa/ C Input Bias Current IB ±6 na Average Input Bias Current Drift 2 TCIB pa/ C Input Voltage Range 3 IVR ±3 ±3.5 ±3 ±3.5 V COMMON-MODE REJECTION RATIO CMRR VCM = ±3 V db POWER SUPPLY REJECTION RATIO PSRR VS = ±3 V to ±8 V db LARGE-SIGNAL VOLTAGE GAIN 4 AVO RL 2 kω, VO = ±0 V V/mV OUTPUT VOLTAGE SWING VO RL 2 kω ±2 ±3 ±2 ±3 V POWER CONSUMPTION PD VS = ±5 V, no load mw SUPPLY CURRENT ISY VS = ±5 V, no load ma TCVOS is sample tested. 2 Guaranteed by endpoint limits. 3 Guaranteed by CMRR test condition. 4 To ensure high open-loop gain throughout the ±0 V output range, AVO is tested at 0 V VO 0 V, 0 V VO 0 V, and 0 V VO 0 V. TEST CIRCUITS 200kΩ 50Ω V OS = V O 4000 V O Figure 3. Typical Offset Voltage Test Circuit kΩ V V OUTPUT V OS TRIM RANGE IS TYPICALLY ±3.0mV Figure 4. Optional Offset Nulling Circuit kΩ 20V PINOUTS SHOWN FOR P AND Z PACKAGES 20V Figure 5. Burn-In Circuit Rev. E Page 4 of 6

4 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Ratings Supply Voltage ±22 V Internal Power Dissipation 500 mw Differential Input Voltage ±30 V Input Voltage ±22 V Output Short-Circuit Duration Indefinite Storage Temperature Range 65 C to 25 C Operating Temperature Range 40 C to 85 C Lead Temperature (Soldering, 60 sec) 300 C DICE Junction Temperature (TJ) 65 C to 50 C For supply voltages less than ±22 V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for worst-case mounting conditions, that is, θja is specified for device in socket for PDIP; θja is specified for device soldered to printed circuit board for SOIC package. Table 4. Thermal Resistance Package Type θja θjc Unit 8-Lead PDIP (P-Suffix) C/W 8-Lead SOIC (S-Suffix) C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. E Page 5 of 6

5 OUTLINE DIMENSIONS (0.6) (9.27) (9.02) PIN 0.20 (5.33) MAX 0.50 (3.8) 0.30 (3.30) 0.5 (2.92) (0.56) 0.08 (0.46) 0.04 (0.36) (2.54) BSC (.78) (.52) (.4) (7.) (6.35) (6.0) 0.05 (0.38) MIN SEATING PLANE (0.3) MIN (.52) MAX 0.05 (0.38) GAUGE PLANE (8.26) 0.30 (7.87) (7.62) (0.92) MAX 0.95 (4.95) 0.30 (3.30) 0.5 (2.92) 0.04 (0.36) 0.00 (0.25) (0.20) COMPLIANT TO JEDEC STANDARDS MS-00-BA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure Lead Plastic Dual In-Line Package (PDIP) P-Suffix (N-8) Dimensions show in inches and (millimeters) 5.00 (0.968) 4.80 (0.890) 4.00 (0.574) 3.80 (0.497) (0.2440) 5.80 (0.2284) 0.25 (0.0098) 0.0 (0.0040) COPLANARITY (0.0500) BSC SEATING PLANE.75 (0.0688).35 (0.0532) 0.5 (0.020) 0.3 (0.022) 0.25 (0.0098) 0.7 (0.0067) (0.096) 0.25 (0.0099) (0.0500) 0.40 (0.057) COMPLIANT TO JEDEC STANDARDS MS-02-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package (SOIC_N) S-Suffix (R-8) Dimensions shown in millimeters and( inches) Rev. E Page 3 of 6

6 ORDERING GUIDE Model Temperature Range Package Description Package Option FP 40 C to 85 C 8-Lead PDIP P-Suffix (N-8) FPZ 40 C to 85 C 8-Lead PDIP P-Suffix (N-8) GP 40 C to 85 C 8-Lead PDIP P-Suffix (N-8) GPZ 40 C to 85 C 8-Lead PDIP P-Suffix (N-8) FS 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FS-REEL 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FS-REEL7 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FSZ 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FSZ-REEL 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) FSZ-REEL7 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GS 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GS-REEL 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GS-REEL7 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GSZ 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GSZ-REEL 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) GSZ-REEL7 40 C to 85 C 8-Lead SOIC_N S-Suffix (R-8) Z = Pb-free part. Rev. E Page 4 of 6