High Common-Mode Voltage, Programmable Gain Difference Amplifier AD628

Transcription

1 High Common-Mode Voltage, Programmable Gain Difference Amplifier FEATURES High common-mode input voltage range ±2 V at VS = ± V Gain range. to Operating temperature range: 4 C to ±8 C Supply voltage range Dual supply: ±2.2 V to ±8 V Single supply: 4. V to 36 V Excellent ac and dc performance Offset temperature stability RTI: μv/ C maximum Offset: ±. V mv maximum CMRR RTI: 7 db minimum, dc to Hz, G = + APPLICATIONS High voltage current shunt sensing Programmable logic controllers Analog input front end signal conditioning + V, + V, ± V, ± V, and 4 to 2 ma Isolation Sensor signal conditioning Power supply monitoring Electrohydraulic control Motor control GENERAL DESCRIPTION The is a precision difference amplifier that combines excellent dc performance with high common-mode rejection over a wide range of frequencies. When used to scale high voltages, it allows simple conversion of standard control voltages or currents for use with single-supply ADCs. A wideband feedback loop minimizes distortion effects due to capacitor charging of Σ-Δ ADCs. A reference pin (VREF) provides a dc offset for converting bipolar to single-sided signals. The converts + V, + V, ± V, ± V, and 4 to 2 ma input signals to a single-ended output within the input range of single-supply ADCs. The has an input common-mode and differential-mode operating range of ±2 V. The high common-mode input impedance makes the device well suited for high voltage measurements across a shunt resistor. The inverting input of the buffer amplifier is available for making a remote Kelvin connection. CMRR (db) kω kω V S FUNCTIONAL BLOCK DIAGRAM G = +. A V REF +V S C FILT Figure. V S = ±V R EXT2 R G R EXT A2 3 k k k FREQUENCY (Hz) V S = ±2.V Figure 2. CMRR vs. Frequency of the OUT A precision kω resistor connected to an external pin is provided for either a low-pass filter or to attenuate large differential input signals. A single capacitor implements a lowpass filter. The operates from single and dual supplies and is available in an 8-lead SOIC_N or 8-lead MSOP package. It operates over the standard industrial temperature range of 4 C to +8 C C C- Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 7 Thermal Characteristics... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 Typical Performance Characteristics... 9 Theory of Operation... 4 Applications... Gain Adjustment... Input Voltage Range... Voltage Level Conversion... 6 Current Loop Receiver... 7 Monitoring Battery Voltages... 7 Filter Capacitor Values... 8 Kelvin Connection... 8 Outline Dimensions... 9 Ordering Guide... 9 Test Circuits... 3 REVISION HISTORY 3/6 Rev. E to Rev. F Changes to Table... 3 Changes to Figure Replaced Voltage Level Conversion Section... 6 Changes to Figure 32 and Figure Updated Outline Dimensions... 9 Changes to Ordering Guide... 9 / Rev. D to Rev. E Changes to Table... 3 Changes to Table 2... Changes to Figure / Rev. C to Rev. D Updated Format... Universal Changes to Table... 3 Changes to Table /4 Rev. B to Rev. C Updated Format... Universal Changes to Specifications... 3 Changes to Absolute Maximum Ratings... 7 Changes to Figure Changes to Figure Changes to Figure Changes to Theory of Operation...4 Changes to Figure Changes to Table... Changes to Gain Adjustment Section... Added the Input Voltage Range Section... Added Figure 3... Added Figure 3... Changes to Voltage Level Conversion Section... 6 Changes to Figure Changes to Table Changes to Figure 33 and Figure Changes to Figure Changes to Kelvin Connection Section /3 Rev. A to Rev. B Changes to General Description... Changes to Specifications... 2 Changes to Ordering Guide... 4 Changes to TPCs 4,, and 6... Changes to TPC Updated Outline Dimensions... 4 /3 Rev. to Rev. A Change to Ordering Guide... 4 /2 Rev. : Initial Version Rev. F Page 2 of 2

3 SPECIFICATIONS TA = 2 C, VS = ± V, RL = 2 kω, REXT = kω, REXT2 =, VREF =, unless otherwise noted. Rev. F Page 3 of 2 Table. AR ARM Parameter Conditions Min Typ Max Min Typ Max Unit DIFFERENTIAL AND OUTPUT AMPLIFIER Gain Equation G = +.(+ REXT/REXT2) V/V Gain Range See Figure 29.. V/V Offset Voltage VCM = V; RTI of input pins 2 ; mv output amplifier G = + vs. Temperature μv/ C CMRR 3 RTI of input pins; 7 7 db G = +. to + Hz 7 7 db Minimum CMRR Over Temperature 4 C to +8 C 7 7 db vs. Temperature 4 4 (μv/v)/ C PSRR (RTI) VS = ± V to ±8 V db Input Voltage Range Common Mode V Differential V Dynamic Response Small Signal Bandwidth 3 db G = khz Full Power Bandwidth khz Settling Time G = +., to.%, V step 4 4 μs Slew Rate.3.3 V/μs Noise (RTI) Spectral Density khz 3 3 nv/ Hz. Hz to Hz μv p-p DIFFERENTIAL AMPLIFIER Gain.. V/V Error % vs. Temperature ppm/ C Nonlinearity ppm vs. Temperature 3 3 ppm Offset Voltage RTI of input pins mv vs. Temperature 8 8 μv/ C Input Impedance Differential kω Common Mode kω CMRR 4 RTI of input pins; 7 7 db G = +. to + Hz 7 7 db Minimum CMRR Over Temperature 4 C to +8 C 7 7 db vs. Temperature 4 4 (μv/v)/ C Output Resistance kω Error % OUTPUT AMPLIFIER Gain Equation G = ( + REXT/REXT2) V/V Nonlinearity G = +, VOUT = ± V.. ppm Offset Voltage RTI of output amp mv vs. Temperature.6.6 μv/ C Output Voltage Swing RL = kω V RL = 2 kω V

4 AR ARM Parameter Conditions Min Typ Max Min Typ Max Unit Bias Current na Offset Current na CMRR VCM = ±3 V 3 3 db Open-Loop Gain VOUT = ±3 V 3 3 db POWER SUPPLY Operating Range ±2.2 ±8 ±2.2 ±8 V Quiescent Current.6.6 ma TEMPERATURE RANGE C To use a lower gain, see the Ga in Adjustment section. 2 The addition of the difference amplifier and output amplifier offset voltage does not exceed this specification. (.)( V ) 3 Error due to common mode as seen at the output: V [ CM OUT = ] [ Output AmplifierGain] 7 2 (.)( V 4 CM ) Error due to common mode as seen at the output of A: V OUT A = [ ] 7 2 Rev. F Page 4 of 2

5 TA = 2 C, VS = V, RL = 2 kω, REXT = kω, REXT2 =, VREF = 2., unless otherwise noted. Table 2. AR ARM Parameter Conditions Min Typ Max Min Typ Max Unit DIFFERENTIAL AND OUTPUT AMPLIFIER Gain Equation G = +.(+ REXT/REXT2) V/V Gain Range See Figure 29.. V/V Offset Voltage VCM = 2.2 V; RTI of input pins 2 ; mv output amplifier G = + vs. Temperature 6 6 μv/ C CMRR 3 RTI of input pins; G = +. to db Hz 7 7 db Minimum CMRR Over Temperature 4 C to +8 C 7 7 db vs. Temperature 4 4 (μv/v)/ C PSRR (RTI) VS = 4. V to V db Input Voltage Range Common Mode V Differential + + V Dynamic Response Small Signal Bandwidth 3 db G = khz Full Power Bandwidth 3 3 khz Settling Time G = +.; to.%, 3 V step μs Slew Rate.3.3 V/μs Noise (RTI) Spectral Density khz 3 3 nv/ Hz. Hz to Hz μv p-p DIFFERENTIAL AMPLIFIER Gain.. V/V Error % Nonlinearity 3 3 ppm vs. Temperature 3 3 ppm Offset Voltage RTI of input pins mv vs. Temperature μv/ C Input Impedance Differential kω Common Mode kω CMRR RTI of input pins; G = +. to db Hz 7 7 db Minimum CMRR Over Temperature 4 C to +8 C 7 7 db vs. Temperature 4 4 (μv/v)/ C Output Resistance kω Error % OUTPUT AMPLIFIER Gain Equation G = ( + REXT/REXT2) V/V Nonlinearity G = +, VOUT = V to 4 V.. ppm Output Offset Voltage RTI of output amplifier.... mv vs. Temperature.6.6 μv/ C Output Voltage Swing RL = kω V RL = 2 kω 4 4 V Bias Current na Offset Current na CMRR VCM = V to 4 V 3 3 db Open-Loop Gain VOUT = V to 4 V 3 3 db Rev. F Page of 2

6 AR ARM Parameter Conditions Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range ± ± V Quiescent Current.6.6 ma TEMPERATURE RANGE C To use a lower gain, see the Gain Adjustment section. 2 The addition of the difference amplifier and output amplifier offset voltage does not exceed this specification. (.)( V ) 3 Error due to common mode as seen at the output: V [ CM OUT = ] [ Output AmplifierGain] Greater values of voltage are possible with greater or lesser values of VREF. (.)( V CM ) Error due to common mode as seen at the output of A: V OUT A = [ ] 7 2 Rev. F Page 6 of 2

7 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±8 V Internal Power Dissipation See Figure 3 Input Voltage (Common Mode) ±2 V Differential Input Voltage ±2 V Output Short-Circuit Duration Indefinite Storage Temperature 6 C to +2 C Operating Temperature Range 4 C to +8 C Lead Temperature (Soldering, sec) 3 C When using ±2 V supplies or higher (see the Input Voltage Range section). Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS.6.4 T J = C POWER DISSIPATION (W) LEAD SOIC PACKAGE 8-LEAD MSOP PACKAGE MSOP θ JA (JEDEC; 4-LAYER BOARD) = 32.4 C/W SOIC θ JA (JEDEC; 4-LAYER BOARD) = 4 C/W AMBIENT TEMPERATURE ( C) Figure 3. Maximum Power Dissipation vs. Temperature 2992-C-3 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F Page 7 of 2

8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V S V REF C FILT TOP VIEW (Not to Scale) V S R G OUT Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Descriptions Noninverting Input 2 VS Negative Supply Voltage 3 VREF Reference Voltage Input 4 CFILT Filter Capacitor Connection OUT Amplifier Output 6 RG Output Amplifier Inverting Input 7 +VS Positive Supply Voltage 8 IN Inverting Input 2992-C-4 Rev. F Page 8 of 2

9 TYPICAL PERFORMANCE CHARACTERISTICS UNITS G = +. % OF UNITS 2 2 PSRR (db) V +V +2.V INPUT OFFSET VOLTAGE (mv) Figure. Typical Distribution of Input Offset Voltage, VS = ± V, SOIC_N Package 2992-C-. k k k M FREQUENCY (Hz) Figure 8. PSRR vs. Frequency, Single and Dual Supplies 2992-C UNITS % OF UNITS 2 VOLTAGE NOISE DENSITY (nv/ Hz) CMRR (db) Figure 6. Typical Distribution of Common-Mode Rejection, SOIC_N Package C-6 k k k FREQUENCY (Hz) Figure 9. Voltage Noise Spectral Density, RTI, VS = ± V 2992-C-9 CMRR (db) V S = ±V V S = ±2.V VOLTAGE NOISE DENSITY (nv/ Hz) 4 3 k k k FREQUENCY (Hz) Figure 7. CMRR vs. Frequency 2992-C-7 k k k FREQUENCY (Hz) Figure. Voltage Noise Spectral Density, RTI, VS = ±2. V 2992-C- Rev. F Page 9 of 2

10 s UNITS 9 3 NOISE (μv/div) % OF DEVICES 2 2 TIME (Sec) Figure.. Hz to Hz Voltage Noise, RTI 2992-C GAIN ERROR (ppm) Figure 4. Typical Distribution of + Gain Error 2992-C-4 6 GAIN (db) G = + G = + G = + G = +. COMMON-MODE VOLTAGE (V) +2 C 4 C +8 C +8 C 4 C UPPER CMV LIMIT V REF = V LOWER CMV LIMIT 4 k k k M M FREQUENCY (Hz) 2992-C-2 V S (±V) C- Figure 2. Small Signal Frequency Response, VOUT = 2 mv p-p, G = +., +, +, and + Figure. Common-Mode Operating Range vs. Power Supply Voltage for Three Temperatures 6 μv V S = ±V GAIN (db) G = + G = + G = + G = +. OUTPUT ERROR (μv) 9 R L = kω R L = 2kΩ R L = 3 4.V 4 k k k M FREQUENCY (Hz) 2992-C-3 OUTPUT VOLTAGE (V) 2992-C-6 Figure 3. Large Signal Frequency Response, VOUT = 2 V p-p, G = +., +, +, and + Figure 6. Normalized Gain Error vs. VOUT, VS = ± V Rev. F Page of 2

11 μv V S = ±2.V R L = kω mv 9 9 OUTPUT ERROR (μv) R L = 2kΩ R L = OUTPUT VOLTAGE (V) mv 2992-C-7 mv 4μs 2992-C-2 4 Figure 7. Normalized Gain Error vs. VOUT, VS = ±2. V Figure 2. Small Signal Pulse Response, RL = 2 kω, CL = pf, Top: Input, Bottom: Output mv 3 BIAS CURRENT (na) TEMPERATURE ( C) 2992-C-8 mv 4μs 2992-C-2 Figure 8. Bias Current vs. Temperature Buffer 4 C Figure 2. Small Signal Pulse Response, RL = 2 kω, CL = pf, Top: Input, Bottom: Output OUTPUT VOLTAGE SWING (V) +8 C +2 C +8 C 2 C 4 C 2 C +2 C 9 mv 2 2 OUTPUT CURRENT (ma) 2992-C-9 mv 4μs 2992-C-2 Figure 9. Output Voltage Operating Range vs. Output Current Figure 22. Large Signal Pulse Response, RL = 2 kω, CL = pf, Top: Input, Bottom: Output Rev. F Page of 2

12 9 V 9 V mv mv μs 2992-C-23 μs 2992-C-24 Figure 23. Settling Time to.%, V to V Step Figure 24. Settling Time to.% V to V Step Rev. F Page 2 of 2

13 TEST CIRCUITS HP389A SPECTRUM ANALYZER HP36A +V S SPECTRUM ANALYZER +V S kω kω G = +. V REF C FILT OUT R G AD829 + G = + FET PROBE kω 8 kω 7 G = +. C FILT 4 OUT AD77 + V S 2992-C-2 3 V REF 2 6 R G V S 2992-C-27 Figure 2. CMRR vs. Frequency Figure 27. Noise Tests SCOPE +V S VAC +V kω kω G = +. G = + OUT 2Ω G = + + AD829 V REF C FILT R G V S 2992-C-26 Figure 26. PSRR vs. Frequency Rev. F Page 3 of 2

14 THEORY OF OPERATION The is a high common-mode voltage difference amplifier, combined with a user-configurable output amplifier (see Figure 28 and Figure 29). Differential mode voltages in excess of 2 V are accurately scaled by a precision : voltage divider at the input. A reference voltage input is available to the user at Pin 3 (VREF). The output common-mode voltage of the difference amplifier is the same as the voltage applied to the reference pin. If the uncommitted amplifier is configured for gain, connect Pin 3 to one end of the external gain resistor to establish the output common-mode voltage at Pin (OUT). The uncommitted amplifier is a high open-loop gain, low offset, low drift op amp, with its noninverting input connected to the internal kω resistor. Both inputs are accessible to the user. Careful layout design has resulted in exceptional commonmode rejection at higher frequencies. The inputs are connected to Pin () and Pin 8 ( IN), which are adjacent to the power pins, Pin 2 ( VS) and Pin 7 (+VS). Because the power pins are at ac ground, input impedance balance and, therefore, commonmode rejection are preserved at higher frequencies. The output of the difference amplifier is internally connected to a kω resistor trimmed to better than ±.% absolute accuracy. The resistor is connected to the noninverting input of the output amplifier and is accessible at Pin 4 (CFILT). A capacitor can be connected to implement a low-pass filter, a resistor can be connected to further reduce the output voltage, or a clamp circuit can be connected to limit the output swing. kω kω G = +. A R G A2 OUT V REF C FILT 2992-C-28 Figure 28. Simplified Schematic C FILT +V S kω kω G = +. A A2 OUT V S V REF R G R EXT3 REFERENCE VOLTAGE R EXT2 Figure 29. Circuit Connections R EXT 2992-C-29 Rev. F Page 4 of 2

15 APPLICATIONS GAIN ADJUSTMENT The system gain is provided by an architecture consisting of two amplifiers. The gain of the input stage is fixed at.; the output buffer is user-adjustable as GA2 = + REXT/REXT2. The system gain is then R = + EXT GTOTAL. () R EXT2 At a 2 na maximum, the input bias current of the buffer amplifier is very low and any offset voltage induced at the buffer amplifier by its bias current may be neglected (2 na kω = 2 μv). However, to absolutely minimize bias current effects, select REXT and REXT2 so that their parallel combination is kω. If practical resistor values force the parallel combination of REXT and REXT2 below kω, add a series resistor (REXT3) to make up for the difference. Table lists several values of gain and corresponding resistor values. Table. Nearest Standard % Resistor Values for Various Gains Total Gain (V/V) A2 Gain (V/V) REXT (Ω) REXT2 (Ω). k k 2 k k 8.7 k k 2.4 k k k k. k 499 k.2 k M.2 k See Figure 29. REXT3 (Ω) To set the system gain to less than., create an attenuator by placing Resistor REXT4 from Pin 4 (CFILT) to the reference voltage. A divider is formed by the kω resistor that is in series with the positive input of A2 and Resistor REXT4. A2 is configured for unity gain. Using a divider and setting A2 to unity gain yields G W / DIVIDER REXT4 =. kω + R EXT4 INPUT VOLTAGE RANGE VREF and the supply voltage determine the common-mode input voltage range. The relation is expressed by V UPPER ( V +. 2 V) V (2) V CM CM LOWER S S REF ( V +. 2 V) V where VS+ is the positive supply, VS is the negative supply, and.2 V is the headroom needed for suitable performance. Equation 2 provides a general formula for calculating the common-mode input voltage range. However, keep the within the maximum limits listed in Table to maintain optimal performance. This is illustrated in Figure 3 where the maximum common-mode input voltage is limited to ±2 V. Figure 3 shows the common-mode input voltage bounds for single-supply voltages. INPUT COMMON-MODE VOLTAGE (V) INPUT COMMON-MODE VOLTAGE (V) REF MAXIMUM INPUT COMMON-MODE VOLTAGE WHEN V REF = GND SUPPLY VOLTAGE (±V) Figure 3. Input Common-Mode Voltage vs. Supply Voltage for Dual Supplies MAXIMUM INPUT COMMON-MODE VOLTAGE WHEN V REF = MIDSUPPLY 2992-C SINGLE-SUPPLY VOLTAGE (V) Figure 3. Input Common-Mode Voltage vs. Supply Voltage for Single Supplies 2992-C-34 Rev. F Page of 2

16 The differential input voltage range is constrained to the linear operation of the internal amplifiers A and A2. The voltage applied to the inputs of A and A2 should be between VS +.2 V and VS+.2 V. Similarly, the outputs of A and A2 should be kept between VS +.9 V and VS+.9 V. VOLTAGE LEVEL CONVERSION Industrial signal conditioning and control applications typically require connections between remote sensors or amplifiers and centrally located control modules. Signal conditioners provide output voltages of up to ± V full scale. However, ADCs or microprocessors operating on single 3.3 V to V logic supplies are now the norm. Thus, the controller voltages require further reduction in amplitude and reference. Furthermore, voltage potentials between locations are seldom compatible, and power line peaks and surges can generate destructive energy between utility grids. The offers an ideal solution to both problems. It attenuates otherwise destructive signal voltage peaks and surges by a factor of and shifts the differential input signal to the desired output voltage. Conversion from voltage-driven or current-loop systems is easily accomplished using the circuit shown in Figure 32. This shows a circuit for converting inputs of various polarities and amplitudes to the input of a single-supply ADC. To adjust common-mode output voltage, connect Pin 3 (VREF) and the lower end of the kω resistor to the desired voltage. The output common-mode voltage is the same as the reference voltage. Designing such an application can be done in a few simple steps, including the following: Determine the required gain. For example, if the input voltage must be transformed from ± V to V to + V, the gain is +/+2 or +.2. Determine if the circuit common-mode voltage should be changed. An AD794 ADC is illustrated for this example. When operating from a V supply, the common-mode voltage of the AD794 is half the supply, or 2. V. If the reference pin and the lower terminal of the kω resistor are connected to a 2. V voltage source, the output common-mode voltage is 2. V. Table 6 shows resistor and reference values for commonly used single-supply converter voltages. REXT3 is included as an option to balance the source impedance into A2. This is described in more detail in the Gain Adjustment section. Table 6. Nearest % Resistor Values for Voltage Level Conversion Applications Input Voltage (V) ADC Supply Voltage (V) Desired Output Voltage (V) VREF (V) REXT (kω) REXT2 (kω) ± ± ± ± Rev. F Page 6 of 2

17 +2V 2V.μF μf.μf μf +/ V 8 kω kω 7 2 +Vs Vs A A2 49.9Ω 33nF 3 V IN AD794 GND 2 SCLK SDATA VDD CS SERIAL DATA 4 6 V REF C FILT RG μF μf nf R EXT2 REFERENCE VOLTAGE R EXT kω AD866 / AD866 2/2 6 4 μf V OUT.μF 6 V IN 2 REF V Figure 32. Level Shifter CURRENT LOOP RECEIVER Analog data transmitted on a 4 to 2 ma current loop can be detected with the receiver shown in Figure 33. The is an ideal choice for such a function because the current loop is driven with a compliance voltage sufficient to stabilize the loop, and the resultant common-mode voltage often exceeds commonly used supply voltages. Note that with large shunt values, a resistance of equal value must be inserted in series with the inverting input to compensate for an error at the noninverting input. MONITORING BATTERY VOLTAGES Figure 34 illustrates how the is used to monitor a battery charger. Voltages approximately eight times the power supply voltage can be applied to the input with no damage. The resistor divider action is well-suited for the measurement of many power supply applications, such as those found in battery chargers or similar equipment. V CM = V 3 +V V Ω kω V TO V TO ADC 249Ω 8 kω I = 4 TO 2mA 2 6 kω +2.V 9.3kΩ Figure 33. Level Shifter for 4 to 2 ma Current Loop 2992-C-3 Rev. F Page 7 of 2

18 V +V S CHARGING CIRCUIT nv BAT (V) +.V BATTERY kω kω G = +. A A2 OUT R G R EXT V TO V TO ADC OTHER BATTERIES IN CHARGING CIRCUIT V S V REF C FILT 2992-C-32 Figure 34. Battery Voltage Monitor FILTER CAPACITOR VALUES Connect a capacitor to Pin 4 (CFILT) to implement a low-pass filter. The capacitor value is C =.9/ f t ( μf) where ft is the desired 3 db filter frequency. Table 7 shows several frequencies and their closest standard capacitor values. Table 7. Capacitor Values for Various Filter Frequencies Frequency (Hz) Capacitor Value (μf) k. k.33 k. KELVIN CONNECTION In certain applications, it may be desirable to connect the inverting input of an amplifier to a remote reference point. This eliminates errors resulting in circuit losses in interconnecting wiring. The is particularly suited for this type of connection. In Figure 3, a kω resistor added in the feedback matches the source impedance of A2. This is described in more detail in the Gain Adjustment section. kω kω +V S V G = +. A A2 OUT R G CIRCUIT LOSS LOAD V S V REF V S /2 C FILT 2992-C-33 Figure 3. Kelvin Connection Rev. F Page 8 of 2

19 OUTLINE DIMENSIONS (.968) 4.8 (.89) (.74) 3.8 (.497) (.244).8 (.2284) PIN.6 BSC COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters (.98). (.4) COPLANARITY..27 (.) BSC SEATING PLANE.7 (.688).3 (.32). (.2).3 (.22).2 (.98).7 (.67) 8. (.96).2 (.99) 4.27 (.).4 (.7) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Description Package Option Branding AR 4 C to +8 C 8-Lead SOIC_N R-8 AR-REEL 4 C to +8 C 8-Lead SOIC_N 3" Reel R-8 AR-REEL7 4 C to +8 C 8-Lead SOIC_N 7" Reel R-8 ARZ 4 C to +8 C 8-Lead SOIC_N R-8 ARZ-RL 4 C to +8 C 8-Lead SOIC_N 3" Reel R-8 ARZ-R7 4 C to +8 C 8-Lead SOIC_N 7" Reel R-8 ARM 4 C to +8 C 8-Lead MSOP RM-8 JGA ARM-REEL 4 C to +8 C 8-Lead MSOP 3" Reel RM-8 JGA ARM-REEL7 4 C to +8 C 8-Lead MSOP 7" Reel RM-8 JGA ARMZ 4 C to +8 C 8-Lead MSOP RM-8 JGZ ARMZ-RL 4 C to +8 C 8-Lead MSOP 3" Reel RM-8 JGZ ARMZ-R7 4 C to +8 C 8-Lead MSOP 7" Reel RM-8 JGZ -EVAL Evaluation Board Z = Pb-free part. Rev. F Page 9 of 2

20 T TTT NOTES 26 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C /6(F) Rev. F Page 2 of 2