Low Power, Wide Supply Range, Low Cost Difference Amplifiers, G = ½, 2 AD8278/AD8279

Transcription

1 Low Power, Wide Supply Range, Low Cost Difference Amplifiers, G = ½, 2 /AD8279 FEATURES Wide input range beyond supplies Rugged input overvoltage protection Low supply current: 2 μa maximum (per amplifier) Low power dissipation:. mw at VS = 2. V Bandwidth: MHz (G = ½) CMRR: 8 db minimum, dc to 2 khz (G = ½, B Grade) Low offset voltage drift: ± μv/ C maximum (B Grade) Low gain drift: ppm/ C maximum (B Grade) Enhanced slew rate:. V/μs Wide power supply range Single supply: 2 V to 3 V Dual supplies: ±2 V to ±8 V 8-lead SOIC, -lead SOIC, and 8-lead MSOP packages APPLICATIONS Voltage measurement and monitoring Current measurement and monitoring Instrumentation amplifier building block Portable, battery-powered equipment Test and measurement GENERAL DESCRIPTION The and AD8279 are general-purpose difference amplifiers intended for precision signal conditioning in power critical applications that require both high performance and low power. The and AD8279 provide exceptional commonmode rejection ratio (8 db) and high bandwidth while amplifying input signals that are well beyond the supply rails. The on-chip resistors are laser trimmed for excellent gain accuracy and high CMRR. They also have extremely low gain drift vs. temperature. The common-mode range of the amplifier extends to almost triple the supply voltage (for G = ½), making the amplifer ideal for single-supply applications that require a high commonmode voltage range. The internal resistors and ESD circuitry at the inputs also provide overvoltage protection to the op amp. The and AD8279 can be used as difference amplifiers with G = ½ or G = 2. They can also be connected in a high precision, single-ended configuration for non inverting and inverting gains of ½, 2, +3, +2, +½, +, or +½. The and AD8279 provide an integrated precision solution that has a smaller size, lower cost, and better performance than a discrete alternative. The and AD8279 operate on single supplies (2. V to 3 V) or dual supplies (±2 V to ±8 V). The maximum quiescent supply current is 2 μa, which is ideal for battery-operated and portable systems. For unity-gain difference amplifiers with similar performance, refer to the AD827 and AD8277 data sheets. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. FUNCTIONAL BLOCK DIAGRAMS +VS 7 kω 2kΩ IN 2 SENSE kω 2kΩ +IN 3 REF VS Figure. +VS One Technology Way, P.O. Box 9, Norwood, MA 22-9, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved. AD8279 kω 2kΩ INA 2 2 SENSEA 3 A +INA 3 REFA kω 2kΩ kω 2kΩ INB SENSEB +INB 8 REFB kω 2kΩ VS Figure 2. AD B Table. Difference Amplifiers by Category Low Distortion High Voltage Current Sensing Low Power AD827 AD28 AD822 (U) AD827 AD827 AD29 AD823 (U) AD8277 AD8273 AD82 (B) AD827 AD82 (B) AMP3 AD82 (B) U = unidirectional, B = bidirectional. The is available in the space-saving 8-lead MSOP and SOIC packages, and the AD8279 is offered in a -lead SOIC package. Both are specified for performance over the industrial temperature range of C to +8 C and are fully RoHS compliant

2 TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagrams... Revision History... 2 Specifications... 3 Absolute Maximum Ratings... 7 Thermal Resistance... 7 Maximum Power Dissipation... 7 Short-Circuit Current... 7 ESD Caution... 7 Pin Configurations and Function Descriptions... 8 Typical Performance Characteristics...9 Theory of Operation... Circuit Information... Driving the and AD Input Voltage Range... Power Supplies... 7 Applications Information... 8 Configurations... 8 Differential Output... 9 Instrumentation Amplifier... 9 Outline Dimensions... 2 Ordering Guide... 2 REVISION HISTORY / Rev. B to Rev. C Change to Impedance/Differential Parameter, Table 3... Change to Impedance/Differential Parameter, Table... / Rev. A to Rev. B Changed Supply Current Parameters to Supply Current Parameter and AD8279 Supply Current Parameter, Table... Updated Outline Dimensions... 2 /9 Rev. to Rev. A Added AD8279 and -Lead SOIC Model...Universal Changes to Features... Changes to General Description... Change to Table Change to Table 3... Change to Table... Change to Table... Added Figure and Table Changes to Figure 3 and Figure Changes to Figure, Figure, and Figure 2... Added Figure 7; Renumbered Sequentially... Changes to Figure to Figure Added Differential Output Section... 9 Changes to Figure Updated Outline Dimensions... 2 Changes to Ordering Guide /9 Revision : Initial Version Rev. C Page 2 of 2

3 SPECIFICATIONS VS = ± V to ± V, VREF = V, TA = 2 C, RL = kω connected to ground, G = ½ difference amplifier configuration, unless otherwise noted. /AD8279 Table 2. G = ½ Grade B Grade A Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS System Offset 2 μv Over Temperature TA = C to +8 C 2 μv vs. Power Supply VS = ± V to ±8 V 2. μv/v Average Temperature Coefficient TA = C to +8 C.3 2 μv/ C Common-Mode Rejection Ratio (RTI) VS = ± V, VCM = ±27 V, RS = Ω 8 7 db Input Voltage Range 2 3 (VS +.) +3 (VS.) 3 (VS +.) +3 (VS.) V Impedance 3 Differential 2 2 kω Common Mode 3 3 kω DYNAMIC PERFORMANCE Bandwidth MHz Slew Rate.... V/μs Channel Separation f = khz 3 3 db Settling Time to.% V step on output, CL = pf 9 9 μs Settling Time to.% μs GAIN Gain Error..2.. % Gain Drift TA = C to +8 C ppm/ C Gain Nonlinearity V = 2 V p-p 7 2 ppm PUT CHARACTERISTICS Output Voltage Swing VS = ± V, RL = kω TA = C to +8 C VS +.2 +VS.2 VS +.2 +VS.2 V Short-Circuit Current Limit ± ± ma Capacitive Load Drive 2 2 pf NOISE Output Voltage Noise f =. Hz to Hz.. μv p-p f = khz 7 7 nv/ Hz POWER SUPPLY Supply Current 2 2 μa Over Temperature TA = C to +8 C 2 2 μa AD8279 Supply Current μa Over Temperature TA = C to +8 C μa Operating Voltage Range 7 ±2 ±8 ±2 ±8 V TEMPERATURE RANGE Operating Range C Includes input bias and offset current errors, RTO (referred to output). 2 The input voltage range may also be limited by absolute maximum input voltage or by the output swing. See the Input Voltage Range for details. 3 Internal resistors are trimmed to be ratio matched and have ±2% absolute accuracy. Output voltage swing varies with supply voltage and temperature. See Figur e 22 through Figure 2 for details. Includes amplifier voltage and current noise, as well as noise from internal resistors. Supply current varies with supply voltage and temperature. See Figure 2 and Figure 28 for details. 7 Unbalanced dual supplies can be used, such as VS =. V and +VS = +2 V. The positive supply rail must be at least 2 V above the negative supply and reference voltage. Rev. C Page 3 of 2

4 VS = ± V to ± V, VREF = V, TA = 2 C, RL = kω connected to ground, G = 2 difference amplifier configuration, unless otherwise noted. Table 3. G = 2 Grade B Grade A Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS System Offset 2 μv Over Temperature TA = C to +8 C 2 μv vs. Power Supply VS = ± V to ±8 V μv/v Average Temperature Coefficient TA = C to +8 C. 2 2 μv/ C Common-Mode Rejection Ratio (RTI) VS = ± V, VCM = ±27 V, RS = Ω 8 8 db Input Voltage Range 2. (VS +.) +. (VS.). (VS +.) +. (VS.) V Impedance 3 Differential 3 3 kω Common Mode 3 3 kω DYNAMIC PERFORMANCE Bandwidth khz Slew Rate.... V/μs Channel Separation f = khz 3 3 db Settling Time to.% V step on output, CL = pf μs Settling Time to.% μs GAIN Gain Error..2.. % Gain Drift TA = C to +8 C ppm/ C Gain Nonlinearity V = 2 V p-p 7 2 ppm PUT CHARACTERISTICS Output Voltage Swing VS = ± V, RL = kω, TA = C to +8 C VS +.2 +VS.2 VS +.2 +VS.2 V Short-Circuit Current Limit ± ± ma Capacitive Load Drive 3 3 pf NOISE Output Voltage Noise f =. Hz to Hz μv p-p f = khz nv/ Hz POWER SUPPLY Supply Current 2 2 μa Over Temperature TA = C to +8 C 2 2 μa AD8279 Supply Current μa Over Temperature TA = C to +8 C μa Operating Voltage Range 7 ±2 ±8 ±2 ±8 V TEMPERATURE RANGE Operating Range C Includes input bias and offset current errors, RTO (referred to output). 2 The input voltage range may also be limited by absolute maximum input voltage or by the output swing. See the Input Voltage Range section for details. 3 Internal resistors are trimmed to be ratio matched and have ±2% absolute accuracy. Output voltage swing varies with supply voltage and temperature. See Figur e 22 through Figure 2 for details. Includes amplifier voltage and current noise, as well as noise from internal resistors. Supply current varies with supply voltage and temperature. See Figure 2 and Figure 28 for details. 7 Unbalanced dual supplies can be used, such as VS =. V and +VS = +2 V. The positive supply rail must be at least 2 V above the negative supply and reference voltage. Rev. C Page of 2

5 VS = +2.7 V to <± V, VREF = midsupply, TA = 2 C, RL = kω connected to midsupply, G = ½ difference amplifier configuration, unless otherwise noted. Table. G = ½ Grade B Grade A Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS System Offset μv Over Temperature TA = C to +8 C 2 μv vs. Power Supply VS = ± V to ±8 V 2. μv/v Average Temperature Coefficient TA = C to +8 C.3 2 μv/ C Common-Mode Rejection Ratio (RTI) VS = 2.7 V, VCM = V to 2. V, RS = Ω 8 7 db VS = ± V, VCM = V to +7 V, RS = Ω 8 7 db Input Voltage Range 2 3 (VS +.) +3 (VS.) 3 (VS +.) +3 (VS.) V Impedance 3 Differential 2 2 kω Common Mode 3 3 kω DYNAMIC PERFORMANCE Bandwidth khz Slew Rate.3.3 V/μs Channel Separation f = khz 3 3 db Settling Time to.% 2 V step on output, CL = pf, VS = 2.7 V 7 7 μs GAIN Gain Error..2.. % Gain Drift TA = C to +8 C ppm/ C PUT CHARACTERISTICS Output Swing RL = kω, TA = C to +8 C VS +. +VS. VS +. +VS. V Short-Circuit Current Limit ± ± ma Capacitive Load Drive 2 2 pf NOISE Output Voltage Noise f =. Hz to Hz.. μv p-p f = khz 7 7 nv/ Hz POWER SUPPLY Supply Current TA = C to +8 C 2 2 μa AD8279 Supply Current TA = C to +8 C μa Operating Voltage Range V TEMPERATURE RANGE Operating Range C Includes input bias and offset current errors, RTO (referred to output). 2 The input voltage range may also be limited by absolute maximum input voltage or by the output swing. See the Input Voltage Range section for details. 3 Internal resistors are trimmed to be ratio matched and have ±2% absolute accuracy. Output voltage swing varies with supply voltage and temperature. See Figur e 22 through Figure 2 for details. Includes amplifier voltage and current noise, as well as noise from internal resistors. Supply current varies with supply voltage and temperature. See Figure 27 and Figure 28 for details. Rev. C Page of 2

6 VS = +2.7 V to <± V, VREF = midsupply, TA = 2 C, RL = kω connected to midsupply, G = 2 difference amplifier configuration, unless otherwise noted. Table. G = 2 Grade B Grade A Parameter Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS System Offset 3 μv Over Temperature TA = C to +8 C 3 μv vs. Power Supply VS = ± V to ±8 V μv/v Average Temperature Coefficient TA = C to +8 C. 2 3 μv/ C Common-Mode Rejection Ratio (RTI) VS = 2.7 V, VCM = V to 2. V, RS = Ω 8 8 db VS = ± V, VCM = V to +7 V, RS = Ω 8 8 db Input Voltage Range 2. (VS +.) +. (VS.). (VS +.) +. (VS.) V Impedance 3 Differential 3 3 kω Common Mode 3 3 kω DYNAMIC PERFORMANCE Bandwidth khz Slew Rate.3.3 V/μs Channel Separation f = khz 3 3 db Settling Time to.% 2 V step on output, CL = pf, VS = 2.7 V 9 9 μs GAIN Gain Error..2.. % Gain Drift TA = C to +8 C ppm/ C PUT CHARACTERISTICS Output Swing RL = kω, TA = C to +8 C VS +. +VS. VS +. +VS. V Short-Circuit Current Limit ± ± ma Capacitive Load Drive 2 2 pf NOISE Output Voltage Noise f =. Hz to Hz μv p-p f = khz 9 9 nv/ Hz POWER SUPPLY Supply Current TA = C to +8 C 2 2 μa AD8279 Supply Current TA = C to +8 C μa Operating Voltage Range V TEMPERATURE RANGE Operating Range C Includes input bias and offset current errors, RTO (referred to output). 2 The input voltage range may also be limited by absolute maximum input voltage or by the output swing. See the Input Voltage Range section for details. 3 Internal resistors are trimmed to be ratio matched and have ±2% absolute accuracy. Output voltage swing varies with supply voltage and temperature. See Figur e 22 through Figure 2 for details. Includes amplifier voltage and current noise, as well as noise from internal resistors. Supply current varies with supply voltage and temperature. See Figure 27 and Figure 28 for details. Rev. C Page of 2

7 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ±8 V Maximum Voltage at Any Input Pin VS + V Minimum Voltage at Any Input Pin +VS V Storage Temperature Range C to + C Specified Temperature Range C to +8 C Package Glass Transition Temperature (TG) C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The θja values in Table 7 assume a -layer JEDEC standard board with zero airflow. Table 7. Thermal Resistance Package Type θja Unit 8-Lead MSOP 3 C/W 8-Lead SOIC 2 C/W -Lead SOIC C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation for the and AD8279 are limited by the associated rise in junction temperature (TJ) on the die. At approximately C, which is the glass transition temperature, the properties of the plastic change. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of C for an extended period may result in a loss of functionality. MAXIMUM POWER DISSIPATION (W) MSOP θ JA = 3 C/W SOIC θ JA = 2 C/W AMBIENT TEMERATURE ( C) T J MAX = C Figure 3. Maximum Power Dissipation vs. Ambient Temperature SHORT-CIRCUIT CURRENT The and AD8279 have built-in, short-circuit protection that limits the output current (see Figure 29 for more information). While the short-circuit condition itself does not damage the part, the heat generated by the condition can cause the part to exceed its maximum junction temperature, with corresponding negative effects on reliability. Figure 3 and Figure 29, combined with knowledge of the supply voltages and ambient temperature of the part, can be used to determine whether a short circuit will cause the part to exceed its maximum junction temperature. ESD CAUTION Rev. C Page 7 of 2

8 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF IN 2 +IN 3 VS TOP VIEW (Not to Scale) NC = NO CONNECT 8 7 NC +VS SENSE Figure. MSOP Pin Configuration REF IN 2 +IN 3 VS TOP VIEW (Not to Scale) NC = NO CONNECT 8 7 NC +VS SENSE Figure. SOIC Pin Configuration 838- Table 8. Pin Function Descriptions Pin No. Mnemonic Description REF Reference Voltage Input. 2 IN Inverting Input. 3 +IN Noninverting Input. VS Negative Supply. SENSE Sense Terminal. Output. 7 +VS Positive Supply. 8 NC No Connect. NC REFA INA 2 3 A +INA 3 AD SENSEA VS +VS +INB TOP VIEW (Not to Scale) SENSEB INB 9 B NC 7 8 REFB NC = NO CONNECT Figure. -Lead SOIC Pin Configuration Table 9. AD8279 Pin Function Descriptions Pin No. Mnemonic Description NC No Connect. 2 INA Channel A Inverting Input. 3 +INA Channel A Noninverting Input. VS Negative Supply. +INB Channel B Noninverting Input. INB Channel B Inverting Input. 7 NC No Connect. 8 REFB Channel B Reference Voltage Input. 9 B Channel B Output. SENSEB Channel B Sense Terminal. +VS Positive Supply. 2 SENSEA Channel A Sense Terminal. 3 A Channel A Output. REFA Channel A Reference Voltage Input. Rev. C Page 8 of 2

9 TYPICAL PERFORMANCE CHARACTERISTICS VS = ± V, TA = 2 C, RL = kω connected to ground, G = ½ difference amplifier configuration, unless otherwise noted. /AD8279 N = 38 MEAN =.8 SD = NUMBER OF HITS 3 2 SYSTEM OFFSET (µv) 2 2 SYSTEM OFFSET VOLTAGE (µv) Figure 7. Distribution of Typical System Offset Voltage, G = REPRESENTATIVE DATA TEMPERATURE ( C) Figure. System Offset vs. Temperature, Normalized at 2, G = ½ NUMBER OF HITS N = 3837 MEAN = 7.78 SD = CMRR (µv/v) Figure 8. Distribution of Typical Common-Mode Rejection, G = GAIN ERROR (µv/v) REPRESENTATIVE DATA TEMPERATURE ( C) Figure. Gain Error vs. Temperature, Normalized at 2 C, G = ½ V S = ±V CMRR (µv/v) COMMON-MODE VOLTAGE (V) 2 V S = ±V REPRESENTATIVE DATA TEMPERATURE ( C) Figure 9. CMRR vs. Temperature, Normalized at 2 C, G = ½ PUT VOLTAGE (V) Figure 2. Input Common-Mode Voltage vs. Output Voltage, ± V and ± V Supplies, G = ½ 838- Rev. C Page 9 of 2

10 COMMON-MODE VOLTAGE (V) V S = 2.7V V S = V V REF = MIDSUPPLY COMMON-MODE VOLTAGE (V) 3 2 V S = 2.7V V S = V V REF = MIDSUPPLY PUT VOLTAGE (V) Figure 3. Input Common-Mode Voltage vs. Output Voltage, V and 2.7 V Supplies, VREF = Midsupply, G = ½ PUT VOLTAGE (V) Figure. Input Common-Mode Voltage vs. Output Voltage, V and 2.7 V Supplies, VREF = Midsupply, G = V S = V V REF = V V S = V V REF = V COMMON-MODE VOLTAGE (V) V S = 2.7V COMMON-MODE VOLTAGE (V) 3 2 V S = 2.7V PUT VOLTAGE (V) Figure. Input Common-Mode Voltage vs. Output Voltage, V and 2.7 V Supplies, VREF = V, G = ½ PUT VOLTAGE (V) Figure 7. Input Common-Mode Voltage vs. Output Voltage, V and 2.7 V Supplies, VREF = V, G = COMMON-MODE VOLTAGE (V) 2 2 V S = ±V V S = ±V GAIN (db) GAIN = 2 GAIN = ½ PUT VOLTAGE (V) Figure. Input Common-Mode Voltage vs. Output Voltage, ± V and ± V Supplies, G = k k k M M FREQUENCY (Hz) Figure 8. Gain vs. Frequency, ± V Supplies 838- Rev. C Page of 2

11 8 +V S 2. GAIN (db) GAIN = 2 GAIN = ½ PUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES T A = C T A = +2 C T A = +8 C T A = +2 C 3 +. CMRR (db) 3 k k k M M FREQUENCY (Hz) Figure 9. Gain vs. Frequency, +2.7 V Single Supply 2 GAIN = 2 GAIN = ½ 8 2 k k k M FREQUENCY (Hz) Figure 2. CMRR vs. Frequency V S SUPPLY VOLTAGE (±V S ) Figure 22. Output Voltage Swing vs. Supply Voltage and Temperature, RL = kω PUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +V S V S SUPPLY VOLTAGE (±V S ) T A = C T A = +2 C T A = +8 C T A = +2 C Figure 23. Output Voltage Swing vs. Supply Voltage and Temperature, RL = 2 kω +V S PSRR (db) 8 2 +PSRR PSRR PUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES T A = C T A = +2 C T A = +8 C T A = +2 C k k k M FREQUENCY (Hz) V S k k LOAD RESISTANCE (Ω) k Figure 2. PSRR vs. Frequency Figure 2. Output Voltage Swing vs. RL and Temperature, VS = ± V Rev. C Page of 2

12 +V S. 2 V REF = MIDSUPPLY PUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES T A = C T A = +2 C T A = +8 C T A = +2 C SUPPLY CURRENT (µa) 2 V S = ±V V S = +2.7V +. V S PUT CURRENT (ma) Figure 2. Output Voltage Swing vs. I and Temperature, VS = ± V TEMPERATURE ( C) Figure 28. Supply Current per Channel vs. Temperature SUPPLY CURRENT (µa) 7 3 SHORT-CIRCUIT CURRENT (ma) 2 I SHORT+ I SHORT SUPPLY VOLTAGE (±V) Figure 2. Supply Current per Channel vs. Dual-Supply Voltage, VIN = V TEMPERATURE ( C) Figure 29. Short-Circuit Current per Channel vs. Temperature SLEW RATE 7. SUPPLY CURRENT (µa) SLEW RATE (V/µs) SLEW RATE SUPPLY VOLTAGE (V) Figure 27. Supply Current per Channel vs. Single-Supply Voltage, VIN = V, VREF = V TEMPERATURE ( C) Figure 3. Slew Rate vs. Temperature, VIN = 2 V p-p, khz Rev. C Page 2 of 2

13 8 NONLINEARITY (2ppm/DIV) 2 2 V/DIV.2%/DIV 3.µs TO.%.2µs TO.% PUT VOLTAGE (V) Figure 3. Gain Nonlinearity, VS = ± V, RL 2 kω, G = ½ TIME (µs) µs/div Figure 3. Large Signal Pulse Response and Settling Time, 2 V Step, VS = 2.7 V, G = ½ NONLINEARITY (2ppm/DIV) V/DIV.2%/DIV 7.µs TO.% 9.8µs TO.% PUT VOLTAGE (V) TIME (µs) µs/div Figure 32. Gain Nonlinearity, VS = ± V, RL 2 kω, G = 2 Figure 3. Large Signal Pulse Response and Settling Time, V Step, VS = ± V, G = 2 V/DIV V/DIV.2µs TO.% 7.92µs TO.%.3µs TO.%.2µs TO.%.2%/DIV.2%/DIV TIME (µs) µs/div Figure 33. Large Signal Pulse Response and Settling Time, V Step, VS = ± V, G = ½ TIME (µs) µs/div Figure 3. Large Signal Pulse Response and Settling Time, 2 V Step, VS = 2.7 V Rev. C Page 3 of 2

14 .. V S = V. 2V/DIV PUT VOLTAGE (V p-p) V S = 2.7V µs/div Figure 37. Large Signal Step Response, G = ½ k k k M FREQUENCY (Hz) Figure. Maximum Output Voltage vs. Frequency, VS = V, 2.7 V V/DIV 2mV/DIV NO LOAD µs/div C L = pf C L = 7pF C L = 27pF µs/div Figure 38. Large Signal Step Response, G = 2 Figure. Small Signal Step Response for Various Capacitive Loads, G = ½ 3 V S = ±V 2 PUT VOLTAGE (V p-p) 2 V S = ±V k k k M FREQUENCY (Hz) Figure 39. Maximum Output Voltage vs. Frequency, VS = ± V, ± V mV/DIV C L = pf C L = 2pF C L = 27pF C L = 37pF µs/div Figure 2. Small Signal Step Response for Various Capacitive Loads, G = Rev. C Page of 2

15 GAIN = 2 OVERSHOOT (%) ±V ±2V ±8V ±V µv/div GAIN = ½ 2 2 CAPACITIVE LOAD (pf) Figure 3. Small Signal Overshoot vs. Capacitive Load, RL 2 kω, G = ½ 838- s/div Figure.. Hz to Hz Voltage Noise kΩ LOAD OVERSHOOT (%) 2 2 ±V ±2V ±8V ±V CHANNEL SEPARATION (db) CAPACITIVE LOAD (pf) Figure. Small Signal Overshoot vs. Capacitive Load, RL 2 kω, G = k k k FREQUENCY (Hz) Figure 7. Channel Separation 838- k NOISE (nv/ Hz) GAIN = 2 GAIN = ½. k k k FREQUENCY (Hz) Figure. Voltage Noise Density vs. Frequency Rev. C Page of 2

16 THEORY OF OPERATION CIRCUIT INFORMATION Each channel of the and AD8279 consists of a low power, low noise op amp and four laser-trimmed on-chip resistors. These resistors can be externally connected to make a variety of amplifier configurations, including difference, noninverting, and inverting configurations. Taking advantage of the integrated resistors of the and AD8279 provides the designer with several benefits over a discrete design, including smaller size, lower cost, and better ac and dc performance. DC Performance +VS 7 kω 2kΩ IN 2 SENSE kω 2kΩ +IN 3 REF VS Figure 8. Functional Block Diagram Much of the dc performance of op amp circuits depends on the accuracy of the surrounding resistors. Using superposition to analyze a typical difference amplifier circuit, as is shown in Figure 9, the output voltage is found to be V R2 R + V R + R2 R3 = VIN + IN 838- R R3 This equation demonstrates that the gain accuracy and commonmode rejection ratio of the and AD8279 is determined primarily by the matching of resistor ratios. Even a.% mismatch in one resistor degrades the CMRR to 9 db for a G = 2 difference amplifier. The difference amplifier output voltage equation can be reduced to = R V ( + VIN VIN ) R3 as long as the following ratio of the resistors is tightly matched: R2 R = R R3 The resistors on the and AD8279 are laser trimmed to match accurately. As a result, the and AD8279 provide superior performance over a discrete solution, enabling better CMRR, gain accuracy, and gain drift, even over a wide temperature range. AC Performance Component sizes and trace lengths are much smaller in an IC than on a PCB; therefore, the corresponding parasitic elements are also smaller. This results in better ac performance of the and AD8279. For example, the positive and negative input terminals of the and AD8279 op amps are intentionally not pinned out. By not connecting these nodes to the traces on the PCB, their capacitance remains low and balanced, resulting in improved loop stability and excellent common-mode rejection over frequency. DRIVING THE AND AD8279 Care should be taken to drive the and AD8279 with a low impedance source, for example, another amplifier. Source resistance of even a few kilohms (kω) can unbalance the resistor ratios and, therefore, significantly degrade the gain accuracy and common-mode rejection of the and AD8279. Because all configurations present several kilohms (kω) of input resistance, the and AD8279 do not require a high current drive from the source and are easy to drive. INPUT VOLTAGE RANGE The and AD8279 are able to measure input voltages beyond the supply rails. The internal resistors divide down the voltage before it reaches the internal op amp and provide protection to the op amp inputs. Figure 9 shows an example of how the voltage division works in a difference amplifier configuration. For the and AD8279 to measure correctly, the input voltages at the input nodes of the internal op amp must stay below. V of the positive supply rail and can exceed the negative supply rail by. V. Refer to the Power Supplies section for more details. R2 R + R2 (V IN+ ) V IN V IN+ R3 R R2 R2 R + R2 (V IN+ ) Figure 9. Voltage Division in the Difference Amplifier Configuration The and AD8279 have integrated ESD diodes at the inputs that provide overvoltage protection. This feature simplifies system design by eliminating the need for additional external protection circuitry and enables a more robust system. The voltages at any of the inputs of the parts can safely range from +VS V up to VS + V. For example, on ± V supplies, input voltages can go as high as ±3 V. Care should be taken to not exceed the +VS V to VS + V input limits to avoid damaging the parts. R Rev. C Page of 2

17 POWER SUPPLIES The and AD8279 operate extremely well over a very wide range of supply voltages. They can operate on a single supply as low as 2 V and as high as 3 V, under appropriate setup conditions. For best performance, the user should ensure that the internal op amp is biased correctly. The internal input terminals of the op amp must have sufficient voltage headroom to operate properly. Proper operation of the part requires at least. V between the positive supply rail and the op amp input terminals. This relationship is expressed in the following equation: R V REF < + V S. V R + R2 For example, when operating on a +VS= 2 V single supply and VREF = V, it can be seen from Figure that the op amp input terminals are biased at V, allowing more than the required. V headroom. However, if VREF = V under the same conditions, the input terminals of the op amp are biased at. V (G = ½). Now the op amp does not have the required. V headroom and cannot function. Therefore, the user must increase the supply voltage or decrease VREF to restore proper operation. The and AD8279 are typically specified at single and dual supplies, but they can be used with unbalanced supplies as well; for example, VS = V, +VS = +2 V. The difference between the two supplies must be kept below 3 V. The positive supply rail must be at least 2 V above the negative supply. R R + R2 (V REF ) R3 R R2 V REF R R + R2 (V REF ) Figure. Ensure Sufficient Voltage Headroom on the Internal Op Amp Inputs Use a stable dc voltage to power the and AD8279. Noise on the supply pins can adversely affect performance. Place a bypass capacitor of. μf between each supply pin and ground, as close as possible to each supply pin. Use a tantalum capacitor of μf between each supply and ground. It can be farther away from the supply pins and, typically, it can be shared by other precision integrated circuits. R 838- Rev. C Page 7 of 2

18 APPLICATIONS INFORMATION CONFIGURATIONS The and AD8279 can be configured in several ways (see Figure to Figure 7). These configurations have excellent gain accuracy and gain drift because they rely on the internal matched resistors. Note that Figure 3 shows the and AD8279 as difference amplifiers with a midsupply reference voltage at the noninverting input. This allows the and AD8279 to be used as a level shifter, which is appropriate in single-supply applications that are referenced to midsupply. Table lists several single-ended amplifier configurations that are not illustrated. IN +IN IN +IN 2 3 kω kω V = ½ (V IN+ V IN ) 2kΩ 2kΩ Figure. Difference Amplifier, Gain = ½ IN +IN 2kΩ 2kΩ V = 2(V IN+ V IN ) kω kω 2 3 Figure 2. Difference Amplifier, Gain = kω kω 2kΩ 2kΩ V = ½ (V IN+ V IN ) + V REF V REF = MIDSUPPLY Figure 3. Difference Amplifier, Gain = ½, Referenced to Midsupply kΩ kω 2 IN +IN 2kΩ kω 3 V = 2 (V IN+ V IN ) + V REF V REF = MIDSUPPLY Figure. Difference Amplifier, Gain = 2, Referenced to Midsupply 2 kω 2kΩ IN 3 V = ½V IN 2kΩ kω Figure. Inverting Amplifier, Gain = ½ 2 kω 2kΩ 2kΩ IN 3 kω V =.V IN Figure. Noninverting Amplifier, Gain =. 2kΩ kω 2 2kΩ kω 3 IN V = 2V IN Figure 7. Noninverting Amplifier, Gain = Table. Difference and Single-Ended Amplifier Configurations Amplifier Configuration Signal Gain Pin (REF) Pin 2 (VIN ) Pin 3 (VIN+) Pin (SENSE) Difference Amplifier +½ GND IN IN+ Difference Amplifier +2 IN+ GND IN Single-Ended Inverting Amplifier ½ GND IN GND Single-Ended Inverting Amplifier 2 GND GND IN Single-Ended Noninverting Amplifier +3 2 IN GND IN Single-Ended Noninverting Amplifier +3 IN IN GND Single-Ended Noninverting Amplifier +½ GND GND IN Single-Ended Noninverting Amplifier + IN GND GND Single-Ended Noninverting Amplifier + GND IN GND Single-Ended Noninverting Amplifier +2 IN GND GND Rev. C Page 8 of 2

19 The reference must be driven with a low impedance source to maintain the internal resistor ratio. An example using the low power, low noise OP77 as a reference is shown in Figure 8. V INCORRECT REF DIFFERENTIAL PUT V CORRECT + OP77 REF Figure 8. Driving the Reference Pin The two difference amplifiers of the AD8279 can be configured to provide a differential output, as shown in Figure 9. This differential output configuration is suitable for various applications, such as strain gage excitation and single-ended-to-differential conversion. The differential output voltage has a gain twice that of a single AD8279 channel, as shown in the following equation: VDIFF_ = V+ V = 2 GAD8279 (VIN+ VIN ) If the AD8279 amplifiers are each configured for G = ½, the differential gain is ; if the AD8279 amplifiers are each configured for G = 2, the differential gain is. IN +IN +VS AD8279 2kΩ kω kΩ kω 3 2kΩ kω INSTRUMENTATION AMPLIFIER The and AD8279 can be used as building blocks for a low power, low cost instrumentation amplifier. An instrumentation amplifier provides high impedance inputs and delivers high common-mode rejection. Combining the with an Analog Devices, Inc., low power amplifier (see Table ) creates a precise, power efficient voltage measurement solution suitable for power critical systems. IN +IN R G A A2 R F R F 2kΩ 2kΩ kω REF kω / AD8279 V V = ( + 2R F /R G ) (V IN+ V IN ) 2 Figure. Low Power Precision Instrumentation Amplifier Table. Low Power Op Amps Op Amp (A, A2) Features AD8 Dual micropower op amp AD87 Precision dual micropower op amp AD87 Low cost CMOS micropower op amp AD87 Dual precision CMOS micropower op amp It is preferable to use dual op amps for the high impedance inputs because they have better matched performance and track each other over temperature. The and AD8279 difference amplifiers cancel out common-mode errors from the input op amps, if they track each other. The differential gain accuracy of the in-amp is proportional to how well the input feedback resistors (RF) match each other. The CMRR of the in-amp increases as the differential gain is increased ( + 2RF/RG), but a higher gain also reduces the common-mode voltage range. Refer to A Designer s Guide to Instrumentation Amplifiers for more design ideas and considerations at under Technical Documentation kΩ kω 8 VS Figure 9. AD8279 Differential Output G = Configuration 838- Rev. C Page 9 of 2

20 LINE DIMENSIONS. (.98).8 (.89). (.7) 3.8 (.97) 8.2 (.2).8 (.228).2 (.98). (.) COPLANARITY. SEATING PLANE.27 (.) BSC.7 (.88).3 (.32). (.2).3 (.22) 8.2 (.98).7 (.7). (.9).2 (.99).27 (.). (.7) COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 27-A PIN IDENTIFIER. BSC COPLANARITY...2. MAX MAX.23.9 COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure 2. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters B Rev. C Page 2 of 2

21 8.7 (.3) 8. (.33). (.7) 3.8 (.9) (.2).8 (.2283).2 (.98). (.39) COPLANARITY..27 (.) BSC. (.2).3 (.22).7 (.89).3 (.3) SEATING PLANE 8.2 (.98).7 (.7). (.97).2 (.98).27 (.). (.7) COMPLIANT TO JEDEC STANDARDS MS-2-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 3. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) -A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ARZ C to +8 C 8-Lead SOIC_N R-8 ARZ-R7 C to +8 C 8-Lead SOIC_N, 7" Tape and Reel R-8 ARZ-RL C to +8 C 8-Lead SOIC_N, 3" Tape and Reel R-8 BRZ C to +8 C 8-Lead SOIC_N R-8 BRZ-R7 C to +8 C 8-Lead SOIC_N, 7" Tape and Reel R-8 BRZ-RL C to +8 C 8-Lead SOIC_N, 3" Tape and Reel R-8 ARMZ C to +8 C 8-Lead MSOP RM-8 Y2 ARMZ-R7 C to +8 C 8-Lead MSOP, 7" Tape and Reel RM-8 Y2 ARMZ-RL C to +8 C 8-Lead MSOP, 3" Tape and Reel RM-8 Y2 BRMZ C to +8 C 8-Lead MSOP RM-8 Y22 BRMZ-R7 C to +8 C 8-Lead MSOP, 7" Tape and Reel RM-8 Y22 BRMZ-RL C to +8 C 8-Lead MSOP, 3" Tape and Reel RM-8 Y22 AD8279ARZ C to +8 C -Lead SOIC_N R- AD8279ARZ-R7 C to +8 C -Lead SOIC_N, 7" Tape and Reel R- AD8279ARZ-RL C to +8 C -Lead SOIC_N, 3" Tape and Reel R- AD8279BRZ C to +8 C -Lead SOIC_N R- AD8279BRZ-R7 C to +8 C -Lead SOIC_N, 7" Tape and Reel R- AD8279BRZ-RL C to +8 C -Lead SOIC_N, 3" Tape and Reel R- Z = RoHS Compliant Part. Rev. C Page 2 of 2

22 NOTES Rev. C Page 22 of 2

23 NOTES Rev. C Page 23 of 2

24 NOTES 29 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D838--/(C) Rev. C Page 2 of 2