Single-Supply, Low Cost Instrumentation Amplifier AD8223

Transcription

1 Single-Supply, Low Cost Instrumentation Amplifier FEATURES Gain set with resistor Gain = 5 to Inputs Voltage range to 5 mv below negative rail 5 na maximum input bias current 3 nv/ Hz, RTI khz Power supplies Dual supply: ± V to ± V Single supply: 3 V to 4 V 5 μa maximum supply current APPLICATIONS Low power medical instrumentation Transducer interface Thermocouple amplifiers Industrial process controls Difference amplifiers Low power data acquisition CONNECTION DIAGRAM IN IN 3 V S V S OUT Figure. 8-Lead SOIC (R) and 8-Lead MSOP (RM) Packages Table. Instrumentation Amplifiers by Category General- Purpose Zero Drift Mil Grade Low Power 695- High Voltage PGA AD8 AD83 AD6 AD67 AD85 AD8 AD8553 AD6 AD63 AD85 AD8 AD8555 AD54 AD853 AD84 AD8556 AD56 AD88 AD8557 AD64 Rail-to-rail output. GENERAL DESCRIPTION The is an integrated single-supply instrumentation amplifier that delivers rail-to-rail output swing on a single supply (3 V to 4 V). The conforms to the 8-lead industry standard pinout configuration. The is simple to use: one resistor sets the gain. With no external resistor, the is configured for G = 5. With an external resistor, the can be programmed for gains up to. The has a wide input common-mode range and can amplify signals that have a 5 mv common-mode voltage below ground. Although the design of the is optimized to operate from a single supply, the still provides excellent performance when operated from a dual voltage supply (± V to ± V). Low power consumption (.5 mw at 3 V), wide supply voltage range, and rail-to-rail output swing make the ideal for battery-powered applications. The rail-to-rail output stage maximizes the dynamic range when operating from low supply voltages. The replaces discrete instrumentation amplifier designs and offers superior linearity, temperature stability, and reliability in a minimum of space. Rev. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Connection Diagram... General Description... Revision History... Specifications... 3 Single Supply... 3 Dual Supply... 5 Absolute Maximum Ratings... 7 Thermal Resistance... 7 ESD Caution... 7 Pin Configuration and Function Descriptions... 8 Typical Performance Characteristics... 9 Theory of Operation... 4 Amplifier Architecture... 4 Gain Selection... 4 Input Voltage Range... 4 Reference Terminal... 5 Input Protection... 5 RF Interference (RFI)... 5 Ground Returns for Input Bias Currents... 6 Applications Information... 7 Basic Connection... 7 Differential Output... 7 Output Buffering... 7 Cables... 7 A Single-Supply Data Acquisition System... 8 Amplifying Signals with Low Common-Mode Voltage... 8 Outline Dimensions... 9 Ordering Guide... REVISION HISTORY /8 Revision : Initial Version Rev. Page of

3 SPECIFICATIONS SINGLE SUPPLY TA = 5 C, VS = V, VS = 5 V, and RL = kω to.5 V, unless otherwise noted. Table A B Parameter Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO DC to 6 Hz with kω Source VCM = V to 3 V Imbalance G = db G = 86 9 db G = 9 96 db G = 9 96 db NOISE VIN = VIN = V = V Voltage Noise, khz G = nv/ Hz G = 3 3 nv/ Hz RTI,. Hz to Hz G = 5.. μv p-p G =.6.6 μv p-p Current Noise, khz 7 7 fa/ Hz. Hz to Hz.. pa p-p VOLTAGE OFFSET Total RTI error = VOSI VOSO/G Input Offset, VOSI 5 μv Over Temperature TA = 4 C to 85 C 4 6 μv Average TC TA = 4 C to 85 C μv/ C Output Offset, VOSO 5 μv Over Temperature TA = 4 C to 85 C 5 μv Average TC TA = 4 C to 85 C 5 μv/ C Offset Referred to Input vs. Supply (PSR) VS = 4 V to 4 V, VS = V G = db G = 86 9 db G = 9 96 db G = 9 96 db INPUT CURRENT Input Bias Current na Over Temperature TA = 4 C to 85 C na Average Temperature TA = 4 C to 85 C 5 5 pa/ C Coefficient Input Offset Current.5.5 na Over Temperature TA = 4 C to 85 C.5.5 na Average Temperature TA = 4 C to 85 C 5 5 pa/ C Coefficient DYNAMIC RESPONSE Small Signal 3 db Bandwidth G = khz G = 5 5 khz G = 5 5 khz G = 5 5 khz Slew Rate.. V/μs Rev. Page 3 of

4 A B Parameter Conditions Min Typ Max Min Typ Max Unit Settling Time to.% Step size = 3.5 V G = μs G = 8 8 μs G = 8 8 μs G = μs GAIN G = 5 (8 kω/rg) Gain Range 5 5 V/V Gain Error VOUT =.5 V to 4.5 V G = 5.7. % G =..3.. % G = % G = % Nonlinearity VOUT =.5 V to 4.5 V G = 5 ppm G = ppm Gain vs. Temperature TA = 4 C to 85 C G = 5 ppm/ C G > ppm/ C INPUT Input Impedance Differential GΩ pf Common-Mode GΩ pf Common-Mode Input Voltage VIN = VIN ( VS) (VS) ( VS) (VS) V Range OUTPUT Output Swing RL = kω to ground. (VS).5. (VS).5 V ERENCE INPUT RL = kω to ground. (VS).5. (VS).5 RIN 6 ±% 6 ±% kω IIN VIN = VIN = V = V μa Voltage Range VS VS VS VS V Gain to Output ±. ±. POWER SUPPLY Operating Range V Quiescent Current μa Over Temperature TA = 4 C to 85 C 6 6 μa TEMPERATURE RANGE For Specified Performance C Does not include effects of external resistor, RG. Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 8 through Figure, and the Input Voltage Range section in the Theory of Operation section for more information. V V Rev. Page 4 of

5 DUAL SUPPLY TA = 5 C, VS = V, VS = V, and RL = kω to ground, unless otherwise noted. Table 3. A B Parameter Conditions Min Typ Max Min Typ Max Unit COMMON-MODE REJECTION RATIO DC to 6 Hz with kω Source VCM = V to V Imbalance G = db G = 86 9 db G = 9 96 db G = 9 96 db NOISE VIN = VIN = V = V Voltage Noise, khz G = nv/ Hz G = 3 3 nv/ Hz RTI,. Hz to Hz G = 5.. μv p-p G =.6.6 μv p-p Current Noise, khz 7 7 fa/ Hz. Hz to Hz.. pa p-p VOLTAGE OFFSET Total RTI error = VOSI VOSO/G Input Offset, VOSI 5 μv Over Temperature TA = 4 C to 85 C 4 6 μv Average TC TA = 4 C to 85 C μv/ C Output Offset, VOSO 5 μv Over Temperature TA = 4 C to 85 C 5 μv Average TC TA = 4 C to 85 C 5 μv/ C Offset Referred to Input vs. Supply (PSR) VS = 5 V to V, VS = 5 V to V G = db G = 86 9 db G = 9 96 db G = 9 96 db INPUT CURRENT Input Bias Current na Over Temperature TA = 4 C to 85 C na Average Temperature TA = 4 C to 85 C 5 5 pa/ C Coefficient Input Offset Current.5.5 na Over Temperature TA = 4 C to 85 C.5.5 na Average Temperature TA = 4 C to 85 C 5 5 pa/ C Coefficient DYNAMIC RESPONSE Small Signal 3 db Bandwidth G = 5 khz G = khz G = 7 7 khz G = 7 7 khz Slew Rate.3.3 V/μs Settling Time to.% Step size = V G = μs G = 3 3 μs G = 3 3 μs G = 5 5 μs Rev. Page 5 of

6 A B Parameter Conditions Min Typ Max Min Typ Max Unit GAIN G = 5 (8 kω/rg) Gain Range 5 5 V/V Gain Error VOUT = V to V G = 5.7. % G =..3.. % G = % G = % Nonlinearity VOUT = V to V G = ppm G = 3 3 ppm Gain vs. Temperature TA = 4 C to 85 C G = 5 ppm/ C G > ppm/ C INPUT Input Impedance Differential GΩ pf Common-Mode GΩ pf Common-Mode Input Voltage VIN = VIN ( VS) (VS) ( VS) (VS) V Range OUTPUT Output Swing RL = kω to ground ( VS).3 (VS).8 ( VS).3 (VS).8 V ERENCE INPUT RL = kω to ground ( VS). (VS).3 ( VS). (VS).3 RIN 6 ±% 6 ±% kω IIN VIN = VIN = V = V μa Voltage Range VS VS VS VS V Gain to Output ±. ±. POWER SUPPLY Operating Range ± ± ± ± V Quiescent Current μa Over Temperature TA = 4 C to 85 C μa TEMPERATURE RANGE For Specified Performance C Because maximum supply voltage is 4 V between the negative and positive supply, these specifications at ±V are at the part s limit. Operation at a nominal supply voltage slightly less than ± V is recommended to allow for power supply tolerances. Does not include effects of external resistor, RG. 3 Total input range depends on common-mode voltage, differential voltage, and gain. See Figure 8 through Figure and the Input Voltage Range section in the Theory of Operation section for more information. V V Rev. Page 6 of

7 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage ± V Internal Power Dissipation 65 mw Differential Input Voltage ±VS Output Short-Circuit Duration Indefinite Storage Temperature Range (R, RM) 65 C to 5 C Operating Temperature Range 4 C to 85 C Lead Temperature (Soldering, sec) 3 C ESD (Human Body Model).5 kv ESD (Charge Device Model) 5 V ESD (Machine Model) V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Specification is for the device in free air. Table 5. Thermal Resistance Package Type θja Unit 8-Lead SOIC (R) 55 C/W 8-Lead MSOP (RM) C/W ESD CAUTION Rev. Page 7 of

8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 IN IN 3 V S 4 TOP VIEW (Not to Scale) V S OUT 695- Figure. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Descriptions RG Gain Resistor Terminal. IN Negative Input. 3 IN Positive Input. 4 VS Negative Supply. 5 Reference. Connect to a low impedance source. Output is referenced to this node. 6 OUT Output. 7 VS Positive Supply. 8 RG Gain Resistor Terminal. Rev. Page 8 of

9 TYPICAL PERFORMANCE CHARACTERISTICS TA = 5 C, VS = ±5 V, RL = kω, unless otherwise noted. 7 N = 47 MEAN =.9448 SD = NUMBER OF UNITS INPUT BIAS CURRENT (na) Figure 3. Typical Distribution of Input Bias Current VOLTAGE NOISE DENSITY (nv/ Hz) G = 5 G = G = BW LIMIT G =. k BW LIMIT k k FREQUENCY (Hz) Figure 6. Voltage Noise Density vs. Frequency N = 47 MEAN =.5757 SD =.78 5 NUMBER OF UNITS I BIAS (na) INPUT OFFSET CURRENT (na) Figure 4. Typical Distribution of Input Offset Current TEMPERATURE ( C) Figure 7. IBIAS vs. Temperature NUMBER OF UNITS GAIN ERROR, G = 5 (%) N = 536 MEAN = SD =.5548 Figure 5. Typical Distribution for Gain Error (G = 5) CURRENT NOISE DENSITY (fa/ Hz).. k FREQUENCY (Hz) Figure 8. Current Noise Density vs. Frequency Rev. Page 9 of

10 8 6 4 ±V S = ±V ±V S = ±5V ±V S = ±.5V 9 G = G = 5 G = G = I BIAS (na) 8 CMRR (db) k k k CMV (V) Figure 9. IBIAS vs. CMV FREQUENCY (Hz) Figure. CMRR vs. Frequency, ±VS = ± G = 9 G = 5 G = G = CMRR (db) fA/DIV Figure.. Hz to Hz Current Noise s/div k k k FREQUENCY (Hz) Figure 3. CMRR vs. Frequency, VS = 5 V G = G = G = G = 5 GAIN (db) 3 G = G = 5.5µV/DIV s/div Figure.. Hz to Hz RTI and RTO Voltage Noise k k k M FREQUENCY (Hz) Figure 4. Gain vs. Frequency, ±VS = ± V Rev. Page of

11 7 6 G = 4 3 ±V S = ±5V GAIN (db) G = G = G = 5 COMMON-MODE INPUT (V) 3 4 ±V S = ±.5V V S = 5V OUTPUT VOLTAGE (V p-p) 3 k k k M FREQUENCY (Hz) Figure 5. Gain vs. Frequency, VS = 5 V 5 ±V 5 ±5V ±.5V 5. FREQUENCY (khz) Figure 6. Large Signal Frequency Response COMMON-MODE INPUT (V) MAXIMUM OUTPUT VOLTAGE (V) Figure 8. Common-Mode Input vs. Maximum Output Voltage, G = 5, Small Supplies MAXIMUM OUTPUT VOLTAGE (V) Figure 9. Common-Mode Input vs. Maximum Output Voltage, G = 5, ±VS = ± V ±V S = ±5V.36 SLEW RATE (V/μs) COMMON-MODE INPUT (V) 3 4 ±V S = ±.5V V S = 5V SUPPLY VOLTAGE (±V S ) Figure 7. Slew Rate vs. Supply Voltage MAXIMUM OUTPUT VOLTAGE (V) Figure. Common-Mode Input vs. Maximum Output Voltage, G =, Small Supplies Rev. Page of

12 5 G = COMMON-MODE INPUT (V) 5 5 PSRR (db) G = G = G = MAXIMUM OUTPUT VOLTAGE (V) Figure. Common-Mode Input vs. Maximum Output Voltage, G =, ±VS = ± V k k k FREQUENCY (Hz) Figure 4. Negative PSRR vs. Frequency, ±VS = ± V G = G = 5V/DIV PSRR (db) 8 6 G = 4 G = 5.%/DIV k k k FREQUENCY (Hz) Figure. Positive PSRR vs. Frequency, ±VS = ± V Figure 5. Large Signal Response, G = 5 µs/div G = G = 5V/DIV PSRR (db) 8 6 G = 4 G = 5.%/DIV k k k FREQUENCY (Hz) Figure 3. Positive PSRR vs. Frequency, VS = 5 V µs/div Figure 6. Large Signal Pulse Response, G =, CL = pf Rev. Page of

13 5V/DIV.%/DIV µs/div mv/div µs/div Figure 7. Large Signal Pulse Response, G =, CL = pf Figure 9. Small Signal Pulse Response, G =, RL = 5 kω, CL = pf V S G = G = 5 G = OUTPUT VOLTAGE SWING (V) ERRED TO SUPPLY VOLTAGES SOURCING SINKING mv/div µs/div Figure 8. Small Signal Pulse Response, G = 5,, ; RL = kω V S.. OUTPUT CURRENT (ma) Figure 3. Output Voltage Swing vs. Output Current Rev. Page 3 of

14 THEORY OF OPERATION AMPLIFIER ARCHITECTURE The is an instrumentation amplifier based on a classic 3-op amp approach, modified to ensure operation even at common-mode voltages at the negative supply rail. The architecture allows lower voltage offsets, better CMRR, and higher gain accuracy than competing instrumentation amplifiers in its class. INVERTING POSITIVE SUPPLY 7 4 8kΩ kω 5kΩ GAIN 8kΩ kω 5kΩ 8 7 NON- INVERTING 3 4 NEGATIVE SUPPLY Figure 3. Simplified Schematic OUT 6 5 Figure 3 shows a simplified schematic of the. The has three stages. In the first stage, the input signal is applied to PNP transistors. These PNP transistors act as voltage buffers and allow input voltages below ground. The second stage consists of a pair of 8 kω resistors, the RG resistor, and a pair of amplifiers. This stage allows the amplification of the to be set with a single external resistor. The third stage is a differential amplifier composed of an op amp, two kω resistors, and two 5 kω resistors. This stage removes the common-mode signal and applies an additional gain of 5. The transfer function of the is VOUT = G(VIN VIN ) V where: G 5 8 kω RG GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the, which can be calculated by referring to Table 7 or by using the following gain equation: 8 kω G 5 Table 7. Gains Achieved Using % Resistors % Standard Table Value of RG (Ω) Desired Gain Calculated Gain 6.7 k k k k k The defaults to G = 5 when no gain resistor is used. Add the tolerance and gain drift of the RG resistor to the specifications of the to determine the total gain accuracy of the system. When the gain resistor is not used, gain depends only on internal resistor matching, so gain error and gain drift are minimal. INPUT VOLTAGE RANGE The 3-op amp architecture of the applies gain and then removes the common-mode voltage. Therefore, internal nodes in the experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. To determine whether the signal can be limited, refer to Figure 8 through Figure. Alternatively, use the parameters in the Specifications section to verify that the input and output are not limited and then use the following formula to make sure the internal nodes are not limited. To check if it is limited by the internal nodes, VDIFF Gain V S. V.6 VCM VS. V If more common-mode range is required, a solution is to apply less gain in the instrumentation amplifier and more in a later stage. Rev. Page 4 of

15 ERENCE TERMINAL The output voltage of the is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the pin to levelshift the output so that the can drive a single-supply ADC. The pin is protected with ESD diodes and should not exceed either VS or VS by more than.3 V. For best performance, keep the source impedance to the terminal below 5 Ω. As shown in Figure 3, the reference terminal,, is at one end of a 5 kω resistor. Additional impedance at the terminal adds to this resistor and results in poorer CMRR performance. V INCORRECT INPUT PROTECTION V CORRECT OP77 Figure 3. Driving the Reference Pin Internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the to safely withstand overvoltages of.3 V above or below the supplies. This is true for all gains, and for power-on and power-off. This last case is particularly important because the signal source and amplifier can be powered separately. If the overvoltage is expected to exceed this value, limit the current through these diodes to about ma using external current limiting resistors. This is shown in Figure 33. The size of this resistor is defined by the supply voltage and the required overvoltage protection. V OVER V OVER R LIM R LIM = ma MAX V S V OVER V S.7V R LIM = ma V S Figure 33. Input Protection OUT RF INTERFERENCE (RFI) RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, R-C network placed at the input of the instrumentation amplifier, as shown in Figure 34. The filter limits the input signal bandwidth according to the following relationship: FilterFreqDiff R(CD CC) FilterFreq CM where CD CC. R 4.kΩ R 4.kΩ RC C C nf C D 47nF C C nf C R 499Ω.µF IN IN 5V µf.µf µf 5V Figure 34. RFI Suppression V OUT Figure 34 shows an example in which the differential filter frequency is approximately 4 Hz, and the common-mode filter frequency is approximately 4 khz. The typical dc offset shift over frequency is less than.5 μv, and the RF signal rejection of the circuit is better than 7 db. The resistors were selected to be large enough to isolate the circuit input from the capacitors but not large enough to significantly increase the circuit noise. Choose values of R and CC to minimize RFI. Mismatch between the R CC at positive input and the R CC at negative input degrades the CMRR of the. Because of their higher accuracy and stability, COG/NPO type ceramic capacitors are recommended for the CC capacitors. The dielectric for the CD capacitor is not as critical Rev. Page 5 of

16 GROUND RETURNS FOR INPUT BIAS CURRENTS Input bias currents are those dc currents that must flow to bias the input transistors of an amplifier. These are usually transistor base currents. When amplifying floating input sources such as transformers or ac-coupled sources, there must be a direct dc path into each input so that the bias current can flow. Figure 35 shows how a bias current path can be provided for the cases of transformer coupling, capacitive ac-coupling, and a thermocouple application. In dc-coupled resistive bridge applications, providing this path is generally not necessary because the bias current simply flows from the bridge supply through the bridge and into the amplifier. However, if the impedances that the two inputs see are large and differ by a large amount (> kω), the offset current of the input stage causes dc errors proportional to the input offset voltage of the amplifier. INCORRECT V S V S TRANSFORMER V S CORRECT V S V S TRANSFORMER V S MΩ V S THERMOCOUPLE V S THERMOCOUPLE C V S C V S C f HIGH-PASS = πrc C R R V S V S CAPACITIVELY COUPLED CAPACITIVELY COUPLED Figure 35. Creating an IBIAS Path Rev. Page 6 of

17 APPLICATIONS INFORMATION V S V TO V V S 3V TO 4V.µF µf.µf µf V IN OUTPUT V OUT (INPUT) V IN OUTPUT V OUT (INPUT).µF µf BASIC CONNECTION V TO V V S A. DUAL SUPPLY B. SINGLE SUPPLY Figure 36 shows the basic connection circuit for the. The VS and VS terminals are connected to the power supply. The supply can be either bipolar (VS = ± V to ± V) or single supply ( VS = V, VS = 3 V to 4 V). Power supplies should be capacitively decoupled close to the power pins of the device. For best results, use surface-mount. μf ceramic chip capacitors and μf electrolytic tantalum capacitors. The input voltage, which can be either single-ended (tie either IN or IN to ground) or differential, is amplified by the programmed gain. The output signal appears as the voltage difference between the output pin and the externally applied voltage on the input. DIFFERENTIAL OUTPUT Figure 37 shows how to create a differential output in-amp. An OP77 op amp creates the inverted output. Because the op amp drives the reference pin, the can still ensure that the differential voltage is correct. Errors from the op amp or mismatched resistors are common to both outputs and are thus common mode. These common-mode errors should be rejected by the next device in the signal chain. IN IN kω kω V OP77 OUT OUT Figure 37. Differential Output Using Op Amp Figure 36. Basic Connections OUTPUT BUFFERING The is designed to drive loads of kω or greater. If the load is less than this value, buffer the output with a precision single-supply op amp such as the OP3. This op amp can swing from V to 4 V on its output while driving a load as small as 6 Ω. V IN 5V.µF 5V OP µF Figure 38. Output Buffering V OUT CABLES Receiving from a Cable In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 39 shows an active guard drive that is configured to improve ac common-mode rejection by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. Ω INPUT AD83 INPUT 8 3 V S V S Figure 39. Common-Mode Shield Driver V OUT ERENCE Rev. Page 7 of

18 Driving a Cable All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the output response of the. To reduce the peaking, use a resistor between the and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 75 Ω. The AD83 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. (DIFF OUT) (SINGLE OUT) Figure 4. Driving a Cable A SINGLE-SUPPLY DATA ACQUISITION SYSTEM Interfacing bipolar signals to single-supply analog-to-digital converters (ADCs) presents a challenge. The bipolar signal must be mapped into the input range of the ADC. Figure 4 shows how this translation can be achieved. 5V 5V.µF V.µF The bridge circuit is excited by a 5 V supply. The full-scale output voltage from the bridge (± mv), therefore, has a commonmode level of.5 V. The removes the common-mode component and amplifies the input signal by a factor of (RG =. kω). This results in an output signal of ± V. To prevent this signal from running into the ground rail, the voltage on the pin must be raised to at least V. In this example, the V reference voltage from the AD7776 ADC is used to bias the output voltage to V ± V, which corresponds to the input range of the ADC. AMPLIFYING SIGNALS WITH LOW COMMON- MODE VOLTAGE Because the common-mode input range of the extends.5 V below ground, it is possible to measure small differential signals that have low, or no, common-mode components. Figure 4 shows a thermocouple application in which one side of the J-type thermocouple is grounded. J-TYPE THERMOCOUPLE.kΩ 5V.µF V OUT Figure 4. Amplifying Bipolar Signals with Low Common-Mode Voltage Over a temperature range of C to C, the J-type thermocouple delivers a voltage ranging from 7.89 mv to.777 mv. A programmed gain on the of (RG = 845) and a voltage on the pin of V results in the output voltage ranging from. V to 3.77 V relative to ground. V ±mv.kω AD7776 A IN OUT IN Figure 4. A Single-Supply Data Acquisition System Rev. Page 8 of

19 OUTLINE DIMENSIONS PIN.65 BSC.38. COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.688).35 (.53).5 (.).3 (.) 8.5 (.98).7 (.67).5 (.96).5 (.99).7 (.5).4 (.57) 45 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR ERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 47-A Rev. Page 9 of

20 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AR 4 C to 85 C 8-Lead SOIC_N R-8 AR-RL 4 C to 85 C 8-Lead SOIC_N,3" Tape and Reel R-8 AR-R7 4 C to 85 C 8-Lead SOIC_N, 7" Tape and Reel R-8 ARM 4 C to 85 C 8-Lead MSOP RM-8 YU ARM-RL 4 C to 85 C 8-Lead MSOP, 3" Tape and Reel RM-8 YU ARM-R7 4 C to 85 C 8-Lead MSOP, 7" Tape and Reel RM-8 YU ARMZ 4 C to 85 C 8-Lead MSOP RM-8 YQ ARMZ-RL 4 C to 85 C 8-Lead MSOP, 3" Tape and Reel RM-8 YQ ARMZ-R7 4 C to 85 C 8-Lead MSOP, 7" Tape and Reel RM-8 YQ ARZ 4 C to 85 C 8-Lead SOIC_N R-8 ARZ-RL 4 C to 85 C 8-Lead SOIC_N, 3" Tape and Reel R-8 ARZ-R7 4 C to 85 C 8-Lead SOIC_N, 7" Tape and Reel R-8 BR 4 C to 85 C 8-Lead SOIC_N R-8 BR-RL 4 C to 85 C 8-Lead SOIC_N, 3" Tape and Reel R-8 BR-R7 4 C to 85 C 8-Lead SOIC_N, 7" Tape and Reel R-8 BRM 4 C to 85 C 8-Lead MSOP RM-8 YV BRM-RL 4 C to 85 C 8-Lead MSOP, 3" Tape and Reel RM-8 YV BRM-R7 4 C to 85 C 8-Lead MSOP, 7" Tape and Reel RM-8 YV BRMZ 4 C to 85 C 8-Lead MSOP RM-8 YR BRMZ-RL 4 C to 85 C 8-Lead MSOP, 3" Tape and Reel RM-8 YR BRMZ-R7 4 C to 85 C 8-Lead MSOP, 7" Tape and Reel RM-8 YR BRZ 4 C to 85 C 8-Lead SOIC_N R-8 BRZ-RL 4 C to 85 C 8-Lead SOIC_N, 3" Tape and Reel R-8 BRZ-R7 4 C to 85 C 8-Lead SOIC_N, 7" Tape and Reel R-8 Z = RoHS Compliant Part. 8 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D695--/8() Rev. Page of