Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp AD822

Transcription

1 Single-Supply, Rail-to-Rail Low Power FET-Input Op Amp AD822 FEATURES True single-supply operation Output swings rail-to-rail Input voltage range extends below ground Single-supply capability from 3 V to 36 V Dual-supply capability from ±.5 V to ±8 V High load drive Capacitive load drive of 350 pf, G = + Minimum output current of 5 ma Excellent ac performance for low power 800 μa maximum quiescent current per amplifier Unity-gain bandwidth:.8 MHz Slew rate of 3 V/μs Good dc performance 800 μv maximum input offset voltage 2 μv/ C typical offset voltage drift 25 pa maximum input bias current Low noise 3 nv/ khz No phase inversion APPLICATIONS Battery-powered precision instrumentation Photodiode preamps Active filters 2-bit to 4-bit data acquisition systems Medical instrumentation Low power references and regulators CONNECTION DIAGRAM OUT IN +IN V AD V+ OUT2 IN2 +IN2 Figure. 8-Lead PDIP (N Suffix); 8-Lead MSOP (RM Suffix); and 8-Lead SOIC_N (R Suffix) GENERAL DESCRIPTION The AD822 is a dual precision, low power FET input op amp that can operate from a single supply of 3 V to 36 V or dual supplies of ±.5 V to ±8 V. It has true single-supply capability with an input voltage range extending below the negative rail, allowing the AD822 to accommodate input signals below ground in the single-supply mode. Output voltage swing extends to within mv of each rail, providing the maximum output dynamic range. INPUT VOLTAGE NOISE (nv/ Hz) k k FREQUENCY (Hz) Figure 2. Input Voltage Noise vs. Frequency Offset voltage of 800 μv maximum, offset voltage drift of 2 μv/ C, input bias currents below 25 pa, and low input voltage noise provide dc precision with source impedances up to a gigaohm. The.8 MHz unity-gain bandwidth, 93 db THD at khz, and 3 V/μs slew rate are provided with a low supply current of 800 μa per amplifier Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... Connection Diagram... General Description... Revision History... 2 Specifications... 4 Absolute Maximum Ratings... 2 Thermal Resistance... 2 Maximum Power Dissipation... 2 ESD Caution... 2 Typical Performance Characteristics... 3 Applications Information Input Characteristics Output Characteristics Single-Supply Voltage-to-Frequency Converter... 2 Single-Supply Programmable Gain Instrumentation Amplifier V, Single-Supply Stereo Headphone Driver Low Dropout Bipolar Bridge Driver Outline Dimensions Ordering Guide REVISION HISTORY 8/08 Rev. G to Rev H. Changes to Features Section and General Description Section. Changed VO to VOUT Throughout... 4 Changes to Table... 4 Changes to Table Changes to Table Changes to Table Added Table 6; Renumbered Sequentially... 2 Changes to Figure 3 Caption... 4 Changes to Figure 29, Figure 3, and Figure Changes to Figure Changed Application Notes Section to Applications Information Section Changes to Figure 46 and Figure Changes to Figure Changes to Figure /06 Rev. F to Rev. G Changes to Features... Changes to Table 4... Changes to Table Changes to Table /05 Rev. E to Rev. F Updated Format... Universal Changes to Outline Dimensions Updated Ordering Guide /03 Data sheet changed from Rev. D to Rev. E Edits to Specifications... 2 Edits to Figure... 6 Updated Outline Dimensions... 7 /02 Data sheet changed from Rev. C to Rev. D Edits to Features... Edits to Ordering Guide... 6 Updated SOIC Package Outline /02 Data sheet changed from Rev. B to Rev. C All Figures Updated... Global Edits to Features... Updated All Package Outlines /0 Data sheet changed from Rev. A to Rev. B All Figures Updated... Global CERDIP References Removed..., 6, and 8 Additions to Product Description... 8-Lead SOIC and 8-Lead MSOP Diagrams Added... Deletion of AD822S Column... 2 Edits to Absolute Maximum Ratings and Ordering Guide... 6 Removed Metalization Photograph... 6 Rev. H Page 2 of 28

3 The AD822 drives up to 350 pf of direct capacitive load as a follower and provides a minimum output current of 5 ma. This allows the amplifier to handle a wide range of load conditions. Its combination of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single-supply user. The AD822 is available in two performance grades. The A grade and B grade are rated over the industrial temperature range of 40 C to +85 C. The AD822 is offered in three varieties of 8-lead packages: PDIP, MSOP, and SOIC_N. 5V 0V (GND) V OUT V V 20µs 0% V Figure 3. Gain-of-2 Amplifier; VS = 5 V, 0 V, VIN = 2.5 V Sine Centered at.25 V, RL = 0 Ω Rev. H Page 3 of 28

4 SPECIFICATIONS VS = 0 V, 5 TA = 25 C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted. Table. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset mv Maximum Offset Over Temperature mv Offset Drift 2 2 μv/ C Input Bias Current VCM = 0 V to 4 V pa At TMAX na Input Offset Current pa At TMAX na Open-Loop Gain VOUT = 0.2 V to 4 V RL = 0 kω V/mV TMIN to TMAX V/mV RL = kω V/mV TMIN to TMAX V/mV RL = kω V/mV TMIN to TMAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0. Hz to Hz 2 2 μv p-p f = Hz nv/ Hz f = 0 Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise f = 0. Hz to Hz 8 8 fa p-p f = khz fa/ Hz Harmonic Distortion RL = kω to 2.5 V f = khz VOUT = 0.25 V to 4.75 V db DYNAMIC PERFORMANCE Unity-Gain Frequency.8.8 MHz Full Power Response VOUT p-p = 4.5 V 2 2 khz Slew Rate 3 3 V/μs Settling Time To 0.% VOUT = 0.2 V to 4.5 V.4.4 μs To 0.0% VOUT = 0.2 V to 4.5 V.8.8 μs MATCHING CHARACTERISTICS Initial Offset mv Maximum Offset Over Temperature.6.3 mv Offset Drift 3 3 μv/ C Input Bias Current 20 pa f = khz RL = 5 kω db f = 0 khz RL = 5 kω db INPUT CHARACTERISTICS Input Voltage Range, TMIN to TMAX V Common-Mode Rejection Ratio (CMRR) VCM = 0 V to 2 V db TMIN to TMAX VCM = 0 V to 2 V db Rev. H Page 4 of 28

5 A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit Input Impedance Differential Ω pf Common Mode Ω pf OUTPUT CHARACTERISTICS Output Saturation Voltage 2 VOL VEE ISINK = 20 μa mv TMIN to TMAX mv VCC VOH ISOURCE = 20 μa 4 4 mv TMIN to TMAX mv VOL VEE ISINK = 2 ma mv TMIN to TMAX mv VCC VOH ISOURCE = 2 ma mv TMIN to TMAX mv VOL VEE ISINK = 5 ma mv TMIN to TMAX mv VCC VOH ISOURCE = 5 ma mv TMIN to TMAX 0 0 mv Operating Output Current 5 5 ma TMIN to TMAX 2 2 ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current, TMIN to TMAX ma Power Supply Rejection V+ = 5 V to 5 V db TMIN to TMAX db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ V) to V+. Common-mode effort voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. H Page 5 of 28

6 VS = ±5 TA = 25 C, VCM = 0 V, VOUT = 0 V, unless otherwise noted. Table 2. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset mv Maximum Offset Over Temperature mv Offset Drift 2 2 μv/ C Input Bias Current VCM = 5 V to +4 V pa At TMAX na Input Offset Current pa At TMAX na Open-Loop Gain VOUT = 4 V to +4 V RL = 0 kω V/mV TMIN to TMAX V/mV RL = kω V/mV TMIN to TMAX V/mV RL = kω V/mV TMIN to TMAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0. Hz to Hz 2 2 μv p-p f = Hz nv/ Hz f = 0 Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise f = 0. Hz to Hz 8 8 fa p-p f = khz fa/ Hz Harmonic Distortion RL = kω f = khz VOUT = ±4.5 V db DYNAMIC PERFORMANCE Unity-Gain Frequency.9.9 MHz Full Power Response VOUT p-p = 9 V 5 5 khz Slew Rate 3 3 V/μs Settling Time to 0.% VOUT = 0 V to ±4.5 V.4.4 μs to 0.0% VOUT = 0 V to ±4.5 V.8.8 μs MATCHING CHARACTERISTICS Initial Offset mv Maximum Offset Over Temperature 3 2 mv Offset Drift 3 3 μv/ C Input Bias Current 25 pa f = khz RL = 5 kω db f = 0 khz RL = 5 kω db INPUT CHARACTERISTICS Input Voltage Range, TMIN to TMAX V Common-Mode Rejection Ratio (CMRR) VCM = 5 V to +2 V db TMIN to TMAX VCM = 5 V to +2 V db Input Impedance Differential Ω pf Common Mode Ω pf Rev. H Page 6 of 28

7 A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage 2 VOL VEE ISINK = 20 μa mv TMIN to TMAX mv VCC VOH ISOURCE = 20 μa 4 4 mv TMIN to TMAX mv VOL VEE ISINK = 2 ma mv TMIN to TMAX mv VCC VOH ISOURCE = 2 ma mv TMIN to TMAX mv VOL VEE ISINK = 5 ma mv TMIN to TMAX mv VCC VOH ISOURCE = 5 ma mv TMIN to TMAX 0 0 mv Operating Output Current 5 5 ma TMIN to TMAX 2 2 ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current, TMIN to TMAX ma Power Supply Rejection VSY = ±5 V to ±5 V db TMIN to TMAX db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ V) to V+. Common-mode effort voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. H Page 7 of 28

8 VS = ±5 TA = 25 C, VCM = 0 V, VOUT = 0 V, unless otherwise noted. Table 3. A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit DC PERFORMANCE Initial Offset mv Maximum Offset Over Temperature mv Offset Drift 2 2 μv/ C Input Bias Current VCM = 0 V pa VCM = V pa At TMAX VCM = 0 V na Input Offset Current pa At TMAX na Open-Loop Gain VOUT = V to + V RL = 0 kω V/mV TMIN to TMAX V/mV RL = kω V/mV TMIN to TMAX 0 0 V/mV RL = kω V/mV TMIN to TMAX V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise f = 0. Hz to Hz 2 2 μv p-p f = Hz nv/ Hz f = 0 Hz 2 2 nv/ Hz f = khz 6 6 nv/ Hz f = khz 3 3 nv/ Hz Input Current Noise f = 0. Hz to Hz 8 8 fa p-p f = khz fa/ Hz Harmonic Distortion RL = kω f = khz VOUT = ± V db DYNAMIC PERFORMANCE Unity-Gain Frequency.9.9 MHz Full Power Response VOUT p-p = 20 V khz Slew Rate 3 3 V/μs Settling Time to 0.% VOUT = 0 V to ± V μs to 0.0% VOUT = 0 V to ± V μs MATCHING CHARACTERISTICS Initial Offset 3 2 mv Maximum Offset Over Temperature mv Offset Drift 3 3 μv/ C Input Bias Current 25 2 pa f = khz RL = 5 kω db f = 0 khz RL = 5 kω db INPUT CHARACTERISTICS Input Voltage Range, TMIN to TMAX V Common-Mode Rejection Ratio (CMRR) VCM = 5 V to +2 V db TMIN to TMAX VCM = 5 V to +2 V db Input Impedance Differential Ω pf Common Mode Ω pf Rev. H Page 8 of 28

9 A Grade B Grade Parameter Conditions Min Typ Max Min Typ Max Unit OUTPUT CHARACTERISTICS Output Saturation Voltage 2 VOL VEE ISINK = 20 μa mv TMIN to TMAX mv VCC VOH ISOURCE = 20 μa 4 4 mv TMIN to TMAX mv VOL VEE ISINK = 2 ma mv TMIN to TMAX mv VCC VOH ISOURCE = 2 ma mv TMIN to TMAX mv VOL VEE ISINK = 5 ma mv TMIN to TMAX mv VCC VOH ISOURCE = 5 ma mv TMIN to TMAX 0 0 mv Operating Output Current ma TMIN to TMAX 5 5 ma Capacitive Load Drive pf POWER SUPPLY Quiescent Current, TMIN to TMAX ma Power Supply Rejection VSY = ±5 V to ±5 V db TMIN to TMAX db This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (V+ V) to V+. Common-mode effort voltage is typically less than 5 mv with the common-mode voltage set at V below the positive supply. 2 VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Rev. H Page 9 of 28

10 VS = 0 V, 3 TA = 25 C, VCM = 0 V, VOUT = 0.2 V, unless otherwise noted. Table 4. Parameter Conditions Typ Unit DC PERFORMANCE Initial Offset 0.2 mv Maximum Offset Over Temperature 0.5 mv Offset Drift μv/ C Input Bias Current VCM = 0 V to 2 V 2 pa At TMAX 0.5 na Input Offset Current 2 pa At TMAX 0.5 na Open-Loop Gain VOUT = 0.2 V to 2 V TMIN to TMAX RL = 0 kω 00 V/mV TMIN to TMAX RL = kω 50 V/mV TMIN to TMAX RL = kω 30 V/mV NOISE/HARMONIC PERFORMANCE Input Voltage Noise 0. Hz to Hz 2 μv p-p f = Hz 25 nv/ Hz f = 0 Hz 2 nv/ Hz f = khz 6 nv/ Hz f = khz 3 nv/ Hz Input Current Noise f = 0. Hz to Hz 8 fa p-p f = khz 0.8 fa/ Hz Harmonic Distortion RL = kω to.5 V f = khz VOUT = ±.25 V 92 db DYNAMIC PERFORMANCE Unity-Gain Frequency.5 MHz Full Power Response VOUT p-p = 2.5 V 240 khz Slew Rate 3 V/μs Settling Time to 0.% VOUT = 0.2 V to 2.5 V μs to 0.0%.4 μs MATCHING CHARACTERISTICS Offset Drift 2 μv/ C f = khz RL = 5 kω 30 db f = 0 khz RL = 5 kω 93 db INPUT CHARACTERISTICS Common-Mode Rejection Ratio (CMRR), TMIN to TMAX VCM = 0 V to V 74 db Input Impedance Differential Ω pf Common Mode Ω pf Rev. H Page of 28

11 Parameter Conditions Typ Unit OUTPUT CHARACTERISTICS Output Saturation Voltage VOL VEE ISINK = 20 μa 5 mv VCC VOH ISOURCE = 20 μa mv VOL VEE ISINK = 2 ma 40 mv VCC VOH ISOURCE = 2 ma 80 mv VOL VEE ISINK = ma 200 mv VCC VOH ISOURCE = ma 500 mv Capacitive Load Drive 350 pf POWER SUPPLY Quiescent Current, TMIN to TMAX.24 ma Power Supply Rejection, TMIN to TMAX VSY = 3 V to 5 V 80 db VOL VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC). Specifications are TMIN to TMAX. Rev. H Page of 28

12 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Internal Power Dissipation 8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Input Voltage Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range (N) Storage Temperature Range (R, RM) Operating Temperature Range A Grade and B Grade Lead Temperature (Soldering, 60 sec) Rating ±8 V Observe derating curves Observe derating curves Observe derating curves ((V+) V) to (20 V + (V+)) Indefinite ±30 V 65 C to +25 C 65 C to +50 C 40 C to +85 C 260 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type θja Unit 8-lead PDIP (N) C/W 8-lead SOIC_N (R) 60 C/W 8-lead MSOP (RM) C/W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD822 is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 45 C. If these maximums are exceeded momentarily, proper circuit operation is restored as soon as the die temperature is reduced. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the derating curves shown in Figure 27. While the AD822 is internally short-circuit protected, this may not be sufficient to guarantee that the maximum junction temperature is not exceeded under all conditions. With power supplies ±2 V (or less) at an ambient temperature of 25 C or less, if the output node is shorted to a supply rail, then the amplifier is not destroyed, even if this condition persists for an extended period. ESD CAUTION Rev. H Page 2 of 28

13 TYPICAL PERFORMANCE CHARACTERISTICS V S = 0V, 5V NUMBER OF UNITS OFFSET VOLTAGE (mv) Figure 4. Typical Distribution of Offset Voltage (3 Units) V S = ±5V V S = ±5V % IN BIN OFFSET VOLTAGE DRIFT (µv/ C) Figure 5. Typical Distribution of Offset Voltage Drift (0 Units) Rev. H Page 3 of 28

14 M 40 OPEN-LOOP GAIN (V/V) M 0k V S = 0V, +5V V S = ±5V V S = 0V, +3V INPUT ERROR VOLTAGE (µv) POS RAIL R L = 20kΩ POS RAIL R L = 2kΩ POS RAIL NEG RAIL NEG RAIL k 0 k k 0k LOAD RESISTANCE (Ω) Figure. Open-Loop Gain vs. Load Resistance M R L = 0kΩ NEG RAIL OUTPUT VOLTAGE FROM SUPPLY RAILS (mv) Figure 3. Input Error Voltage with Output Voltage Within 300 mv of Either Supply Rail for Various Resistive Loads; VS = ±5 V k OPEN-LOOP GAIN (V/V) M 0k R L = 0kΩ R L = kω R L = 600Ω V S = ±5V V S = 0V, +5V V S = ±5V V S = 0V, +5V V S = ±5V INPUT VOLTAGE NOISE (nv/ Hz) 0 V S = 0V, +5V k TEMPERATURE ( C) Figure. Open-Loop Gain vs. Temperature k k FREQUENCY (Hz) Figure 4. Input Voltage Noise vs. Frequency R L = kω A CL = INPUT ERROR VOLTAGE (V) R L = kω R L = 600Ω R L = 0kΩ THD (db) V S = 0V, +3V; V OUT = 2.5V p-p V S = ±5V; V OUT = 20V p-p V S = ±5V; V OUT = 9V p-p V S = 0V, +5V; V OUT = 4.5V p-p OUTPUT VOLTAGE (V) Figure 2. Input Error Voltage vs. Output Voltage for Resistive Loads k k 0k FREQUENCY (Hz) Figure 5. Total Harmonic Distortion (THD) vs. Frequency Rev. H Page 4 of 28

15 OPEN-LOOP GAIN (db) GAIN PHASE PHASE MARGIN (Degrees) 0 R L = 2kΩ 20 C L = 0pF 20 0 k k 0k M M FREQUENCY (Hz) Figure 6. Open-Loop Gain and Phase Margin vs. Frequency k 0 OUTPUT IMPEDANCE (Ω) 0 k k 0k M M FREQUENCY (Hz) Rev. H Page 5 of 28

16 00 0 OUTPUT SATURATION VOLTAGE (mv) 0 I SOURCE = ma I SINK = ma I SOURCE = ma I SINK = ma I SOURCE = µa I SINK = µa POWER SUPPLY REJECTION (db) PSRR PSRR TEMPERATURE ( C) Figure 22. Output Saturation Voltage vs. Temperature k k 0k M M FREQUENCY (Hz) Figure 25. Power Supply Rejection vs. Frequency SHORT-CIRCUIT CURRENT LIMIT (ma) V S = ±5V V S = ±5V V S = 0V, +5V V S = 0V, +3V V S = 0V, +5V V S = 0V, +3V OUT OUTPUT VOLTAGE (V) V S = 0V, +5V V S = 0V, +3V V S = ±5V R L = 2kΩ TEMPERATURE ( C) Figure 23. Short-Circuit Current Limit vs. Temperature k 0k M M FREQUENCY (Hz) Figure 26. Large Signal Frequency Response QUIESCENT CURRENT (µa) T = +25 C T = +25 C T = 55 C TOTAL POWER DISSIPATION (W) LEAD SOIC 8-LEAD MSOP 8-LEAD PDIP TOTAL SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE ( C) Figure 24. Quiescent Current vs. Supply Voltage vs. Temperature Figure 27. Maximum Power Dissipation vs. Temperature for Packages Rev. H Page 6 of 28

17 V 5µs CROSSTALK (db) k 3k k 30k 0k 300k M FREQUENCY (Hz) Figure 28. Crosstalk vs. Frequency % Figure 32. Large Signal Response Unity-Gain Follower; VS = ±5 V, RL = kω V+ 0.0µF mv 500ns V IN 8 + /2 AD µF R L 0pF V OUT Figure 29. Unity-Gain Follower 0% 5V µs Figure 33. Small Signal Response Unity-Gain Follower; VS = ±5 V, RL = kω V 2µs 0 0% Figure V p-p, 25 khz Sine Wave Input; Unity-Gain Follower; VS = ±5 V, RL = 600 Ω 20V p-p V IN V+ 8 /2 AD822 0.µF µf CROSSTALK = 20 log V OUT V IN 5kΩ V OUT 7 5kΩ 20kΩ Figure 3. Crosstalk Test Circuit V /2 AD kΩ 0.µF µf GND 0% Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step V+ 0.0µF 8 V IN + /2 AD822 R L 0pF V OUT 4 Figure 35. Unity-Gain Follower Rev. H Page 7 of 28

18 V IN kω V+ 8 20kΩ 0.0µF V OUT 0 mv 2µs /2 AD822 + R L 0pF Figure 36. Gain-of-Two Inverter GND 0% 0 V 2µs Figure 39. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mv Step, Centered 20 mv Below Ground, RL = kω V 2µs 0 GND 0% Figure 37. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step GND 0% 0 mv 2µs Figure 40. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step, Centered.25 V Below Ground, RL = kω mV µs 0 GND 0% Figure 38. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mv Step, Centered 40 mv above Ground, RL = kω GND 0% Figure 4. VS = 3 V, 0 V; Gain-of-2 Inverter, VIN =.25 V, 25 khz, Sine Wave Centered at 0.75 V, RL = 600 Ω Rev. H Page 8 of 28

19 V µs GND 0% V (a) V V µs +Vs GND 0% V (b) 5V R P V IN V OUT Figure 42. (a) Response with RP = 0; VIN from 0 V to +VS (b) VIN = 0 V to +VS mv VOUT = 0 V to +VS RP = 49.9 kω Rev. H Page 9 of 28

20 APPLICATIONS INFORMATION INPUT CHARACTERISTICS In the AD822, N-channel JFETs are used to provide a low offset, low noise, high impedance input stage. Minimum input commonmode voltage extends from 0.2 V below VS to V less than +VS. Driving the input voltage closer to the positive rail causes a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in Figure 34 and Figure 37) and increased common-mode voltage error as illustrated in Figure 20. The AD822 does not exhibit phase reversal for input voltages up to and including +VS. Figure 42 shows the response of an AD822 voltage follower to a 0 V to 5 V (+VS) square wave input. The input and output are superimposed. The output tracks the input up to +VS without phase reversal. The reduced bandwidth above a 4 V input causes the rounding of the output waveform. For input voltages greater than +VS, a resistor in series with the AD822 noninverting input prevents phase reversal, at the expense of greater input voltage noise. This is illustrated in Figure 42. Because the input stage uses N-channel JFETs, input current during normal operation is negative; the current flows out from the input terminals. If the input voltage is driven more positive than +VS 0.4 V, then the input current reverses direction as internal device junctions become forward biased. This is illustrated in Figure 7. A current limiting resistor should be used in series with the input of the AD822 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mv, or if an input voltage is applied to the AD822 when +VS or VS = 0 V. The amplifier is damaged if left in that condition for more than seconds. A kω resistor allows the amplifier to withstand up to V of continuous overvoltage and increases the input voltage noise by a negligible amount. Input voltages less than VS are a completely different story. The amplifier can safely withstand input voltages 20 V below the negative supply voltage if the total voltage from the positive supply to the input terminal is less than 36 V. In addition, the input stage typically maintains picoampere (pa) level input currents across that input voltage range. The AD822 is designed for 3 nv/ Hz wideband input voltage noise and maintains low noise performance to low frequencies (refer to Figure 4). This noise performance, along with the AD822 low input current and current noise, means that the AD822 contributes negligible noise for applications with source resistances greater than kω and signal bandwidths greater than khz. This is illustrated in Figure 43. INPUT VOLTAGE NOISE (µv) 0k k k 0 WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE CONSIDERED NEGLIGIBLE FOR APPLICATION. khz RESISTOR JOHNSON NOISE Hz AMPLIFIER-GENERATED NOISE 0. k 0k M M 0M G G SOURCE IMPEDANCE (Ω) Figure 43. Total Noise vs. Source Impedance Rev. H Page 20 of 28

21 20mV 2µs Figure 46 shows a method for extending capacitance load drive capability for a unity-gain follower. With these component values, the circuit drives 5000 pf with a % overshoot. V+ 0.0µF 0% V IN 8 + /2 AD µF V 0Ω C L V OUT Figure 44. Small Signal Response of AD822 as Unity-Gain Follower Driving 350 pf Figure 45 is a plot of noise gain vs. capacitive load that results in a 20 phase margin for the AD822. Noise gain is the inverse of the feedback attenuation factor provided by the feedback network in use. NOISE GAIN + R F R k 3k k 30k CAPACITIVE LOAD FOR 20 PHASE MARGIN (pf) R Figure 45. Noise Gain vs. Capacitive Load Tolerance R F C L kΩ 20pF Figure 46. Extending Unity-Gain Follower Capacitive Load Capability Beyond 350 pf SINGLE-SUPPLY VOLTAGE-TO-FREQUENCY CONVERTER The circuit shown in Figure 47 uses the AD822 to drive a low power timer that produces a stable pulse of width t. The positive going output pulse is integrated by R and C and used as one input to the AD822 that is connected as a differential integrator. The other input (nonloading) is the unknown voltage, VIN. The AD822 output drives the timer trigger input, closing the overall feedback loop. C5 0.µF 3 V IN V 2 4 U4 REF02 V 6 REF = 5V 5 R2 499kΩ % R 499kΩ % C2 0.0µF 2% 0V TO 2.5V FULL SCALE R SCALE kω CMOS 74HCO4 U3B µF, 2% U C + /2 AD822B U3A 2 R3 6kΩ C3 0.µF U2 CMOS R V+ THR OUT 3 TR 5 CV DIS GND NOTES. f OUT = V IN /(V REF t ), t =. R3 C6. = 25kHz f S AS SHOWN. 2. R3 = % METAL FILM <50ppm/ C TC. 3. R SCALE = % 20T FILM <0ppm/ C TC. 4. t = 33µF FOR f OUT = V IN = 2.0V. Figure 47. Single-Supply Voltage-to-Frequency Converter OUT2 OUT C4 0.0µF Typical AD822 bias currents of 2 pa allow MΩ range source impedances with negligible dc errors. Linearity errors on the order of 0.0% full scale can be achieved with this circuit. This performance is obtained with a 5 V single supply that delivers less than ma to the entire circuit Rev. H Page 2 of 28

22 SINGLE-SUPPLY PROGRAMMABLE GAIN INSTRUMENTATION AMPLIFIER The AD822 can be configured as a single-supply instrumentation amplifier that is able to operate from single supplies down to 3 V or dual supplies up to ±5 V. Using only one AD822 rather than three separate op amps, this circuit is cost and power efficient. The 2 pa bias currents of the AD822 FET inputs minimize offset errors caused by high unbalanced source impedances. An array of precision thin film resistors sets the in-amp gain to be either or 0. These resistors are laser trimmed to ratio match to 0.0% and have a maximum differential TC of 5 ppm/ C. Table 7. In-Amp Performance Parameters VS = 3 V, 0 V VS = ±5 V CMRR 74 db 80 db Common-Mode Voltage Range 0.2 V to +2 V 5.2 V to +4 V 3 db BW G = 80 khz 80 khz G = 0 8 khz 8 khz tsettling 2 V Step 2 μs 5 V Step 5 μs f = khz G = 270 nv/ Hz 270 nv/ Hz G = μv/ Hz 2.2 μv/ Hz ISUPPLY (Total). ma.5 ma % V Figure 48. Pulse Response of In-Amp to a 500 mv p-p Input Signal; VS = 5 V, 0 V; Gain = 0 5µs V REF V IN V IN2 R P kω R kω G = G = 0 G = 0 G = R P kω 2 R2 9kΩ V+ /2 AD R3 kω 0.µF R4 kω R5 9kΩ 6 /2 AD R6 kω ( ) R5 + R6 ( + R4 ) R6 (G = ) V OUT = (V IN V IN2 ) + +V REF R4 + R5 (G = 0) V OUT = (V IN V IN2 ) +V REF 7 OHMTEK PART # 43 + V OUT Figure 49. A Single-Supply Programmable Instrumentation Amplifier 3 V, SINGLE-SUPPLY STEREO HEADPHONE DRIVER The AD822 exhibits good current drive and total harmonic distortion plus noise (THD + N) performance, even at 3 V single supplies. At khz, THD + N equals 62 db (0.079%) for a 300 mv p-p output signal. This is comparable to other singlesupply op amps that consume more power and cannot run on 3 V power supplies. CHANNEL CHANNEL 2 µf MYLAR 95.3kΩ µf MYLAR 3V 95.3kΩ /2 47.5kΩ 2 AD kΩ kω kω 4.99kΩ 6 /2 47.5kΩ AD µF HEADPHONES 32Ω IMPEDANCE 7 0.µF 500µF 500µF Figure V Single-Supply Stereo Headphone Driver In Figure 50, the input signal of each channel is coupled via a μf Mylar capacitor. Resistor dividers set the dc voltage at the noninverting inputs so that the output voltage is midway between the power supplies (.5 V). The gain is.5. Each half of the AD822 can then be used to drive a headphone channel. A 5 Hz high-pass filter is realized by the 500 μf capacitors and the headphones that can be modeled as 32 Ω load resistors to ground. This ensures that all signals in the audio frequency range (20 Hz to 20 khz) are delivered to the headphones. L R Rev. H Page 22 of 28

23 LOW DROPOUT BIPOLAR BRIDGE DRIVER The AD822 can be used for driving a 350 Ω Wheatstone bridge. Figure 5 shows one-half of the AD822 being used to buffer the AD589, a.235 V low power reference. The output of 4.5 V can be used to drive an analog-to-digital converter (ADC) front end. The other half of the AD822 is configured as a unity-gain inverter and generates the other bridge input of 4.5 V. Resistor R and Resistor R2 provide a constant current for bridge excitation. The AD620 low power instrumentation amplifier is used to condition the differential output voltage of the bridge. The gain of the AD620 is programmed using an external resistor RG and determined by 49.9 kω G = + R G 49.9kΩ V /2 AD589 AD kΩ % kω % 350Ω kω % 6 V+ kω % /2 AD822 R 20Ω 350Ω 350Ω 350Ω R G TO A/D CONVERTER REFERENCE INPUT V S AD620 V S V REF 7 4.5V V+ +5V R2 0.μF μf 4 20Ω GND + + V 0.μF μf V 5V Figure 5. Low Dropout Bipolar Bridge Driver Rev. H Page 23 of 28

24 OUTLINE DIMENSIONS (.6) (9.27) (9.02) 0.2 (5.33) MAX 0.50 (3.8) 0.30 (3.30) 0.5 (2.92) (0.56) 0.08 (0.46) 0.04 (0.36) (2.54) BSC (7.) (6.35) (6.) 0.05 (0.38) MIN SEATING PLANE (0.3) MIN (.52) MAX 0.05 (0.38) GAUGE PLANE (8.26) 0.3 (7.87) (7.62) (.92) MAX 0.95 (4.95) 0.30 (3.30) 0.5 (2.92) 0.04 (0.36) 0.0 (0.25) (0.20) (.78) (.52) (.4) COMPLIANT TO JEDEC STANDARDS MS-00 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) A 5.00 (0.968) 4.80 (0.8) 4.00 (0.574) 3.80 (0.497) (0.244) 5.80 (0.2284) (0.0098) 0. (0.0040) COPLANARITY 0. SEATING PLANE.27 (0.0500) BSC.75 (0.0688).35 (0.0532) 0.5 (0.020) 0.3 (0.022) 0.25 (0.0098) 0.7 (0.0067) 0.50 (0.096) 0.25 (0.0099).27 (0.0500) 0.40 (0.057) COMPLIANT TO JEDEC STANDARDS MS-02-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) A PIN BSC MAX SEATING PLANE 8 0 COMPLIANT TO JEDEC STANDARDS MO-87-AA Rev. H Page 24 of 28

25 ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD822AN 40 C to +85 C 8-Lead PDIP N-8 AD822ANZ 40 C to +85 C 8-Lead PDIP N-8 AD822AR 40 C to +85 C 8-Lead SOIC_N R-8 AD822AR-REEL 40 C to +85 C 8-Lead SOIC_N R-8 AD822AR-REEL7 40 C to +85 C 8-Lead SOIC_N R-8 AD822ARZ 40 C to +85 C 8-Lead SOIC_N R-8 AD822ARZ-REEL 40 C to +85 C 8-Lead SOIC_N R-8 AD822ARZ-REEL7 40 C to +85 C 8-Lead SOIC_N R-8 AD822ARM-R2 40 C to +85 C 8-Lead MSOP RM-8 B4A AD822ARM-REEL 40 C to +85 C 8-Lead MSOP RM-8 B4A AD822ARMZ-R2 40 C to +85 C 8-Lead MSOP RM-8 #B4A AD822ARMZ-REEL 40 C to +85 C 8-Lead MSOP RM-8 #B4A AD822BR 40 C to +85 C 8-Lead SOIC_N R-8 AD822BR-REEL 40 C to +85 C 8-Lead SOIC_N R-8 AD822BR-REEL7 40 C to +85 C 8-Lead SOIC_N R-8 AD822BRZ 40 C to +85 C 8-Lead SOIC_N R-8 AD822BRZ-REEL 40 C to +85 C 8-Lead SOIC_N R-8 AD822BRZ-REEL7 40 C to +85 C 8-Lead SOIC_N R-8 Z = RoHS Compliant Part, # denotes RoHS-compliant product may be top or bottom marked. SPICE model is available at Rev. H Page 25 of 28

26 NOTES Rev. H Page 26 of 28

27 NOTES Rev. H Page 27 of 28

28 NOTES Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D /08(H) Rev. H Page 28 of 28