TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... 2 Specifications... 3 Electrical Charac

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1 6 V Rail-to-Rail Operational Amplifiers AD86/AD866/AD867 FEATURES Single-supply operation: 4. V to 6 V Input capability beyond the rails Rail-to-rail output swing Continuous output current: 3 ma Peak output current: 2 ma Offset voltage: mv Slew rate: 6 V/μs Unity gain stable with large capacitive loads Supply current: 7 μa per amplifier PIN CONFIGURATIONS OUT V+ 2 AD86 V +IN 3 TOP VIEW 4 IN (Not to Scale) Figure. -Lead SC7 Pin Configuration OUT A AD866 8 V+ 99- APPLICATIONS LCD reference drivers Portable electronics Communications equipment GENERAL DESCRIPTION The AD86, AD866, and AD867 are low cost, single-supply, OUT A 4 OUT D rail-to-rail input and output operational amplifiers optimized IN A 2 3 IN D for LCD monitor applications. They are built on an advanced high voltage CBCMOS process. The AD86 contains a single +IN A 3 2 +IN D amplifier, the AD866 has two amplifiers, and the AD867 has AD867 four amplifiers. These LCD op amps have high slew rates, 3 ma continuous output drive, 2 ma peak output drive, and a high capacitive load drive capability. They have a wide supply range and offset voltages below mv. The AD86, AD866, and AD867 are ideal for LCD grayscale reference buffer and VCOM applications. The AD86, AD866, and AD867 are specified over the 4 C to +8 C temperature range. The AD86 single is available in a -lead SC7 package. The AD866 dual is available in an 8-lead MSOP package. The AD867 quad is available in a 4-lead TSSOP package and a 6-lead LFCSP package. IN A +IN A OUT B IN B V 4 TOP VIEW +IN B (Not to Scale) Figure 2. 8-Lead MSOP Pin Configuration V+ +IN B IN B OUT B 4 TOP VIEW V (Not to Scale) +IN C IN C OUT C Figure 3. 4-Lead TSSOP Pin Configuration IN A +IN A V+ +IN B NC OUT A OUT D NC AD867 TOP VIEW (Not to Scale) IN D +IN D V +IN C IN B OUT B OUT C IN C NC = NO CONNECT Figure 4. 6-Lead LFCSP Pin Configuration 99-4 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Features... Applications... General Description... Pin Configurations... Revision History... 2 Specifications... 3 Electrical Characteristics... 3 Absolute Maximum Ratings... 4 ESD Caution... 4 Input Overvoltage Protection...9 Output Phase Reversal... Power Dissipation... Thermal Pad AD Total Harmonic Distortion + Noise (THD+N)... Short-Circuit Output Conditions... LCD Panel Applications... Outline Dimensions... 2 Ordering Guide... 3 Typical Performance Characteristics... Theory of Operation... 9 REVISION HISTORY 2/6 Rev C to Rev. D Updated Format...Universal Changes to Figure 6 and Figure 8... Added the Thermal Pad AD867 Section... Changes to Ordering Guide /4 Rev B to Rev. C Changes to Specifications... 2 Changes to TPC Changes to TPC... Changes to TPC Changes to TPC /3 Rev. A to Rev. B Updated Ordering Guide... 3 Updated Outline Dimensions... / Rev. to Rev. A Edit to 6-Lead CSP and -Lead SC7 Pin Configuration... Edit to Ordering Guide / Revision : Initial Version Rev. D Page 2 of 6

3 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 4. V VS 6 V, VCM = VS/2, TA = 2 C, unless otherwise noted. AD86/AD866/AD867 Table. Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 2 mv Offset Voltage Drift ΔVOS/ΔT 4 C TA +8 C μv/ C Input Bias Current IB 8 6 na 4 C TA +8 C 8 na Input Offset Current IOS 8 na 4 C TA +8 C 3 na Input Voltage Range Common-mode input. VS +. V Common-Mode Rejection Ratio CMRR VCM = to VS, 4 C TA +8 C 4 9 db Large Signal Voltage Gain AVO RL = kω, VO =. V to (VS. V) 3 V/mV Input Impedance ZIN 4 kω Input Capacitance CIN pf OUTPUT CHARACTERISTICS Output Voltage High VOH IL = μa VS. V VS = 6 V, IL = ma.8.9 V 4 C TA +8 C.7 V VS = 4. V, IL = ma V 4 C TA +8 C 4. V Output Voltage Low VOL IL = μa mv VS = 6 V, IL = ma 42 mv 4 C TA +8 C 2 mv VS = 4. V, IL = ma 9 3 mv 4 C TA +8 C 4 mv Continuous Output Current IOUT 3 ma Peak Output Current IPK VS = 6 V 2 ma POWER SUPPLY Supply Voltage VS 4. 6 V Power Supply Rejection Ratio PSRR VS = 4 V to 7 V, 4 C TA +8 C 7 9 db Supply Current/Amplifier ISY VO = VS/2, no load 7 8 μa 4 C TA +8 C ma DYNAMIC PERFORMANCE Slew Rate SR RL = kω, CL = 2 pf 4 6 V/μs Gain Bandwidth Product GBP RL = kω, CL = pf MHz Phase Margin Øo RL = kω, CL = pf 6 Degrees Channel Separation 7 db NOISE PERFORMANCE Voltage Noise Density en f = khz 26 nv/ Hz en f = khz 2 nv/ Hz Current Noise Density in f = khz.8 pa/ Hz Rev. D Page 3 of 6

4 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Ratings Supply Voltage (VS) 8 V Input Voltage. V to VS +. V Differential Input Voltage VS Storage Temperature Range 6 C to + C Operating Temperature Range 4 C to +8 C Junction Temperature Range 6 C to + C Lead Temperature (Soldering, 6 sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Package Type θja θjc Unit -Lead SC7 (KS-) C/W 8-Lead MSOP (RM-8) 2 4 C/W 4-Lead TSSOP (RU-4) 8 3 C/W 6-Lead LFCSP (CP-6-4) C/W θja is specified for worst-case conditions, that is, θja is specified for a device soldered onto a circuit board for surface-mount packages. 2 DAP is soldered down to PCB. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D Page 4 of 6

5 TYPICAL PERFORMANCE CHARACTERISTICS INPUT OFFSET VOLTAGE (mv) V CM = V S / V S = 4.V VOLTAGE NOISE DENSITY (nv/ Hz) 4.V V S 6V TEMPERATURE ( C) Figure. Input Offset Voltage vs. Temperature 99- k k Figure 8. Voltage Noise Density vs. Frequency 99-8 CURRENT NOISE DENSITY (pa/ Hz) 4.V V S 6V SUPPLY CURRENT/AMPLIFIER (ma)..8 V O = V S /2 A V = k k Figure 6. Current Noise Density vs. Frequency SUPPLY VOLTAGE (V) Figure 9. Supply Current/Amplifier vs. Supply Voltage TIME (mv/div) R L = kω C L = pf A V = + SUPPLY CURRENT/AMPLIFIER (ma) V CM = V S /2 V S = 4.V FREQUENCY (µs/div) Figure 7. Small Signal Transient Response TEMPERATURE ( C) Figure. Supply Current/Amplifier vs. Temperature 99- Rev. D Page of 6

6 OVERSHOOT (%) V IN = mv p-p R L = kω A V = + OS +OS GAIN (db) R L = kω C L = 4pF PHASE SHIFT (Degrees) 2 27 k LOAD CAPACITANCE (pf) Figure. Small Signal Overshoot vs. Load Capacitance 99- k k k M M M Figure 4. Open-Loop Gain and Phase Shift vs. Frequency k OUTPUT SWING (V p-p) 4 2 V S = 4.V 8 6 V S = 6V A 4 V = + R L = kω DISTORTION < % 2. k k k M M... LOAD CURRENT (ma) Figure 2. Closed-Loop Output Swing vs. Frequency Figure. Output Voltage to Supply Rail vs. Load Current 99-2 OUTPUT VOLTAGE (mv) 99- CLOSED-LOOP GAIN (db) A VCL = A VCL = A VCL = + 4.V V S 6V R L = kω C L = 4pF OUTPUT VOLTAGE (mv) I SINK = ma V S = 4.V 3 k k k M M Figure 3. Closed-Loop Gain vs. Frequency TEMPERATURE ( C) Figure 6. Output Voltage Swing to Rail vs. Temperature 99-6 Rev. D Page 6 of 6

7 OUTPUT VOLTAGE (mv) I SOURCE = ma V S = 4.V POWER SUPPLY REJECTION RATIO (db) PSRR +PSRR TEMPERATURE ( C) Figure 7. Output Voltage Swing to Rail vs. Temperature k k k M M Figure 2. Power Supply Rejection Ratio vs. Frequency A V = + R L = kω A V = + IMPEDANCE (Ω) V S = 4.V k k k M M Figure 8. Closed-Loop Output Impedance vs. Frequency 99-8 VOLTAGE (3V/DIV) TIME (4µs/DIV) Figure 2. No Phase Reversal k.6k.4k CMRR (db) QUANTITY (Amplifiers).2k.k k k k M M Figure 9. Common-Mode Rejection Ratio (CMRR) vs. Frequency INPUT OFFSETVOLTAGE (mv) Figure 22. Input Offset Voltage Distribution Rev. D Page 7 of 6

8 7 INPUT OFFSET CURRENT (na) V S = 4.V TEMPERATURE ( C) Figure 23. Input Offset Current vs. Temperature BANDWIDTH (MHz) A V = + R L = x COMMON-MODE VOLTAGE (V) Figure 26. Frequency vs. Common-Mode Voltage (VS = 6 V) INPUT BIAS CURRENT (na) V CM = V S /2 BANDWIDTH (MHz) 6 4 V S = V A V = + R L = kω V 3 S = 4.V TEMPERATURE ( C) Figure 24. Input Bias Current vs. Temperature COMMON-MODE VOLTAGE (V) Figure 27. Frequency vs. Common-Mode Voltage (VS = V) CROSSTALK (db) V 6V k k 6k Figure 2. Channel A vs. Channel B Crosstalk 99-2 Rev. D Page 8 of 6

9 THEORY OF OPERATION The AD86x family is designed to drive large capacitive loads in LCD applications. It has high output current drive, rail-to-rail input/output operation, and is powered from a single 6 V supply. It is also intended for other applications where low distortion and high output current drive are needed. AD86/AD866/AD867 Figure 28 illustrates a simplified equivalent circuit for the AD86x. The rail-to-rail bipolar input stage is composed of two PNP differential pairs, Q4 to Q and Q to Q, operating in series with diode protection networks, D to D2. Diode network D to D2 serves as protection against large transients for Q4 to Q to accommodate rail-to-rail input swing. D to D6 protect Q to Q against Zenering. In normal operation, Q to Q are off and their input stage is buffered from the operational amplifier inputs by Q6 to D3 and Q8 to D4. Operation of the 8 input stage is best understood as a function of applied 6 common-mode voltage: when the inputs of the AD86x are 4 biased midway between the supplies, the differential signal path 2 gain is controlled by resistive loads (via R9, R) Q4 to Q. As the input common-mode level is reduced toward the negative supply 2 (VNEG or GND), the input transistor current sources, I and I2, are forced into saturation, thereby forcing the Q6 to D3 4 and Q8 to D4 networks into cutoff. However, Q4 to Q remain 6 active, providing input stage gain. Inversely, when commonmode input voltage is increased toward the positive supply, Q4 8 to Q are driven into cutoff, Q3 is driven into saturation, and INPUT COMMON-MODE VOLTAGE (V) Q4 becomes active, providing bias to the Q to Q differential Figure 29. AD86x Input Bias Current vs. Common-Mode Voltage pair. The point at which Q to Q differential pair becomes active is approximately equal to (VPOS V). V+ Q6 D3 I D R3 Q4 R9 R Q3 C R Q V POS C2 Q D D6 R6 Q4 D2 R4 Q R D4 I2 Q8 BIAS LINE V FOLDED CASCADE The benefit of this type of input stage is low bias current. The input bias current is the sum of base currents of Q4 to Q and Q6 to Q8 over the range from (VNEG + V) to (VPOS V). Outside of this range, input bias current is dominated by the sum of base currents of Q to Q for input signals close to VNEG and of Q6 to Q8 (Q to Q) for signals close to VPOS. From this type of design, the input bias current of AD86x not only exhibits different amplitude but also exhibits different polarities. Figure 29 provides the characteristics of the input bias current vs. the common-mode voltage. It is important to keep in mind that the source impedances driving the AD86x inputs are balanced for optimum dc and ac performance. INPUT BIAS CURRENT (na) To achieve rail-to-rail output performance, the AD86x design uses a complementary common-source (or gmrl) output. This configuration allows output voltages to approach the power supply rails, particularly if the output transistors are allowed to enter the triode region on extremes of signal swing, which are limited by VGS, the transistor sizes, and output load current. In addition, this type of output stage exhibits voltage gain in an open-loop gain configuration. The amount of gain depends on the total load resistance at the output of the AD86x. INPUT OVERVOLTAGE PROTECTION As with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. When the input voltage exceeds either supply by more than.6 V, internal pn junctions allow current to flow from the input to the supplies V NEG Figure 28. AD86x Equivalent Input Circuit Rev. D Page 9 of 6

10 This input current is not inherently damaging to the device as long as it is limited to ma or less. If a condition exists using the AD86x where the input exceeds the supply more than.6 V, an external series resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided by ma. This resistance should be placed in series with either input exposed to an overvoltage. OUTPUT PHASE REVERSAL The AD86x family is immune to phase reversal. Although the device s output does not change phase, large currents due to input overvoltage could damage the device. In applications where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used as described in the Input Overvoltage Protection section. POWER DISSIPATION 4-LEAD SOIC The maximum allowable internal junction temperature of. C limits the AD86x family s maximum power dissipation of AD86x devices. As the ambient temperature increases, the maximum power dissipated by AD86x devices must decrease linearly to maintain the maximum junction temperature. If this maximum junction temperature is exceeded momentarily, the device still operates properly once the junction temperature is.7. 4-LEAD TSSOP 8-LEAD MSOP -LEAD SOT-23.2 reduced below C. If the maximum junction temperature is exceeded for an extended period, overheating could lead to permanent damage of the device AMBIENT TEMPERATURE ( C) The maximum safe junction temperature, TJMAX, is C. Using Figure 3. Maximum Power Dissipation vs. Temperature the following formula, the maximum power that an AD86x for -Lead SC7, 8-Lead MSOP, and 4-Lead TSSOP/SOIC Packages device can safely dissipate as a function of temperature can be obtained: THERMAL PAD AD867 where: PDISS = TJMAX TA/θJA PDISS is the AD86x power dissipation. TJMAX is the AD86x maximum allowable junction temperature ( C). TA is the ambient temperature of the circuit. θja is the AD86x package thermal resistance, junction-to-ambient. The power dissipated by the device can be calculated as where: PDISS = (VS VOUT) ILOAD VS is the supply voltage. VOUT is the output voltage. ILOAD is the output load current. Figure 3 shows the maximum power dissipation vs. temperature. To achieve proper operation, use the previous equation to calculate PDISS for a specific package at any given temperature or use Figure 3. MAXIMUM POWER DISSIPATION (W).2 The AD867 LFCSP comes with a thermal pad that is attached to the substrate. This substrate is connected to VDD. To be electrically safe, the thermal pad should be soldered to an area on the board that is electrically isolated or connected to VDD. Attaching the thermal pad to ground adversely affects the performance of the part. Soldering down this thermal pad dramatically improves the heat dissipation of the package. It is necessary to attach vias that connect the soldered thermal pad to another layer on the board. This provides an avenue to dissipate the heat away from the part. Without vias, the heat is isolated directly under the part Rev. D Page of 6

11 TOTAL HARMONIC DISTORTION + NOISE (THD+N) The AD86x family features low total harmonic distortion. Figure 3 shows THD+N vs. frequency. The THD+N for the AD86x over the entire supply range is below.8%. When the device is powered from a 6 V supply, the THD+N stays below.3%. Figure 3 shows the AD866 in a unity noninverting configuration. LCD PANEL APPLICATIONS The AD86x amplifier is designed for LCD panel applications or applications where large capacitive load drive is required. It can instantaneously source/sink greater than 2 ma of current. At unity gain, it can drive μf without compensation. This makes the AD86x ideal for LCD VCOM driver applications. To evaluate the performance of the AD86x family, a test circuit was developed to simulate the VCOM driver application for an LCD panel. THD+N (%). V S = ±2.V V S = ±8V Figure 32 shows the test circuit. Series capacitors and resistors connected to the output of the op amp represent the load of the LCD panel. The 3 Ω and 3 kω feedback resistors are used to improve settling time. This test circuit simulates the worst-case scenario for a VCOM. It drives a represented load that is connected to a signal switched symmetrically around VCOM. Figure 33 shows a scope photo of the instantaneous output peak current capability of the AD86x family.. 2 k k 3k 3Ω INPUT VTO 8V Figure 3. THD+N vs. Frequency SQUARE WAVEWITH 8V 3kΩ.6µs PULSE WIDTH Ω Ω Ω Ω 4V nf nf nf nf MEASURE CURRENT Ω TO 2Ω Figure 32. VCOM Test Circuit with Supply Voltage at 6 V SHORT-CIRCUIT OUTPUT CONDITIONS The AD86x family does not have internal short-circuit protection circuitry. As a precautionary measure, it is recommended not to short the output directly to the positive power supply or to ground. It is not recommended to operate the AD86x with more than 3 ma of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using VS RX 3 ma CH 2 = ma/div For a V single-supply operation, RX should have a minimum value of 43 Ω. CH = V/DIV % TIME (2µs/DIV) Figure 33. Scope Photo of the VCOM Instantaneous Peak Current Rev. D Page of 6

12 OUTLINE DIMENSIONS PIN BSC COPLANARITY MAX SEATING PLANE MAX PIN COPLANARITY BSC..8 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA COMPLIANT TO JEDEC STANDARDS MO-23-AA Figure Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Figure 3. -Lead Thin Shrink Small Outline Transistor Package [SC7] (KS-) Dimensions shown in millimeters BSC PIN...6 BSC MAX SEATING PLANE.2.9 COPLANARITY. COMPLIANT TO JEDEC STANDARDS MO-3-AB- Figure Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters Rev. D Page 2 of 6

13 PIN INDICATOR MAX SEATING PLANE 4. BSC SQ TOP VIEW.8 MAX.6 TYP BSC SQ.2 REF. MAX.2 NOM.6 MAX.6 BSC.7.6. COPLANARITY MAX EXPOSED PAD (BOTTOM VIEW) 4.9 BSC PIN INDICATOR SQ.9.2 MIN COMPLIANT TO JEDEC STANDARDS MO-22-VGGC Figure Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm 4 mm Body, Very Thin Quad (CP-6-4) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD86AKS-R2 4 C to +8 C -Lead Thin Shrink Small Outline Transistor Package (SC7) KS- ASA AD86AKS-REEL7 4 C to +8 C -Lead Thin Shrink Small Outline Transistor Package (SC7) KS- ASA AD86AKSZ-REEL7 4 C to +8 C -Lead Thin Shrink Small Outline Transistor Package (SC7) KS- AN AD866ARM-R2 4 C to +8 C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA AD866ARM-REEL 4 C to +8 C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA AD866ARMZ-R2 4 C to +8 C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA# AD866ARMZ-REEL 4 C to +8 C 8-Lead Micro Small Outline Package (MSOP) RM-8 ATA# AD867ARU 4 C to +8 C 4-Lead Thin Shrink Small Outline Package (TSSOP) RU-4 AD867ARU-REEL 4 C to +8 C 4-Lead Thin Shrink Small Outline Package (TSSOP) RU-4 AD867ARUZ 4 C to +8 C 4-Lead Thin Shrink Small Outline Package (TSSOP) RU-4 AD867ARUZ-REEL 4 C to +8 C 4-Lead Thin Shrink Small Outline Package (TSSOP) RU-4 AD867ACP-R2 4 C to +8 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-4 AD867ACP-REEL 4 C to +8 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-4 AD867ACP-REEL7 4 C to +8 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-4 AD867ACPZ-R2 4 C to +8 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-4 AD867ACPZ-REEL 4 C to +8 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-4 AD867ACPZ-REEL7 4 C to +8 C 6-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-6-4 Z = Pb-free part, # denotes lead-free product may be top or bottom marked. Rev. D Page 3 of 6

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16 AD86/AD866/AD867 NOTES 26 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C99--2/6(D) Rev. D Page 6 of 6