AD89/AD83/AD84 TABLE OF CONTENTS Specifications... 3 Specifications with ±5 V Supply... 3 Specifications with +5 V Supply... 4 Specifications with +3

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1 Low Power, High Speed Rail-to-Rail Input/Output Amplifier AD89/AD83/AD84 FEATURES Low power.3 ma supply current/amplifier High speed 5 MHz, db bandwidth (G = +) 6 V/µs slew rate 8 ns settling time to.% Rail-to-rail input and output No phase reversal, inputs mv beyond rails Wide supply range:.7 V to V Offset voltage: 6 mv max Low input bias current +.7 µa to.5 µa Small packaging SOIC-8, SC7-6, SOT3-8, SOIC-4, TSSOP-4 APPLICATIONS Battery-powered instrumentation Filters A-to-D drivers Buffering NC IN +IN 3 V S 4 V OUT IN +IN 3 V S 4 NC = NO CONNECT Figure. SOIC-8 (R) CONNECTION DIAGRAMS 8 DISABLE 7 +V S 6 V OUT 5 NC 8 +V S 7 +V OUT 6 IN 5 +IN Figure 3. SOIC-8(R) and SOT3-8 (RJ) 3679-A A-3 V OUT V S +IN 3 V OUT IN +IN 3 +V S 4 +IN 5 IN 6 V OUT V S 5 DISABLE 4 IN Figure. SC7-6 (KS) 3679-A- 4 V OUT 4 3 IN 4 +IN 4 V S +IN 3 9 IN 3 8 V OUT 3 Figure 4. SOIC-4 (R) and TSSOP-4 (RU) 3679-A- GENERAL DESCRIPTION The AD89 (single), AD83 (dual), and AD84 (quad) are powered systems with large bandwidth requirements to high rail-to-rail input and output high speed amplifiers with a speed systems where component density requires lower power quiescent current of only.3 ma per amplifier. Despite their dissipation. low power consumption, the amplifiers provide excellent performance with 5 MHz small signal bandwidth and The AD89/AD83 are the only low power, rail-to-rail input 6 V/µs slew rate. ADI s proprietary XFCB process enables high and output high speed amplifiers available in SOT3 and SC7 speed and high performance on low power. micro packages. The amplifiers are rated over the extended industrial temperature range, C to +5 C. This family of amplifiers exhibits true single-supply operation with rail-to-rail input and output performance for supply 5. voltages ranging from.7 V to V. The input voltage range INPUT 4.5 extends mv beyond each rail without phase reversal. The OUTPUT dynamic range of the output extends to within 4 mv of each 4. rail. 3.5 The AD89/AD83/AD84 provide excellent signal quality with minimal power dissipation. At G = +, SFDR is dbc at MHz and settling time to.% is only 8 ns. Low distortion and fast settling performance make these amplifiers suitable drivers for single-supply A/D converters. The versatility of the AD89/AD83/AD84 allows the user to operate the amplifiers on a wide range of supplies while consuming less than 6.5 mw of power. These features extend the operation time in applications ranging from battery- VOLTAGE (V) G = + V S = +5V R L = kω TIED TO MIDSUPPLY TIME (µs) Figure 5. Rail-to-Rail Response µs/div 3679-A- Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 AD89/AD83/AD84 TABLE OF CONTENTS Specifications... 3 Specifications with ±5 V Supply... 3 Specifications with +5 V Supply... 4 Specifications with +3 V Supply... 5 Absolute Maximum Ratings... 6 Maximum Power Dissipation... 6 Typical Performance Characteristics... 7 Theory of Operation... 5 Input Stage... 5 Applications... 6 Wideband Operation... 6 Output Loading sensitivity... 6 Disable Pin... 7 Circuit Considerations... 8 Design Tools and Technical Support... 8 Outline Dimensions... 9 Ordering Guide... ESD Caution... Output Stage... 5 REVISION HISTORY Revision A /3 Data Sheet Changed from Rev. to Rev. A Change Page Added AD84 part...universal Change to Figure 5... Changes to Specifications... 3 Changes to Figures... 7 Change to Figure Changes to Figures and... 9 Inserted new Figure Change to Figure 4... Inserted new Figure 4... Added Output Loading Sensitivity section... 6 Changes to Table Changes to Power Supply Bypassing section... 8 Changes to Ordering Guide... Rev. A Page of

3 AD89/AD83/AD84 SPECIFICATIONS SPECIFICATIONS WITH ±5 V SUPPLY Table. VS = ±5 TA = 5 C, G = +, RL = kω to ground, unless otherwise noted. All specifications are per amplifier. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VO =. V p-p 8 5 MHz G = +, VO = V p-p 4 9 MHz Bandwidth for. db Flatness G = +, VO =. V p-p 6 MHz Slew Rate G = +, VO = V Step 6 V/µs G =, VO = V Step 63 V/µs Settling Time to.% G = +, VO = V Step 8 ns NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) fc = MHz, VO = V p-p 4 dbc fc = 5 MHz, VO = V p-p 6 dbc Input Voltage Noise f = khz 6.5 nv/ Hz Input Current Noise f = khz. pa/ Hz Crosstalk (AD83/AD84) f = 5 MHz, VIN = V p-p 9 db DC PERFORMANCE Input Offset Voltage PNP Active, VCM = V.6 5 mv NPN Active, VCM = 4.5 V 6 mv Input Offset Voltage Drift TMIN to TMAX 3 µv/ C Input Bias Current NPN Active, VCM = 4.5 V.7.3 µa TMIN to TMAX µa PNP Active, VCM = V.7.8 µa TMIN to TMAX µa Input Offset Current ±. ±.9 µa Open-Loop Gain Vo = ±4. V db INPUT CHARACTERISTICS Input Resistance 6 MΩ Input Capacitance pf Input Common-Mode Voltage Range. to +5. V Common-Mode Rejection Ratio VCM =.5 V to +3 V, RL = kω 8 9 db DISABLE PIN (AD89) DISABLE Low Voltage VS +.8 V DISABLE Low Current.5 µa DISABLE High Voltage VS +. V DISABLE High Current. µa Turn-Off Time 5% of DISABLE to <% of Final VO, 5 ns VIN = V, G = Turn-On Time 5% of DISABLE to <% of Final VO, 85 ns VIN = V, G = OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) VIN = +6 V to V, G = 55/45 ns Output Voltage Swing RL = kω VS +. +VS. V RL = kω VS +.5 +VS.5 V Short-Circuit Current Sinking and Sourcing 7/6 ma Off Isolation (AD89) VIN =. V p-p, f = MHz, DISABLE = Low 5 db Capacitive Load Drive 3% Overshoot pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier.4.5 ma Quiescent Current (Disabled) DISABLE = Low 5 µa Power Supply Rejection Ratio Vs ± V 73 8 db Plus, +, (or no sign) indicates current into pin; minus ( ) indicates current out of pin. Rev. A Page 3 of

4 AD89/AD83/AD84 SPECIFICATIONS WITH +5 V SUPPLY Table. VS = 5 TA = 5 C, G = +, RL = kω to midsupply, unless otherwise noted. All specifications are per amplifier. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VO =. V p-p 8 MHz G = +, VO = V p-p 3 8 MHz Bandwidth for. db Flatness G = +, VO =. V p-p 6 MHz Slew Rate G = +, VO = V Step 55 V/µs G =, VO = V Step 6 V/µs Settling Time to.% G = +, VO = V Step 8 ns NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) fc = MHz, VO = V p-p 3 dbc fc = 5 MHz, VO = V p-p 5 dbc Input Voltage Noise f = khz 6.5 nv/ Hz Input Current Noise f = khz. pa/ Hz Crosstalk (AD83/AD84) f = 5 MHz, VIN = V p-p -79 db DC PERFORMANCE Input Offset Voltage PNP Active, VCM =.5 V.4 5 mv NPN Active, VCM = 4.5 V.8 6 mv Input Offset Voltage Drift TMIN to TMAX 5 µv/ C Input Bias Current NPN Active, VCM = 4.5 V.8. µa TMIN to TMAX µa PNP Active, VCM =.5 V.8.8 µa TMIN to TMAX µa Input Offset Current ±. ±.9 µa Open-Loop Gain Vo = V to 4 V db INPUT CHARACTERISTICS Input Resistance 6 MΩ Input Capacitance pf Input Common-Mode Voltage Range. to +5. V Common-Mode Rejection Ratio VCM =.5 V to V, RL = kω 8 9 db DISABLE PIN (AD89) DISABLE Low Voltage VS +.8 V DISABLE Low Current.5 µa DISABLE High Voltage VS +. V DISABLE High Current. µa Turn-Off Time 5% of DISABLE to <% of Final VO, 55 ns VIN = V, G = Turn-On Time 5% of DISABLE to <% of Final VO, 9 ns VIN = V, G = OUTPUT CHARACTERISTICS Overdrive Recovery Time (Rising/Falling Edge) VIN = V to +6 V, G = 45/5 ns Output Voltage Swing RL = kω VS +.7 +VS.7 V RL = kω VS +.4 +VS.4 V Short-Circuit Current Sinking and Sourcing 95/6 ma Off Isolation (AD89) Vin =. V p-p, f = MHz, DISABLE = Low 5 db Capacitive Load Drive 3% Overshoot 5 pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier.3.5 ma Quiescent Current (Disabled) DISABLE = Low 4 µa Power Supply Rejection Ratio VS ± V 73 8 db Plus, +, (or no sign) indicates current into pin; minus ( ) indicates current out of pin. Rev. A Page 4 of

5 AD89/AD83/AD84 SPECIFICATIONS WITH +3 V SUPPLY Table 3. VS = +3 TA = 5 C, G = +, RL = kω to midsupply, unless otherwise noted. All specifications are per amplifier. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth G = +, VO =. V p-p 8 MHz G = +, VO = V p-p 3 8 MHz Bandwidth for. db Flatness G = +, VO =. V p-p 6 MHz Slew Rate G = +, VO = V Step 55 V/µs G =, VO = V Step 57 V/µs Settling Time to.% G = +, VO = V Step ns NOISE/DISTORTION PERFORMANCE Spurious Free Dynamic Range (SFDR) fc = MHz, VO = V p-p dbc fc = 5 MHz, VO = V p-p dbc Input Voltage Noise f = khz 6.5 nv/ Hz Input Current Noise f = khz. pa/ Hz Crosstalk (AD83/AD84) f = 5 MHz, VIN = V p-p -8 db DC PERFORMANCE Input Offset Voltage PNP Active, VCM =.5 V. 5 mv NPN Active, VCM =.5 V.6 6 mv Input Offset Voltage Drift TMIN to TMAX 4 µv/ C Input Bias Current NPN Active, VCM =.5 V.7. µa TMIN to TMAX µa Input Bias Current PNP Active, VCM =.5 V.5.5 µa TMIN to TMAX.6 µa Input Offset Current ±. ±.9 µa Open-Loop Gain Vo =.5 V to.5 V db INPUT CHARACTERISTICS Input Resistance 6 MΩ Input Capacitance pf Input Common-Mode Voltage Range. to +3. V Common-Mode Rejection Ratio VCM =.5 V to.5 V, RL = kω db DISABLE PIN (AD89) DISABLE Low Voltage VS +.8 V DISABLE Low Current.5 µa DISABLE High Voltage VS +. V DISABLE High Current. µa Turn-Off Time 5% of DISABLE to <% of Final VO, 65 ns VIN = V, G = Turn-On Time 5% of DISABLE to <% of Final VO, 95 ns VIN = V, G = OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) VIN = V to +4 V, G = 75/ ns Output Voltage Swing RL = kω VS +.9 +VS.9 V RL = kω VS +.4 +VS.4 V Short-Circuit Current Sinking and Sourcing 8/4 ma Off Isolation (AD89) VIN =. V p-p, f = MHz, DISABLE = Low 5 db Capacitive Load Drive 3% Overshoot pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier.3.4 ma Quiescent Current (Disabled) DISABLE = Low 45 µa Power Supply Rejection Ratio VS ± V 7 76 db Plus, +, (or no sign) indicates current into pin; minus ( ) indicates current out of pin. Rev. A Page 5 of

6 AD89/AD83/AD84 ABSOLUTE MAXIMUM RATINGS Table 4. AD89/AD83/AD84 Stress Ratings Parameter Rating Supply Voltage.6 V Power Dissipation See Figure 6 Common-Mode Input Voltage ±VS ±.5 V Differential Input Voltage ±.8 V Storage Temperature 5 C to +5 C Operating Temperature Range C to +5 C Lead Temperature Range 3 C (Soldering sec) Junction Temperature 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Airflow will increase heat dissipation, effectively reducing θja. MAXIMUM POWER DISSIPATION Also, more metal directly in contact with the package leads The maximum safe power dissipation in the AD89/AD83/ from metal traces, through holes, ground, and power planes will AD84 package is limited by the associated rise in junction reduce the θja. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately the PCB Layout section. 5 C, which is the glass transition temperature, the plastic Figure 6 shows the maximum safe power dissipation in the changes its properties. Even temporarily exceeding this package versus the ambient temperature for the SOIC-8 temperature limit may change the stresses that the package (5 C/W), SOT3-8 (6 C/W), SOIC-4 (9 C/W), exerts on the die, permanently shifting the parametric TSSOP-4 ( C/W), and SC7-6 (8 C/W) packages on a performance of the AD89/AD83/AD84. Exceeding a JEDEC standard 4-layer board. θja values are approximations. junction temperature of 75 C for an extended period can result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θja), ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as TJ = TA + (PD θja) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/ IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power Load Power) P D = ( V I ) S S VS VOUT V R + L OUT RL RMS output voltages should be considered. If RL is referenced to VS, as in single-supply operation, then the total drive power is VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply: P D = ( V I ) S S + ( V /4) In single-supply operation with RL referenced to VS, worst case is VOUT = VS/. MAXIMUM POWER DISSIPATION (W) SOIC-8 SOT-3-8 SC7-6 TSSOP AMBIENT TEMPERATURE ( C) Output Short Circuit SOIC-4 Figure 6. Maximum Power Dissipation Shorting the output to ground or drawing excessive current from the AD89/AD83/AD84 could cause catastrophic failure. S R L 3679-A-8 Rev. A Page 6 of

7 AD89/AD83/AD84 TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions: VS = 5 V (TA = 5 C, RL = kω tied to midsupply, unless otherwise noted.) NORMALIZED CLOSED-LOOP GAIN (db) 8 9 G = + R F = 9kΩ, R G = kω G = + R F = R G = kω V O =.V p-p. G = R F = R G = kω G = + R F = Ω Figure 7. Small Signal Frequency Response for Various Gains NORMALIZED CLOSED-LOOP GAIN (db) DASHED LINES: V OUT = V p-p SOLID LINES: V OUT =.V p-p G = + G = +.8 Figure.. db Flatness Frequency Response R F = kω 3679-A- CLOSED-LOOP GAIN (db) G = + +3V G = + V O =.V p-p V O =.V p-p R F = kω ±5V ±5V +5V NORMALIZED CLOSED-LOOP GAIN (db) +3V 8 +5V 3679-A- Figure 8. Small Signal Frequency Response for Various Supplies Figure. Small Signal Frequency Response for Various Supplies CLOSED-LOOP GAIN (db) G = + V O = V p-p +5V ±5V +3V NORMALIZED CLOSED-LOOP GAIN (db) G = + V O = V p-p V S = +3 V S = ±5 V S = +5 R F = kω Figure 9. Large Signal Frequency Response for Various Supplies A-3 Figure. Large Signal Frequency Response for Various Supplies Rev. A Page 7 of

8 AD89/AD83/AD84 CLOSED-LOOP GAIN (db) G = + V O =.V p-p pf pf 5pF pf Figure 3. Small Signal Frequency Response for Various CLOAD CLOSED-LOOP GAIN (db) G = + V O =.V p-p V ICM = V S +.V V ICM = V S+.V V ICM = V Figure 6. Small Signal Frequency Response for Various Input Common-Mode Voltages NORMALIZED CLOSED-LOOP GAIN (db) G = + R F = kω CLOSED-LOOP GAIN (db) G = + V O =.V p-p V p-p V p-p.v p-p C +5 C +85 C +5 C A-4 Figure 4. Frequency Response for Various Output Amplitudes Figure 7. Small Signal Frequency Response vs. Temperature OPEN-LOOP GAIN (db) OPEN-LOOP PHASE (Degrees) CLOSED-LOOP GAIN (db) G = + V O = V p-p C +5 C +5 C +85 C k k k M M M G FREQUENCY (Hz) Figure 5. Open-Loop Gain and Phase vs. Frequency Figure 8. Large Signal Frequency Response vs. Temperature Rev. A Page 8 of

9 AD89/AD83/AD84 HARMONIC DISTORTION (dbc) 5 G = + V OUT = V p-p 5 R L = kω SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE V S = +3V V S = +5V V S = ±5V HARMONIC DISTORTION (dbc) 8 9 G = + V OUT = V p-p SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE R L = kω R L = kω R L = 5kΩ Figure 9. Harmonic Distortion vs. Frequency and Supply Voltage Figure. Harmonic Distortion vs. Frequency and Load HARMONIC DISTORTION (dbc) 5 5 G = + FREQ = MHz R F = kω V S = +3V V S = +5V V S = +V HARMONIC DISTORTION (dbc) G = + V OUT = V p-p FREQ = MHz V S = +3V V S = +5V SECOND HARMONIC: SOLID LINE SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE THIRD HARMONIC: DASHED LINE OUTPUT AMPLITUDE (V p-p) 3679-A-5 INPUT COMMON-MODE VOLTAGE (V) Figure. Harmonic Distortion vs. Output Amplitude Figure 3. Harmonic Distortion vs. Input Common Mode Voltage HARMONIC DISTORTION (dbc) 8 V S = +5V V OUT =.V p-p R L = kω R F = kω G = G = + 9 G = + SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE.. Figure. Harmonic Distortion vs. Frequency and Gain 3679-A-6 VOLTAGE NOISE (nv/ Hz) VOLTAGE NOISE CURRENT NOISE. k k k M M FREQUENCY (Hz) Figure 4. Voltage and Current Noise vs. Frequency CURRENT NOISE (pa/ Hz) Rev. A Page 9 of

10 AD89/AD83/AD84 OUTPUT VOLTAGE (mv) G = + V S = ±.5V OUTPUT VOLTAGE (mv) G = + V S = ±.5V C L = pf C L = pf C L = 5pF 5 5 5mV/DIV TIME (ns) ns/div mV/DIV TIME (ns) ns/div Figure 5. Small Signal Transient Response Figure 8. Small Signal Transient Response with Capacitive Load.5. G = + V S = ±.5V 4V p-p INPUT.5 4. OUTPUT VOLTAGE (V) V p-p 3679-A-3 VOLTAGE (V) G = + OUTPUT.5 V S = +5V.5V/DIV 5ns/DIV R L = kω TIED TO MIDSUPPLY µs/div TIME (Seconds) TIME (ns) Figure 6. Large Signal Transient Response Figure 9. Rail-to-Rail Response, G = INPUT G = (R F = kω) R L = kω V S = ±.5V 4 3 INPUT G = + R L = kω V S = ±.5V OUTPUT VOLTAGE (V) OUTPUT OUTPUT VOLTAGE (V) OUTPUT V/DIV TIME (ns) ns/div V/DIV TIME (ns) ns/div Figure 7. Output Overdrive Recovery Figure 3. Input Overdrive Recovery Rev. A Page of

11 AD89/AD83/AD84 +V G = + V S = ±.5V V IN (5mV/DIV) V OUT (5mV/DIV) G = + V OUT V IN (.%/DIV) +.% V OUT V IN (.%/DIV) +.%.%.% V V OUT (5mV/DIV) 5ns/DIV ns/div Figure 3. Long-Term Settling Time Figure 34..% Short-Term Settling Time CMRR (db) PSRR (db) +PSRR 8 PSRR k k k M M M G k k k M M M G FREQUENCY (Hz) FREQUENCY (Hz) Figure 3. Common-Mode Rejection Ratio vs. Frequency Figure 35. PSRR vs. Frequency G = + R L = kω DISABLE = LOW V IN =.V p-p V IN 5Ω DRIVE AMP kω OUTPUT (db) CROSSTALK (db) 8 9 LISTEN AMP V OUT kω CROSSTALK = log ( V OUT V IN ) AD83 (AMP DRIVE AMP LISTEN) AD84 (AMP 4 DRIVE AMP LISTEN) A-5 Figure 33. AD89 Off-Isolation vs. Frequency Figure 36. AD83/AD84 Crosstalk vs. Frequency Rev. A Page of

12 AD89/AD83/AD84 INPUT BIAS CURRENT (µa) V S = +3V V S = +5V V S = +V INPUT OFFSET VOLTAGE (mv) 4 3 R L = kω TO MIDSUPPLY G = + V S = +3V V S = +5V V S = +V INPUT COMMON-MODE VOLTAGE (V) Figure 37. Input Bias Current vs. Input Common-Mode Voltage INPUT COMMON-MODE VOLTAGE (V) 3679-A-7 Figure 4. Input Offset Voltage vs. Input Common-Mode Voltage.. 4 INPUT BIAS CURRENT (PNP ACTIVE) (µa) NPN ACTIVE V S = ±5 V S = +5 V S = INPUT BIAS CURRENT (NPN ACTIVE) (µa) INPUT OFFSET VOLTAGE (mv) 3 V S = ±5V V S = +5V.4 V S = +3V PNP ACTIVE TEMPERATURE ( C) TEMPERATURE ( C) A-6 Figure 38. Input Bias Current vs. Temperature Figure 4. Input Offset Voltage vs. Temperature SUPPLY CURRENT (ma) V S = ±5V V S = +5V V S = +3V FREQUENCY COUNT = 88 MEAN =.44mV STDEV =.5mV TEMPERATURE ( C) Figure 39 Quiescent Supply Current vs. Temperature INPUT OFFSET VOLTAGE (mv) Figure 4. Input Offset Voltage Distribution Rev. A Page of

13 AD89/AD83/AD84 M DISABLE = LOW G = + k OUTPUT IMPEDANCE (Ω) k k OUTPUT IMPEDANCE (Ω) k M M M G FREQUENCY (Hz) k k k M M M G FREQUENCY (Hz) Figure 43. AD89 Output Impedance vs. Frequency, Disabled Figure 45. Output Impedance vs. Frequency, Enabled OUTPUT SATURATION VOLTAGE (V) LOAD RESISTANCE TIED TO MIDSUPPLY V OL V S INPUT ERROR VOLTAGE (mv) V S = ±.5V R L = kω V S = +3V V S = +5V V S = ±5V R L = kω.5 V OH V S..5.5 LOAD RESISTANCE (Ω) Figure 44. Output Saturation Voltage vs. Load Resistance OUTPUT VOLTAGE (V) Figure 46. Input Error Voltage vs. Output Voltage OUTPUT SATURATION VOLTAGE (mv) V S = ±5V V S = +5V 5 V S = +3V R L = kω TIED TO MIDSUPPLY SOLID LINE: V S+ VOH DASHED LINE: VOL V S TEMPERATURE ( C) Figure 4. Output Saturation Voltage vs. Temperature Rev. A Page 3 of

14 AD89/AD83/AD84 OUTPUT AMPLITUDE (V) R L = Ω R L = kω R L = kω DISABLE (.5V TO V) OUTPUT DISABLED V S = ±.5V G = (R F = kω) TIME (ns) Figure 47. AD89 DISABLE Turn-Off Timing 3679-A- DISABLE PIN CURRENT (µa) V S = +3V, +5V, +V.8. 3 DISABLE PIN VOLTAGE (V) 3679-A- Figure 49. AD89 DISABLE Pin Current vs. DISABLE Pin Voltage.5. DISABLE (V TO.5V) OUTPUT ENABLED OUTPUT AMPLITUDE (V) R L = Ω R L = kω R L = kω V S = ±.5V G = (R F = kω) TIME (ns) 3679-A- Figure 48. AD89 DISABLE Turn-On Timing Rev. A Page 4 of

15 AD89/AD83/AD84 THEORY OF OPERATION +V S DISABLE TO DISABLE CIRCUITRY R TH +V S.V I TH V S I SPD TAIL Q 9 R R R 3 R 4 OUTPUT BUFFER AD89 ONLY IN Q 5 Q 6 Q Q M TOP C MT Q V OUT C MB Q 7 Q 8 Q 3 IN+ Q 4 M BOT R 5 R 6 R 7 R 8 Q OUT COM IN V S Figure 5. Simplified Schematic The AD89 (single), AD83 (dual), and AD84 (quad) are OUTPUT STAGE rail-to-rail input and output amplifiers fabricated using Analog The currents derived from the PNP and NPN input differential Devices XFCB process. The XFCB process enables the AD89/ pairs are injected into the current mirrors MBOT and MTOP, thus AD83/AD84 to operate on.7 V to V supplies with a establishing a common-mode signal voltage at the input of the MHz bandwidth and a 6 V/µs slew rate. A simplified schematic of the AD89/AD83/AD84 is shown in Figure 5. output buffer. The output buffer performs three functions: INPUT STAGE For input common-mode voltages less than a set threshold (. V below VCC), the resistor degenerated PNP differential pair (comprising Q toq4) carries the entire ITAIL current, allowing the input voltage to go mv below VS. Conversely, input common-mode voltages exceeding the same threshold cause ITAIL to be routed away from the PNP differential pair and into the NPN differential pair through transistor Q9. Under this condition, the input common-mode voltage is allowed to rise mv above +VS while still maintaining linear amplifier behavior. The transition between these two modes of operation leads to a sudden, temporary shift in input stage transconductance, gm, and dc parameters (such as the input offset voltage VOS), which in turn adversely affect the distortion performance. The SPD block shortens the duration of this transition, thus improving the distortion performance. As shown in Figure 5, the input differential pair is protected by a pair of two series diodes, connected in anti-parallel, which clamp the differential input voltage to approximately ±.5 V.. It buffers and applies the desired signal voltage to the output devices, Q and Q.. It senses the common-mode current level in the output devices. 3. It regulates the output common-mode current by establishing a common-mode feedback loop. The output devices Q and Q work in a common-emitter configuration, and are Miller-compensated by internal capacitors, CMT and CMB. The output voltage compliance is set by the output devices collector resistance RC (about 5 Ω), and by the required load current IL. For instance, a light equivalent load (5 kω) allows the output voltage to swing to within 4 mv of either rail, while heavier loads cause this figure to deteriorate as RC IL. Rev. A Page 5 of

16 AD89/AD83/AD84 APPLICATIONS WIDEBAND OPERATION V IN R G R R = R F R G + R F +V S AD89 V S C µf C.µF C4.µF C3 µf DISABLE V OUT Figure 5. Wideband Non-inverting Gain Configuration R F +V S C µf For example, if using the values shown in Table 5 for a gain of, with resistor values of.5 kω, the effective load at the output is.67 kω. For inverting configurations, only the feedback resistor RF is in parallel with the output load. If the load is greater than that specified in the data sheet, the amplifier can introduce nonlinearities in its open-loop response, which increases distortion. Figure 53 and Figure 54 illustrate effective output loading and distortion performance. Increasing the resistance of the feedback network can reduce the current consumption, but has other implications. HARMONIC DISTORTION (dbc) V S = 5V V OUT =.V.V p-p SECOND HARMONIC SOLID LINES THIRD HARMONIC DOTTED LINES 8 C.µF 9 R L = 5kΩ R G V IN R L =.5kΩ AD89 V OUT + DISABLE R = R F R G C4....µF R C3 µf Figure 53. Gain of Distortion R L = kω 3679-A-8 V S Figure 5. Wideband Inverting Gain Configuration OUTPUT LOADING SENSITIVITY To achieve maximum performance and low power dissipation, the designer needs to consider the loading at the output of AD89/AD83/AD84. Table 5 shows the effects of output loading and performance. When operating at unity gain, the effective load at the amplifier output is the resistance (RL) being driven by the amplifier. For gains other than, in noninverting configurations, the feedback network represents an additional current load at the amplifier output. The feedback network (RF + RG) is in parallel with RL, which lowers the effective resistance at the output of the amplifier. The lower effective resistance causes the amplifier to supply more current at the output. Lower values of feedback resistance increase the current draw, thus increasing the amplifier s power dissipation. HARMONIC DISTORTION (dbc) V S = 5V V OUT =.V.V p-p SECOND HARMONIC SOLID LINES THIRD HARMONIC DOTTED LINES R F = R L = kω 8 9. R F = R L =.5kΩ R F = R L = 5kΩ.. Figure 54. Gain of Distortion 3679-A-9 Rev. A Page 6 of

17 AD89/AD83/AD84 Table 5. Effect of Load on Performance Noninverting Gain RF (kω) RG (kω) RLOAD (kω) db SS BW (MHz) Peaking (db) HD at MHz, V p-p (db) HD3 at MHz, V p-p (db) N/A N/A N/A Output Noise (nv/ Hz) The feedback resistance (RF RG) combines with the input DISABLE PIN capacitance to form a pole in the amplifier s loop response. This The AD89 disable pin allows the amplifier to be shut down can cause peaking and ringing in the amplifier s response if the for power conservation or multiplexing applications. When in RC time constant is too low. Figure 55 illustrates this effect. the disable mode, the amplifier draws only 5 µa of quiescent Peaking can be reduced by adding a small capacitor ( pf pf) current. The disable pin control voltage is referenced to the across the feedback resistor. The best way to find the optimal negative supply. The amplifier enters power-down mode any value of capacitor is to empirically try it in your circuit. Another time the disable pin is tied to the most negative supply or within factor of higher resistance values is the impact it has on noise.8 V of the negative supply. If left open, the amplifier will performance. Higher resistor values generate more noise. Each operate normally. For switching levels, refer to Table 6. application is unique and therefore a balance must be reached between distortion, peaking, and noise performance. Table 5 Table 6. Disable Pin Control Voltage outlines the trade-offs that different loads have on distortion, Disable Pin Supply Voltage peaking, and noise performance. In gains of,, and, Voltage +3 V +5 V ±5 V equivalent loads of kω, kω, and 5 kω are shown. With increasing load resistance, the distortion and db bandwidth improve, while the noise and peaking degrade slightly. Low (Disabled) V to <.8 V V to <.8 V V to <. V High (Enabled). V to 3 V. V to 5 V.8 V to +5 V NORMALIZED CLOSED-LOOP GAIN (db) V S = 5V V OUT =.V p-p R F = R L =.5kΩ R F = R L = kω G = + R F = R L = 5kΩ R L = kω R L =.5kΩ R L = 5kΩ G = A-7 Figure 55. Frequency Response for Various Feedback/Load Resistances Rev. A Page 7 of

18 AD89/AD83/AD84 CIRCUIT CONSIDERATIONS PCB Layout High speed op amps require careful attention to PCB layout to achieve optimum performance. Particular care must be exercised to minimize lead lengths of the bypass capacitors. Excess lead inductance can influence the frequency response and even cause high frequency oscillations. Using a multilayer board with an internal ground plane can help reduce ground noise and enable a more compact layout. To achieve the shortest possible trace length at the inverting input, the feedback resistor, RF, should be located the shortest distance from the output pin to the input pin. The return node of the resistor RG should be situated as close as possible to the return node of the negative supply bypass capacitor. On multilayer boards, all layers beneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. This is especially true at the summing junction, i.e., the inverting input, IN. Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin. Grounding To minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. Understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and thus the high frequency impedance of the path. Fast current changes in an inductive ground return will create unwanted noise and ringing. The length of the high frequency bypass capacitor pads and traces is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from supplies as well as from ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. Power Supply Bypassing Power supply pins are actually inputs to the op amp. Care must be taken to provide the op amp with a clean, low noise dc voltage source. Power supply bypassing is employed to provide a low impedance path to ground for noise and undesired signals at all frequencies. This cannot be achieved with a single capacitor type; but with a variety of capacitors in parallel the bandwidth of power supply bypassing can be greatly extended. The bypass capacitors have two functions:. Provide a low impedance path for noise and undesired signals from the supply pins to ground.. Provide local stored charge for fast switching conditions and minimize the voltage drop at the supply pins during transients. This is typically achieved with large electrolytic capacitors. Good quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package. A parallel combination of a. µf ceramic and a µf electrolytic covers a wide range of rejection for unwanted noise. The µf capacitor is less critical for high frequency bypassing and, in most cases, one per supply line is sufficient. The values of capacitors are circuit-dependant and should be determined by the system s requirements. DESIGN TOOLS AND TECHNICAL SUPPORT Analog Devices is committed to the design process by providing technical support and online design tools. ADI offers technical support via free evaluation boards, sample ICs, Spice models, interactive evaluation tools, application notes, phone and support all available at Rev. A Page 8 of

19 AD89/AD83/AD84 OUTLINE DIMENSIONS 5. (.968) 4.8 (.89) 8.75 (.3445) 8.55 (.3366) 4. (.574) 3.8 (.497) (.44) 5.8 (.84) 4. (.575) 3.8 (.496) (.44) 5.8 (.83).5 (.98). (.4) COPLANARITY..7 (.5) BSC SEATING PLANE.75 (.688).35 (.53).5 (.).3 (.).5 (.98).7 (.67) 8.5 (.96).5 (.99) 45.7 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Lead Standard Small Outline Package, Narrow Body [SOIC] (R-8) Dimensions shown in millimeters and (inches).5 (.98). (.39) COPLANARITY..7 (.5) BSC.5 (.).3 (.).75 (.689).35 (.53) SEATING PLANE.5 (.98).7 (.67) 8.5 (.97).5 (.98) 45.7 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Lead Standard Small Outline Package [SOIC] (R-4) Dimensions shown in millimeters and (inches). BSC BSC BSC PIN BSC BSC.3 BSC MAX.7 PIN BSC. MAX SEATING.8.. PLANE MAX.9. COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-3AB Figure Lead Plastic Surface-Mount Package [SC7] (KS-6) Dimensions shown in millimeters SEATING PLANE COPLANARITY. 8 COMPLIANT TO JEDEC STANDARDS MO-53AB- Figure 6. 4-Lead Thin Shrink Small Outline Package [TSSOP] (RU-4) Dimensions shown in millimeters BSC BSC.8 BSC PIN.95 BSC.65 BSC.5 MAX MAX..8 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-78BA Figure Lead Small Outline Transistor Package [SOT3] (RJ-8) Dimensions shown in millimeters Rev. A Page 9 of

20 AD89/AD83/AD84 ORDERING GUIDE Model Minimum Ordering Quantity Temperature Range Package Description Package Option Branding AD89AR C to +5 C 8-Lead SOIC R-8 AD89AR-REEL,5 C to +5 C 8-Lead SOIC R-8 AD89AR-REEL7, C to +5 C 8-Lead SOIC R-8 AD89AKS-R 5 C to +5 C 6-Lead SC7 KS-6 H6B AD89AKS-REEL, C to +5 C 6-Lead SC7 KS-6 H6B AD89AKS-REEL7 3, C to +5 C 6-Lead SC7 KS-6 H6B AD83AR C to +5 C 8-Lead SOIC R-8 AD83AR-REEL,5 C to +5 C 8-Lead SOIC R-8 AD83AR-REEL7, C to +5 C 8-Lead SOIC R-8 AD83ARJ-R 5 C to +5 C 8-Lead SOT3-8 RJ-8 H7B AD83ARJ-REEL, C to +5 C 8-Lead SOT3-8 RJ-8 H7B AD83ARJ-REEL7 3, C to +5 C 8-Lead SOT3-8 RJ-8 H7B AD84AR C to +5 C 4-Lead SOIC R-4 AD84AR-REEL 5 C to +5 C 4-Lead SOIC R-4 AD84AR-REEL7 C to +5 C 4-Lead SOIC R-4 AD84ARU C to +5 C 4-Lead TSSOP RU-4 AD84ARU-REEL 5 C to +5 C 4-Lead TSSOP RU-4 AD84ARU-REEL7 C to +5 C 4-Lead TSSOP RU-4 ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 3 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C3679 /3(A) Rev. A Page of