ADA484-/ADA484- TABLE OF CONTENTS Features... Applications... Connection Diagrams... General Description... Revision History... Specifications... Abso

Transcription

1 FEATURES Low power:. ma/amp Low wideband noise. nv/ Hz.4 pa/ Hz Low /f noise 7 nv/ Hz pa/ Hz Low distortion: 5 khz, VO = V p-p High speed 8 MHz, db bandwidth (G = +) V/μs slew rate 75 ns settling time to.% Low offset voltage:. mv maximum Rail-to-rail output Power down Wide supply range:.7 V to V APPLICATIONS Low power, low noise signal processing Battery-powered instrumentation 6-bit PulSAR ADC drivers GENERAL DESCRIPTION Low Power, Low Noise and Distortion, Rail-to-Rail Output Amplifier ADA484-/ADA484- CONNECTION DIAGRAMS ADA484- TOP VIEW NC (Not to Scale) 8 POWER DOWN IN 7 +V S +IN 6 V OUT V S 4 5 NC Figure. 8-Lead SOIC (R) ADA484- OUT IN +IN V S 4 8 +V S 7 OUT 6 IN 5 +IN TOP VIEW (Not to Scale) Figure. 8-Lead MSOP (RM-8) and 8-Lead SOIC_N (R) V OUT ADA484- V S 5 POWER DOWN +IN 4 IN The ADA484-/ADA484- are unity gain stable, low noise and distortion, rail-to-rail output amplifiers that have a quiescent current of.5 ma maximum. Despite their low power consumption, these amplifiers offer low wideband voltage noise performance of. nv/ Hz and.4 pa/ Hz current noise, along with excellent spurious-free dynamic range (SFDR) of 5 dbc at khz. To maintain a low noise environment at lower frequencies, the amplifiers have low /f noise of 7 nv/ Hz and pa/ Hz at Hz. The ADA484-/ADA484- output can swing to less than 5 mv of either rail. The input common-mode voltage range extends down to the negative supply. The ADA484-/ ADA484- can drive up to pf of capacitive load with minimal peaking. The ADA484-/ADA484- provide the performance required to efficiently support emerging 6-bit to 8-bit ADCs and are ideal for portable instrumentation, high channel count, industrial measurement, and medical applications. The ADA484-/ ADA484- are ideally suited to drive the AD7685/AD7686, 6-bit PulSAR ADCs. 6 +V S Figure. 6-Lead SOT- (RJ) The ADA484-/ADA484- packages feature Pb-free lead finish. The amplifiers are rated to work over the industrial temperature range ( 4 C to +5 C). HARMONIC DISTORTION (dbc) G = + V p-p SECOND.. Figure 4. Harmonic Distortion V p-p THIRD Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 ADA484-/ADA484- TABLE OF CONTENTS Features... Applications... Connection Diagrams... General Description... Revision History... Specifications... Absolute Maximum Ratings... 6 Thermal Resistance... 6 ESD Caution... 6 Typical Performance Characteristics... 7 Theory of Operation... Amplifier Description... DC Errors... Headroom Considerations... 4 Capacitance Drive... 5 Input Protection... 5 Power-Down Operation... 6 Applications... 7 Typical Performance Values Bit ADC Driver... 7 Reconstruction Filter... 7 Layout Considerations... 8 Ground Plane... 8 Power Supply Bypassing... 8 Outline Dimensions... 9 Ordering Guide... Noise Considerations... REVISION HISTORY /6 Rev. B to Rev. C Added SOT- Package...Universal Changes to General Description... Changes to Table... Changes to Table... 4 Changes to Table... 5 Changes to Input Protection Section... 5 Changes to Ordering Guide... /5 Rev. A to Rev. B Added ADA Universal Changes to General Description and Features... Changes to Table... Changes to Table... 4 Changes to Table... 5 Changes to Table 4, Table 5, and Figure Changes to Figure Changes to Figure, Figure, Figure 5, and Figure Deleted Figure 5; Renumber Sequentially... Changes to Figure 4 and Figure 8... Changes to Figure... Inserted Figure 7; Renumber Sequentially... Changes to Amplifier Description Section and Figure 9... Changed DC Performance Considerations Section to DC Errors Section... Changes to Noise Considerations Section... 4 Changes to Headroom Considerations Section and Figure 9 5 Changes to Power-Down Operation Section... 6 Changes to 6-Bit ADC Driver Section, Figure 48, and Figure Changes to Power Supply Bypassing Section... 8 Updated Outline Dimensions... 9 Changes to Ordering Guide... 9/5 Rev. to Rev. A Changes to Features... Changes to Figure... Changes to Figure...8 Changes to Figure Changes to Headroom Considerations Section /5 Revision : Initial Version Rev. C Page of

3 SPECIFICATIONS TA = 5 C, VS = ±5 V, RL = kω, Gain = +, unless otherwise noted. ADA484-/ADA484- Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth VO =. V p-p 58 8 MHz VO = V p-p MHz Slew Rate G = +, VO = 9 V step, RL = kω V/μs Settling Time to.% G = +, VO = 8 V step 65 ns Settling Time to.% G = +, VO = 8 V step ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion HD/HD fc = khz, VO = V p-p, G = + / 5 dbc fc = MHz, VO = V p-p 8/ 67 dbc Input Voltage Noise f = khz. nv/ Hz Input Current Noise f = khz.4 pa/ Hz DC PERFORMANCE Input Offset Voltage 4 μv Input Offset Voltage Drift μv/ C Input Bias Current 5. μa Input Offset Current..5 μa Open-Loop Gain VO = ±4 V db INPUT CHARACTERISTICS Input Resistance, Common Mode 9 MΩ Input Resistance, Differential Mode 5 kω Input Capacitance, Common Mode pf Input Capacitance, Differential Mode pf Input Common-Mode Voltage Range V Common-Mode Rejection Ratio (CMRR) VCM = Δ 4 V 95 5 db MATCHING CHARACTERISTICS (ADA484-) Input Offset Voltage 7 μv Input Bias Current 6 na POWER DOWN PIN (ADA484-) POWER DOWN Voltage Enabled >.6 V POWER DOWN Voltage Power down <. V Input Current Enable POWER DOWN = +5 V μa Power Down POWER DOWN = 5 V μa Switching Speed Enable μs Power Down 4 μs OUTPUT CHARACTERISTICS Output Voltage Swing G > + ±4.9 ±4.955 V Output Current Limit Sourcing, VIN = +VS, RL = 5 Ω to GND ma Sinking, VIN = VS, RL = 5 Ω to GND 6 ma Capacitive Load Drive % overshoot 5 pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier POWER DOWN = +5 V..5 ma POWER DOWN = 5 V 4 9 μa Positive Power Supply Rejection Ratio +VS = +5 V to +6 V, VS = 5 V 95 db Negative Power Supply Rejection Ratio +VS = +5 V, VS = 5 V to +6 V 96 db Rev. C Page of

4 ADA484-/ADA484- TA = 5 C, VS = 5 V, RL = kω, Gain = +, VCM =.5 V, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth VO =. V p-p 54 8 MHz VO = V p-p MHz Slew Rate G = +, VO = 4 V step, RL = kω V/μs Settling Time to.% G = +, VO = V step 75 ns Settling Time to.% G = +, VO = V step 55 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion HD/HD fc = khz, VO = V p-p 9/ 5 dbc fc = MHz, VO = V p-p 78/ 66 dbc Input Voltage Noise f = khz. nv/ Hz Input Current Noise f = khz.4 pa/ Hz Crosstalk f = khz 7 db DC PERFORMANCE Input Offset Voltage 4 μv Input Offset Voltage Drift μv/ C Input Bias Current 5. μa Input Offset Current..4 μa Open-Loop Gain VO =.5 V to 4.5 V 4 db INPUT CHARACTERISTICS Input Resistance, Common Mode 9 MΩ Input Resistance, Differential Mode 5 kω Input Capacitance, Common Mode pf Input Capacitance, Differential Mode pf Input Common-Mode Voltage Range. +4 V Common-Mode Rejection Ratio (CMRR) VCM = Δ.5 V 88 5 db MATCHING CHARACTERISTICS (ADA484-) Input Offset Voltage 7 μv Input Bias Current 7 na POWER DOWN PIN (ADA484-) POWER DOWN Voltage Enabled >.6 POWER DOWN Voltage Power down <. V Input Current Enable POWER DOWN = 5 V μa Power Down POWER DOWN = V μa Switching Speed Enable μs Power Down 4 μs OUTPUT CHARACTERISTICS Output Voltage Swing G > +.8 to to V Output Current Limit Sourcing, VIN = +VS, RL = 5 Ω to VCM ma Sinking, VIN = VS, RL = 5 Ω to VCM 6 ma Capacitive Load Drive % overshoot 5 pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier POWER DOWN = 5 V..4 ma POWER DOWN = V 5 7 μa Positive Power Supply Rejection Ratio +VS = +5 V to +6 V, VS = V 95 db Negative Power Supply Rejection Ratio +VS = +5 V, VS = V to V 96 db Rev. C Page 4 of

5 TA = 5 C, VS = V, RL = kω, Gain =+, VCM =.5 V, unless otherwise noted. ADA484-/ADA484- Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE db Bandwidth VO =. V p-p 5 8 MHz Slew Rate G = +, VO = V step, RL = kω V/μs Settling Time to.% G = +, VO = V step ns Settling Time to.% G = +, VO = V step 5 ns NOISE/HARMONIC PERFORMANCE Harmonic Distortion HD/HD fc = khz, VO = V p-p 97/ dbc fc = MHz, VO = V p-p 79/ 8 dbc Input Voltage Noise f = khz. nv/ Hz Input Current Noise f = khz.4 pa/ Hz DC PERFORMANCE Input Offset Voltage 4 μv Input Offset Voltage Drift μv/ C Input Bias Current 5. μa Input Offset Current..5 μa Open-Loop Gain VO =.5 V to.5 V db INPUT CHARACTERISTICS Input Resistance, Common Mode 9 MΩ Input Resistance, Differential Mode 5 kω Input Capacitance, Common Mode pf Input Capacitance, Differential Mode pf Input Common-Mode Voltage Range. + V Common-Mode Rejection Ratio (CMRR) VCM = Δ.4 V 86 5 db MATCHING CHARACTERISTICS (ADA484-) Input Offset Voltage 7 μv Input Bias Current 6 na POWER DOWN PIN (ADA484-) POWER DOWN Voltage Enabled >.6 POWER DOWN Voltage Power down <. V Input Current Enable POWER DOWN = V μa Power Down POWER DOWN = V μa Switching Speed Enable μs Power Down 4 μs OUTPUT CHARACTERISTICS Output Voltage Swing G > +.45 to.955. to.988 V Output Current Limit Sourcing, VIN = +VS, RL = 5 Ω to VCM ma Sinking, VIN = VS, RL = 5 Ω to VCM 6 ma Capacitive Load Drive % overshoot pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier POWER DOWN = V.. ma POWER DOWN = V 5 6 μa Positive Power Supply Rejection Ratio +VS = + V to +4 V, VS = V 95 db Negative Power Supply Rejection Ratio +VS = + V, VS = V to V 96 db Rev. C Page 5 of

6 ADA484-/ADA484- ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage.6 V Power Dissipation See Figure 5 Common-Mode Input Voltage VS.5 V to +VS +.5 V Differential Input Voltage ±.8 V Storage Temperature Range 65 C to +5 C Operating Temperature Range 4 C to +85 C Lead Temperature JEDEC J-STD- Junction Temperature 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θja is specified for the worst-case conditions, that is, θja is specified for device soldered in circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type θja Unit 8-lead SOIC_N 5 C/W 8-lead MSOP C/W 6-Lead SOT- 7 C/W Maximum Power Dissipation The maximum safe power dissipation for the ADA484-/ ADA484- is limited by the associated rise in junction temperature (TJ) on the die. At approximately 5 C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a junction temperature of 5 C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the amplifier s drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power + (Total Drive Power Load Power) P D = ( V I ) S S VS V + RL OUT V R OUT RMS output voltages should be considered. If RL is referenced to VS, as in single-supply operation, the total drive power is VS IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. P D = ( V I ) S S + ( V /4) S R L In single-supply operation with RL referenced to VS, worst case is VOUT = VS/. Airflow increases heat dissipation, effectively reducing θja. In addition, more metal directly in contact with the package leads and through holes under the device reduces θja. Figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead MSOP (45 C/W), 8-lead SOIC_N (5 C/W) and the 6-lead SOT- (7 C/W) on a JEDEC standard 4-layer board. θja values are approximations. MAXIMUM POWER DISSIPATION (W) SOIC SOT- MSOP AMBIENT TEMPERATURE ( C) Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. L Rev. C Page 6 of

7 ADA484-/ADA484- TYPICAL PERFORMANCE CHARACTERISTICS RL = kω, unless otherwise noted. NORMALIZED CLOSED-LOOP GAIN (db) 6 9 V OUT = V pp G = + G = +. G = GAIN (db) 6 V IN = mv p-p G = C +5 C +5 C Figure 6. Large Signal Frequency Response vs. Gain Figure 9. Small Signal Frequency Response vs. Temperature CLOSED-LOOP GAIN (db) 6 6 V IN = mv p-p G = + pf WITH Ω SNUBBER pf pf pf GAIN (db) 4 V IN = mv p-p G = + V S = +V V S = +5V Figure 7. Small Signal Frequency Response vs. Capacitive Load Figure. Small Signal Frequency Response vs. Supply Voltage NORMALIZED CLOSED-LOOP GAIN (db) 6 9 V IN = mv p-p G = + G = G = GAIN (db) 6 G = + V p-p 4mV p-p 9. mv p-p mv p-p mv p-p Figure 8. Small Signal Frequency Response vs. Gain Figure. Frequency Response for Various VOUT Rev. C Page 7 of

8 ADA484-/ADA484- OPEN-LOOP GAIN (db) MAGNITUDE 4 PHASE k k k M M M FREQUENCY (Hz) Figure. Open-Loop Gain and Phase vs. Frequency OPEN-LOOP PHASE (Degrees) HARMONIC DISTORTION (dbc) V OUT = V p-p G = + +V SECOND +V THIRD +5V SECOND ±5V THIRD +5V THIRD ±5V SECOND.. Figure 5. Harmonic Distortion vs. Frequency for Various Supplies V S = + 5V V OUT = V p-p HARMONIC DISTORTION (dbc) 5 G = +5 THIRD G = + SECOND 9 G = +5 SECOND G = + SECOND G = + THIRD G = + THIRD.. k k k M M FREQUENCY (Hz) VOLTAGE NOISE (nv/ Hz) Figure. Harmonic Distortion vs. Frequency for Various Gains Figure 6. Voltage Noise vs. Frequency HARMONIC DISTORTION (dbc) G = + 8V p-p SECOND 8V p-p THIRD 4V p-p THIRD 4V p-p SECOND V p-p THIRD V p-p SECOND.. Figure 4. Harmonic Distortion vs. Frequency for Various Output Voltages CURRENT NOISE (pa/ Hz). k k k M FREQUENCY (Hz) Figure 7. Current Noise vs. Frequency Rev. C Page 8 of

9 ADA484-/ADA484- NUMBER OF PARTS 55 COUNT = 9 5 x =.6μV/ C σ =.μv/ C OUTPUT VOLTAGE (V) G = + TIME = 5ns/DIV V S = +5V V S = +V OFFSET DRIFT DISTRIBUTION (μv/ C) Figure 8. Input Offset Voltage Drift Distribution Figure. Small Signal Transient Response for Various Supplies NONLINEARITY (μv) G = V IN (V) 564- OUTPUT VOLTAGE (V) G = + V IN = mv p-p TIME = 5ns/DIV pf pf pf 47pF 564- Figure 9. Nonlinearity vs. VIN Figure. Small Signal Transient Response for Various Capacitive Loads 8 V S = ±5..5 G = + TIME = 5ns/DIV V S = V 6. V OFFSET (μv) 4 OUTPUT VOLTAGE (V) V OUT (V) Figure. Input Error Voltage vs. Output Voltage Figure. Small Signal Transient Response for Various Supplies Rev. C Page 9 of

10 ADA484-/ADA484- INPUT AND OUTPUT VOLTAGE (V) V IN V OUT G = + TIME = ns/div OUTPUT VOLTAGE (V) C 4 C +5 C G = + V S = 5 TIME = ns/div Figure 4. Input Overdrive Recovery Figure 7. Slew Rate vs. Temperature INPUT AND OUTPUT VOLTAGE (V) V IN V OUT G = + TIME = ns/div 564- EXPANDED V OUT (mv) V IN V OUT G = + V OUT = V p-p TIME = ns/div V OUT (EXPANDED) V IN AND V OUT (V) Figure 5. Output Overdrive Recovery Figure 8. Settling Time.5. V OUT = V p-p TIME = ns/div 6 5 POWER DOWN PIN +5 C.. OUTPUT VOLTAGE (V).5.5 G = + G = + POWER DOWN PIN (V) 4 4 C +5 C V OUT (V) G = + V IN = V DC TIME = ns/div Figure 6. Large Signal Transient Response for Various Gains Figure 9. Power-Up Time vs. Temperature Rev. C Page of

11 ADA484-/ADA484- POWER DOWN PIN (V) POWER DOWN PIN POWER DOWN PIN +5 C +5 C 4 C G = + V IN = V DC TIME = μs/div V OUT (V) POWER SUPPLY REJECTION (db) 4 +PSR 6 8 PSR k k k M M M FREQUENCY (Hz) Figure. POWER DOWN Time vs. Temperature Figure. PSR vs. Frequency SUPPLY CURRENT/AMPLIFIER (ma) C +5 C 4 C k k k M M M POWER DOWN PIN (V) FREQUENCY (Hz) CLOSED-LOOP OUTPUT IMPEDANCE (Ω) Figure. Supply Current per Amplifier vs. POWER DOWN Pin Voltage Figure 4. Output Impedance vs. Frequency COMMON-MODE REJECTION (db) G = k k k M M M FREQUENCY (Hz) Figure. CMR vs. Frequency INPUT OFFSET VOLTAGE (μv) 4 V S = +5V V S = +V TEMPERATURE ( C) Figure 5. Input Offset Voltage vs. Temperature for Various Supplies Rev. C Page of

12 ADA484-/ADA484- INPUT BIAS CURRENT (μa) V S = +5V V S = +V CROSSTALK (db) G=+ V S =5V R L =kω ATOB BTOA TEMPERATURE ( C) k k M M M G FREQUENCY (Hz) Figure 6. Input Bias Current vs. Temperature for Various Supplies Figure 8. Crosstalk Output to Output.6.5 SUPPLY CURRENT (ma) V S = +5V.9 V S = +V TEMPERATURE ( C) Figure 7. Supply Current vs. Temperature for Various Supplies Rev. C Page of

13 THEORY OF OPERATION AMPLIFIER DESCRIPTION The ADA484-/ADA484- are low power, low noise, precision voltage-feedback op amps for single or dual voltage supply operation. The ADA484-/ADA484- are fabricated on ADI s second generation XFCB process and feature trimmed supply current and offset voltage. The. nv/ Hz voltage noise (very low for a. ma supply current amplifier), 4 μv offset voltage, and sub μv/ C offset drift is accomplished with an input stage made of an undegenerated PNP input pair driving a symmetrical folded cascode. A rail-to-rail output stage provides the maximum linear signal range possible on low voltage supplies and has the current drive capability needed for the relatively low resistance feedback networks required for low noise operation. CMRR, PSRR, and open-loop gain are all typically above db, preserving the precision performance in a variety of configurations. Gain bandwidth is kept high for this power level to preserve the outstanding linearity performance for frequencies up to khz. The ADA484- has a powerdown function to further reduce power consumption. All this results in a low noise, power efficient, precision amplifier that is well-suited for high resolution and precision applications. V IN + V IP + R G R S I B + V OUT I B + R F + V OS Figure 9. Typical Connection Diagram and DC Error Sources This reduces to the familiar forms for inverting and noninverting op amp gain expressions R = + VIP () F V OUT RG (Noninverting gain, VIN = V) V R F OUT = VIN R () G (Inverting gain, VIP = V) ADA484-/ADA484- The total output voltage error is the sum of errors due to the amplifier offset voltage and input currents. The output error due to the offset voltage can be estimated as V OUTERROR V where: VOFFSET NOM = OFFSETNOM + VCM CMRR V + P V PSRR PNOM V + A OUT R + R is the offset voltage at the specified supply voltage. This is measured with the input and output at midsupply. VCM is the common-mode voltage. VP is the power supply voltage. Vp NOM is the specified power supply voltage. CMRR is the common-mode rejection ratio. PSRR is the power supply rejection ratio. A is the dc open-loop gain. DC ERRORS Figure 9 shows a typical connection The output error due to the input currents can be estimated as diagram and the major dc error sources. The ideal transfer function (all error sources set R to and infinite dc gain) can be written as = + F R + F VOUT ERROR ( RF RG ) I B RS I B+ (5) RG RG R F R F V OUT = V + IP VIN R G R () Note that setting RS equal to RF RG compensates for the voltage G error due to the input bias current. NOISE CONSIDERATIONS Figure 4 illustrates the primary noise contributors for the typical gain configurations. The total rms output noise is the root-mean-square of all the contributions. vn _ R G = vn _ R S = 4kT R G 4kT R S R G R S ien + vout_en ien R F ven vn _ R F = Figure 4. Noise Sources in Typical Connection F G 4kT R F (4) Rev. C Page of

14 ADA484-/ADA484- The output noise spectral density can be calculated by vout _ en = [ R F 4kTRs + ien RS + ven ] + 4kTRg + ien R R F 4kTRf + + F R G R G (6) where: k is Boltzmann s Constant. T is the absolute temperature, degrees Kelvin. ien is the amplifier input current noise spectral density, pa/ Hz. ven is the amplifier input voltage spectral density, nv/ Hz. RS is the source resistance as shown in Figure 4. RF and RG are the feedback network resistances, as shown in Figure 4. Source resistance noise, amplifier voltage noise (ven), and the voltage noise from the amplifier current noise (ien RS) are all subject to the noise gain term ( + RF/RG). Note that with a. nv/ Hz input voltage noise and.4 pa/ Hz input current, the noise contributions of the amplifier are relatively small for source resistances between approximately Ω and kω. Figure 4 shows the total RTI noise due to the amplifier vs. the source resistance. In addition, the value of the feedback resistors used impacts the noise. It is recommended to keep the value of feedback resistors between 5 Ω and kω to keep the total noise low. NOISE (nv/ Hz) AMPLIFIER + RESISTOR NOISE SOURCE RESISTANCE NOISE TOTAL AMPLIFIER NOISE. k k k SOURCE RESISTANCE (Ω) The input stage positive limit is almost exactly a volt below the positive supply at room temperature. Input voltages above that start to show clipping behavior. The positive input voltage limit increases with temperature with a coefficient of about mv/ C. The lower supply limit is nominally below the minus supply; therefore, in a standard gain configuration, the output stage limits the signal headroom on the negative supply side. Figure 4 and Figure 4 show the nominal CMRR behavior at the limits of the input headroom for three temperatures this is generated using the subtractor topology shown in Figure 44, which avoids the output stage limitation C 6 +5 C 4 C COMMON-MODE VOLTAGE (V) Figure 4. +CMV vs. Common-Mode Error vs. VOS COMMON-MODE ERROR (μv) COMMON-MODE ERROR (μv) C 5 +5 C C COMMON-MODE VOLTAGE (V) Figure 4. CMV vs. Common-Mode Error vs. VOS V CM + + V OUT Figure 4. RTI Noise vs. Source Resistance HEADROOM CONSIDERATIONS The ADA484-/ADA484- are designed to provide maximum input and output signal ranges with 6-bit to 8-bit dc linearity. As the input or output headroom limits are reached, the signal linearity degrades. Rev. C Page 4 of Figure 44. Common-Range Subtractor 564-5

15 ADA484-/ADA484- Figure 45 shows the amplifier frequency response as a G = inverter with the input and output stage biased near the negative supply rail. 6 5 G = + GAIN (db) 6 V S+ = 5V G = V S = 5mV V IN = mv p-p V S = mv V S = mv V S = 5mV 6 9 V S = mv. Figure 45. Small Signal Frequency Response vs. Negative Supply Bias The input voltage (VIN) and reference voltage (VIP) are both at V, (see Figure 9). +VS is biased at +5 V, and VS is swept from mv to mv. With the input and output voltages biased mv above the bottom rail, the G = inverter frequency response is not much different from what is seen with the input and output voltages biased near midsupply. At 5 mv bias, the frequency response starts to decrease and at mv, the inverter bandwidth is less than half its nominal value. CAPACITANCE DRIVE Capacitance at the output of an amplifier creates a delay within the feedback path that, if within the bandwidth of the loop, can create excessive ringing and oscillation. The G = + follower topology has the highest loop bandwidth of any typical configuration and, therefore, is the most vulnerable to the effects of capacitance load. A small resistor in series with the amplifier output and the capacitive load mitigates the problem. Figure 46 plots the recommended series resistance vs. capacitance for gains of +, +, and SERIES RESISTANCE (Ω) 4 G = + G = +5 CAPACITANCE LOAD (pf) Figure 46. Series Resistance vs. Capacitance Load INPUT PROTECTION The ADA484-/ADA484- are fully protected from ESD events, withstanding human body model ESD events of.5 kev and charge device model events of kev with no measured performance degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair, as shown in Figure 47. VCC BIAS ESD ESD VP ESD VEE TO REST OF AMPLIFIER ESD VN Figure 47. Input Stage and Protection Diodes For differential voltages above approximately.4 V, the diode clamps start to conduct. Too much current can cause damage due to excessive heating. If large differential voltages need to be sustained across the input terminals, it is recommended that the current through the input clamps be limited to below 5 ma. Series input resistors sized appropriately for the expected differential overvoltage provide the needed protection. The ESD clamps start to conduct for input voltages more than.7 V above the positive supply and input voltages more than.7 V below the negative supply. It is recommended that the fault current be limited to less than 5 ma if an overvoltage condition is expected Rev. C Page 5 of

16 ADA484-/ADA484- POWER-DOWN OPERATION Figure 48 shows the ADA484- power-down circuitry. If the POWER DOWN pin is left unconnected, then the base of the input PNP transistor is pulled high through the internal pull-up resistor to the positive supply, and the part is turned on. Pulling the POWER DOWN pin approximately.7 V below the positive supply turns the part off, reducing the supply current to approximately 4 μa. VCC I BIAS ESD TO AMPLIFIER BIAS ESD POWER DOWN VEE Figure 48. POWER DOWN Circuit The POWER DOWN pin is protected with ESD clamps, as shown in Figure 48. Voltages beyond the power supplies cause these diodes to conduct. The guidelines for limiting the overload current in the input protection section should also be followed for the POWER DOWN pin. Rev. C Page 6 of

17 ADA484-/ADA484- APPLICATIONS TYPICAL PERFORMANCE VALUES To reduce design time and eliminate uncertainty Table 6 provides a convenient reference for typical gains, component values, and performance parameters. 6-BIT ADC DRIVER The combination of low noise, low power, and high speed make the ADA484-/ADA484- the perfect driver solution for low power, 6-bit ADCs, such as the AD7685. Figure 49 shows a typical 6-bit single-supply application. There are different challenges to a single-supply, high resolution design, and the ADA484-/ADA484- address these nicely. In a single-supply system, a main challenge is using the amplifier in buffer mode with the lowest output noise and preserving linearity compatible with the ADC. RECONSTRUCTION FILTER The ADA484-/ADA484- can also be used as a reconstruction filter at the output of DACs for suppression of the sampling frequency. The filter shown in Figure 5 is a two-pole, 5 khz Sallen-Key LPF with a fixed gain of G = +.6. INPUT R 49Ω R 49Ω C pf U C pf +5V μf.μf.μf μf OUTPUT Rail-to-rail input amplifiers are usually higher noise than the ADA484-/ADA484- and cannot be used in this mode because of the nonlinear region around the crossover point of their input stages. The ADA484-/ADA484-, which have no crossover region but have a wide linear input range from mv below ground to V below positive rail, solve this problem, as shown in Figure 49. The amplifier, when configured as a follower, has a linear signal range from.5 V above the minus supply voltage (limited by the amplifier s output stage) to V below the positive supply (limited by the amplifier input stage). A V to V signal range can be accommodated with a positive supply as low as +5. V and a negative power supply of.5 V. The 5. V supply also allows the use of a small, low dropout, low temperature drift ADR64 reference voltage. If ground is used as the amplifier negative supply, then note that at the low end of the input range close to ground, the ADA484-/ ADA484- exhibit substantial nonlinearity, as any rail-to-rail output amplifier. The ADA484-/ADA484- drive a onepole, low-pass filter. This filter limits the already very low noise contribution from the amplifier to the AD7685. R 84Ω 5V R4 499Ω Figure 5. Two-Pole 5 khz Reconstruction Filter Schematic Setting the resistors and capacitors equal to each other greatly simplifies the design equations for the Sallen-Key filter. The corner frequency, or db frequency, can be described by the equation f C = πrc The quality factor, or Q, is shown in the equation Q = K For minimum peaking, set Q equal to.77. The gain, or K, of the amplifier is R4 K = + R V nf ADR64 μf nf Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. ADA484 nf V TO 4.96V Ω IN+ REF VDD VIO SDI.5V.7nF IN AD7685 GND SCK SDO CNV Figure 49. ADC Driver Schematic Rev. C Page 7 of

18 ADA484-/ADA484- Table 6. Recommended Values and Typical Performance Gain RF (Ω) RG (Ω) db BW (MHz) Slew Rate (V/μs) Peaking (db) Output Noise ADA484-/ ADA484- Only (nv/ Hz) + N/A Total Output Noise Including Resistors (nv/ Hz) Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors, are good choices for filter elements. Figure 5 shows the filter response. GAIN (db) Figure 5. Filter Frequency Response LAYOUT CONSIDERATIONS To ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. GROUND PLANE It is important to avoid ground in the areas under and around the input and output of the ADA484-/ADA484-. Stray capacitance created between the ground plane and the input and output pads of a device are detrimental to high speed amplifier performance. Stray capacitance at the inverting input, along with the amplifier input capacitance, lowers the phase margin and can cause instability. Stray capacitance at the output creates a pole in the feedback loop. This can reduce phase margin and can cause the circuit to become unstable POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect in the performance of the ADA484-/ADA484-. A parallel connection of capacitors from each of the power supply pins to ground works best. A typical connection is shown in Figure 5. Smaller value capacitors offer better high frequency response where larger value electrolytics offer better low frequency performance. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. This can be especially important when the amplifier PSR is starting to roll off the bypass capacitors can help lessen the degradation in PSR performance. Starting directly at the ADA484-/ADA484- power supply pins, the smallest value capacitor should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier power supply pin. The ground end of the capacitor should be connected directly to the ground plane. Keeping the capacitors distance short but equal from the load is important and can improve distortion performance. This process should be repeated for the next largest value capacitor. It is recommended that a. μf ceramic 58 case be used. The 58 case size offers low series inductance and excellent high frequency performance. A μf electrolytic capacitor should be placed in parallel with the. μf capacitor. Depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. Each circuit is different and should be individually analyzed for optimal performance. Rev. C Page 8 of

19 ADA484-/ADA484- OUTLINE DIMENSIONS.9 BSC 4. (.574).8 (.497).5 (.98). (.4) COPLANARITY. 5. (.968) 4.8 (.89) 8 5 SEATING PLANE 4.7 (.5) BSC 6. (.44) 5.8 (.84).75 (.688).5 (.5).5 (.). (.).5 (.98).7 (.67) 8.5 (.96).5 (.99) 45.7 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 5. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) BSC.8 BSC PIN INDICATOR MAX.9 BSC BSC.45 MAX SEATING PLANE..8 4 COMPLIANT TO JEDEC STANDARDS MO-78-AB Figure Lead Small Outline Transistor Package [SOT-] (RJ-6) Dimensions shown in millimeters PIN BSC COPLANARITY MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87-AA Figure 5. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C Page 9 of

20 ADA484-/ADA484- ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity Branding ADA484-YRZ 4 C to +5 C 8-Lead SOIC_N R-8 ADA484-YRZ-R7 4 C to +5 C 8-Lead SOIC_N R-8, ADA484-YRZ-RL 4 C to +5 C 8-Lead SOIC_N R-8,5 ADA484-YRJZ-R 4 C to +5 C 6-Lead SOT- RJ-6 5 HQB ADA484-YRJZ-R7 4 C to +5 C 6-Lead SOT- RJ-6, HQB ADA484-YRJZ-RL 4 C to +5 C 6-Lead SOT- RJ-6, HQB ADA484-YRMZ 4 C to +5 C 8-Lead MSOP RM-8 HRB ADA484-YRMZ-R7 4 C to +5 C 8-Lead MSOP RM-8, HRB ADA484-YRMZ-RL 4 C to +5 C 8-Lead MSOP RM-8, HRB ADA484-YRZ 4 C to +5 C 8-Lead SOIC_N R-8 ADA484-YRZ-R7 4 C to +5 C 8-Lead SOIC_N R-8, ADA484-YRZ-RL 4 C to +5 C 8-Lead SOIC_N R-8,5 Z = Pb-free part. 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D564 /6(C) Rev. C Page of