FEATURES High speed 190 MHz, 3 db bandwidth (G = +1) 100 V/μs slew rate Low distortion MHz SFDR 80 5 MHz SFDR Selectable input cross

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1 FEATURES High speed 9 MHz, 3 db bandwidth (G = ) V/μs slew rate Low distortion MHz SFDR 8 5 MHz SFDR Selectable input crossover threshold Low noise 4.3 nv/ Hz.6 pa/ Hz Low offset voltage: 9 μv max Low power: 6.5 ma/amplifier supply current Power-down mode No phase reversal: VIN > VS mv Wide supply range:.7 V to V Small packaging: SOIC-8, SOT-3-6, MSOP- APPLICATIONS Filters ADC drivers Level shifting Buffering Professional video Low voltage instrumentation GENERAL DESCRIPTION The are high speed amplifiers with rail-torail input and output that operate on low supply voltages and are optimized for high performance and wide dynamic signal range. The have low noise (4.3 nv/ Hz,.6 pa/ Hz) and low distortion ( dbc at MHz). In applications that use a fraction of, or the entire input dynamic range and require low distortion, the are ideal choices. Many rail-to-rail input amplifiers have an input stage that switches from one differential pair to another as the input signal crosses a threshold voltage, which causes distortion. The have a unique feature that allows the user to select the input crossover threshold voltage through the SELECT pin. This feature controls the voltage at which the complementary transistor input pairs switch. The AD87/ AD88 also have intrinsically low crossover distortion. Low Distortion, High Speed Rail-to-Rail Input/Output Amplifiers CONNECTION DIAGRAMS AD87 SOIC-8 (R) NC 8 DISABLE/SELECT V OUT IN 7 V S IN 3 6 V OUT V S V S 4 5 NC NC = NO CONNECT IN 3 AD88 SOIC-8 (R) V OUTA 8 V S V OUTA IN A 7 V OUTB IN A IN A 3 6 IN B IN A 3 V S 4 5 IN B V S 4 DISABLE/SELECT A 5 AD87 SOT-3-6 (RT) AD88 MSOP- (RM) 6 V S B- DISABLE/SELECT 4 IN Figure. Connection Diagrams (Top View) V S 9 V OUTB 8 IN B 7 IN B 6 DISABLE/SELECT B With their wide supply voltage range (.7 V to V) and wide bandwidth (9 MHz), the amplifiers are designed to work in a variety of applications where speed and performance are needed on low supply voltages. The high performance of the is achieved with a quiescent current of only 6.5 ma/amplifier typical. The have a shutdown mode that is controlled via the SELECT pin. The are available in SOIC-8, MSOP-, and SOT-3-6 packages. They are rated to work over the industrial temperature range of 4 C to 5 C. SFDR (db) G = FREQUENCY = khz R L = kω V S = 3V V S = 5V V S = ±5V OUTPUT VOLTAGE (V p-p) Figure. SFDR vs. Output Amplitude Protected by U.S. patent numbers 6,486,737B; 6,58,84B 337-A-63 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Fax: Analog Devices, Inc. All rights reserved.

2 TABLE OF CONTENTS Specifications... 3 Absolute Maximum Ratings... 6 Maximum Power Dissipation... 6 ESD Caution... 6 Typical Performance Characteristics... 8 Theory of Operation... 7 Input Stage... 7 Crossover Selection... 7 Output Stage... 8 Wideband Operation... 9 Circuit Considerations... 9 Applications... Using the SELECT Pin... Driving a 6-Bit ADC... Band-Pass Filter... Design Tools and Technical Support... Outline Dimensions... 3 Ordering Guide... 4 DC Errors... 8 REVISION HISTORY 3/5 Rev. B to Rev. C Updated Format...Universal Change to Figure... /3 Rev. A to Rev. B Changes to Figure... 8/3 Rev. to Rev. A Addition of AD88... Universal Changes to GENERAL DESCRIPTION... Changes to Figures, 3, 4, 8, 3, 5, 7..., 6, 7, 8, 9 Changes to Figures 58, , Changes to SPECIFICATIONS...3 Updated OUTLINE DIMENSIONS... Updated ORDERING GUIDE...3 3/3 Revision : Initial Version Rev. C Page of 4

3 SPECIFICATIONS VS = ±5 V at TA = 5 C, RL = kω to midsupply, G =, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth G =, V O =. V p-p 38 9 MHz G =, V O = V p-p 3 MHz Bandwidth for. db Flatness G =, V O =. V p-p 6 MHz Slew Rate G =, V O = V step/g =, V O = V step 9/ V/μs Settling Time to.% G =, V O = V step 35 ns NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) f C = MHz, V O = V p-p, RF = 4.9 Ω dbc f C = 5 MHz, V O = V p-p, RF = 4.9 Ω 8 dbc Input Voltage Noise f = khz 4.3 nv/ Hz Input Current Noise f = khz.6 pa/ Hz Differential Gain Error NTSC, G =, RL = 5 Ω. % Differential Phase Error NTSC, G =, RL = 5 Ω. Degrees Crosstalk, Output to Output G =, RL = Ω, VOUT = V p-p, 93 db VS = ±5 MHz DC PERFORMANCE Input Offset Voltage SELECT = three-state or open, PNP active 8 μv SELECT = high NPN active 4 9 μv Input Offset Voltage Drift TMIN to TMAX.5 μv/ C Input Bias Current VCM = V, NPN active 4 6 μa TMIN to TMAX 4 μa VCM = V, PNP active 8 μa TMIN to TMAX 8 μa Input Offset Current ±. ±.9 μa Open-Loop Gain V O = ±.5 V db INPUT CHARACTERISTICS Input Impedance 6 MΩ Input Capacitance pf Input Common-Mode Voltage Range 5. to 5. V Common-Mode Rejection Ratio VCM = ±.5 V 9 db SELECT PIN Crossover Low, Selection Input Voltage Three-state < ± μa 3.3 to 5 V Crossover High, Selection Input Voltage 3.9 to 3.3 V Disable Input Voltage 5 to 3.9 V Disable Switching Speed 5% of input to <% of final V O 98 ns Enable Switching Speed 45 ns OUTPUT CHARACTERISTICS Output Overdrive Recovery Time (Rising/Falling Edge) V I = 6 V to 6 V, G = 4/45 ns Output Voltage Swing VS. VS.6, VS.6 VS. V Short-Circuit Output Sinking and Sourcing ma Off Isolation V IN =. V p-p, f = MHz, SELECT = low 49 db Capacitive Load Drive 3% overshoot pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier ma Quiescent Current (Disabled) SELECT = low 37 5 μa Power Supply Rejection Ratio VS ± V 9 db No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin. Rev. C Page 3 of 4

4 VS = 5 V at TA = 5 C, RL = kω to midsupply, unless otherwise noted. Table. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth G =, V O =. V p-p 3 85 MHz G =, V O = V p-p 8 8 MHz Bandwidth for. db Flatness G =, V O =. V p-p MHz Slew Rate G =, V O = V step/g =, V O = V step 85/ V/μs Settling Time to.% G =, V O = V step 4 ns NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) f C = MHz, V O = V p-p, RF = 4.9 Ω 9 dbc f C = 5 MHz, V O = V p-p, RF = 4.9 Ω 64 dbc Input Voltage Noise f = khz 4.3 nv/ Hz Input Current Noise f = khz.6 pa/ Hz Differential Gain Error NTSC, G =, RL = 5 Ω. % Differential Phase Error NTSC, G =, RL = 5 Ω. Degrees Crosstalk, Output to Output G =, RL = Ω, VOUT = V p-p, 9 db VS = ±5 MHz DC PERFORMANCE Input Offset Voltage SELECT = three-state or open, PNP active 8 μv SELECT = high NPN active 4 9 μv Input Offset Voltage Drift TMIN to TMAX μv/ C Input Bias Current VCM =.5 V, NPN active 4 6 μa TMIN to TMAX 4 μa VCM =.5 V, PNP active 8 μa TMIN to TMAX 8 μa Input Offset Current ±. ±.9 μa Open-Loop Gain V O = V to 4 V 96 5 db INPUT CHARACTERISTICS Input Impedance 6 MΩ Input Capacitance pf Input Common-Mode Voltage Range. to 5. V Common-Mode Rejection Ratio VCM = V to.5 V 9 5 db SELECT PIN Crossover Low, Selection Input Voltage Three-state < ± μa.7 to 5 V Crossover High, Selection Input Voltage. to.7 V Disable Input Voltage to. V Disable Switching Speed 5% of input to <% of final V O ns Enable Switching Speed 5 ns OUTPUT CHARACTERISTICS Overdrive Recovery Time V I = V to 6 V, G = 5/5 ns (Rising/Falling Edge) Output Voltage Swing R L = kω VS.8 VS.4, VS.8 V VS.4 Off Isolation VIN =. V p-p, f = MHz, SELECT = low 49 db Short-Circuit Current Sinking and sourcing 5 ma Capacitive Load Drive 3% overshoot pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier ma Quiescent Current (Disabled) SELECT = low 3 45 μa Power Supply Rejection Ratio VS ± V 9 5 db No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin. Rev. C Page 4 of 4

5 VS = 3 V at TA = 5 C, RL = kω to midsupply, unless otherwise noted. Table 3. Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE 3 db Bandwidth G =, V O =. V p-p 5 8 MHz G =, V O = V p-p 9 9 MHz Bandwidth for. db Flatness G =, V O =. V p-p MHz Slew Rate G =, V O = V step/g =, V O = V step 73/ V/μs Settling Time to.% G =, V O = V step 48 ns NOISE/DISTORTION PERFORMANCE Spurious-Free Dynamic Range (SFDR) f C = MHz, V O = V p-p, RF = 4.9 Ω 85 dbc f C = 5 MHz, V O = V p-p, RF = 4.9 Ω 64 dbc Input Voltage Noise f = khz 4.3 nv/ Hz Input Current Noise f = khz.6 pa/ Hz Differential Gain Error NTSC, G =, RL = 5 Ω.5 % Differential Phase Error NTSC, G =, RL = 5 Ω. Degrees Crosstalk, Output to Output G =, RL = Ω, VOUT = V p-p, 89 db VS = 3 MHz DC PERFORMANCE Input Offset Voltage SELECT = three-state or open, PNP active 8 μv SELECT = high NPN active 4 9 μv Input Offset Voltage Drift TMIN to TMAX μv/ C Input Bias Current VCM =.5 V, NPN active 4 6 μa TMIN to TMAX 4 μa VCM =.5 V, PNP active 8 μa TMIN to TMAX 8 μa Input Offset Current ±. ±.9 μa Open-Loop Gain V O = V to V 9 db INPUT CHARACTERISTICS Input Impedance 6 MΩ Input Capacitance pf Input Common-Mode Voltage Range R L = kω. to 3. V Common-Mode Rejection Ratio VCM = V to.5 V 88 db SELECT PIN Crossover Low, Selection Input Voltage Three-state < ± μa.7 to 3 V Crossover High, Selection Input Voltage. to.7 V Disable Input Voltage to. V Disable Switching Speed 5% of input to <% of final V O 5 ns Enable Switching Speed 5 ns OUTPUT CHARACTERISTICS Output Overdrive Recovery Time V I = V to 4 V, G = 55/55 ns (Rising/Falling Edge) Output Voltage Swing R L = kω VS.7 VS.3, VS.7 V VS.3 Short-Circuit Current Sinking and sourcing 7 ma Off Isolation VIN =. V p-p, f = MHz, SELECT = low 49 db Capacitive Load Drive 3% Overshoot pf POWER SUPPLY Operating Range.7 V Quiescent Current/Amplifier ma Quiescent Current (Disabled) SELECT = low 3 4 μa Power Supply Rejection Ratio VS ± V 88 db No sign or a plus sign indicates current into the pin; a minus sign indicates current out of the pin. Rev. C Page 5 of 4

6 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating Supply Voltage.6 V Power Dissipation See Figure 3 Common-Mode Input Voltage ±VS ±.5 V Differential Input Voltage ±.8 V Storage Temperature 65 C to 5 C Operating Temperature Range 4 C to 5 C Lead Temperature Range 3 C (Soldering sec) Junction Temperature 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ( P θ ) T J = TA D JA The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, then the total drive power is VS/ IOUT, some of which is dissipated in the package and some in the load (VOUT IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power (Total Drive Power Load Power) P D = ( V I ) S S V V S OUT R L V R OUT RMS output voltages should be considered. If RL is referenced to VS, as in single-supply operation, then the total drive power is VS IOUT. If the rms signal levels are indeterminate, then consider the MAXIMUM POWER DISSIPATION worst case, when VOUT = VS/4 for RL to midsupply. The maximum safe power dissipation in the package is limited by the associated rise in junction temperature ( ) ( VS /4) P (TJ) on the die. The plastic encapsulating the die locally reaches D = VS IS RL the junction temperature. At approximately 5 C, which is the glass transition temperature, the plastic changes its properties. In single-supply operation with RL referenced to VS, worst case Even temporarily exceeding this temperature limit may change is VOUT = VS/. the stresses that the package exerts on the die, permanently shifting the parametric performance of the. Airflow increases heat dissipation, effectively reducing θja. Also, Exceeding a junction temperature of 75 C for an extended more metal directly in contact with the package leads from period of time can result in changes in the silicon devices, metal traces, through holes, ground, and power planes reduces potentially causing failure. the θja. Care must be taken to minimize parasitic capacitances at the input leads of high speed op amps, as discussed in the The still-air thermal properties of the package and PCB (θja), PCB Layout section. ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature can be calculated as L ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C Page 6 of 4

7 Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC-8 (5 C/W), SOT-3-6 (7 C/W), and MSOP- (3 C/W) packages on a JEDEC standard 4-layer board. Output Short Circuit Shorting the output to ground or drawing excessive current from the can likely cause catastrophic failure. MAXIMUM POWER DISSIPATION (W) MSOP- SOT-3-6 SOIC AMBIENT TEMPERATURE ( C) 337-A- Figure 3. Maximum Power Dissipation vs. Ambient Temperature Rev. C Page 7 of 4

8 TYPICAL PERFORMANCE CHARACTERISTICS Default conditions: VS = 5 V at TA = 5 C, RL = kω, unless otherwise noted. NORMALIZED CLOSED-LOOP GAIN (db) V OUT = mv p-p G =. G = AD87 G = G = AD88 G = 337-A-3 Figure 4. Small Signal Frequency Response for Various Gains CLOSED-LOOP GAIN (db) G = V OUT = mv p-p V S = 3V V S = 5V V S = ±5V A-6 Figure 7. Small Signal Frequency Response for Various Supplies CLOSED- LOOP GAIN (db) G = V OUT = mv p-p V S = 3V R F = 4.9Ω V S = ±5V V S = 5V V S = 3V. 337-A-4 CLOSED-LOOP GAIN (db) G = V OUT = mv p-p V S = 5V V S = 3V 9 V S = ±5V. 337-A-7 Figure 5. AD87 Small Signal Frequency Response for Various Supplies Figure 8. AD88 Small Signal Frequency Response for Various Supplies CLOSED-LOOP GAIN (db) G = V OUT = V p-p V S = 3V V S = 5V V S = ±5V. 337-A-5 Figure 6. Large Signal Frequency Response for Various Supplies CLOSED-LOOP GAIN (db) G = V OUT = V p-p V S = 5V V S = 3V V S = ±5V A-8 Figure 9. Large Signal Frequency Response for Various Supplies Rev. C Page 8 of 4

9 CLOSED-LOOP GAIN (db) G = V OUT = mv p-p 8. C L = pf C L = pf C L = 5pF 337-A-9 CLOSED-LOOP GAIN (db) 3 G = V OUT = mv p-p C L = pf C L = 5pF 3 C L = pf A- Figure. AD87 Small Signal Frequency Response for Various CLOAD Figure 3. AD88 Small Signal Frequency Response for Various CLOAD CLOSED-LOOP GAIN (db) G = V OUT = mv p-p CLOSED-LOOP GAIN (db) 3 3 V OUT = V p-p V OUT =.V p-p R L = 5Ω 3 V OUT = 4V p-p 3 V OUT =.V p-p R L = kω A A G = V OUT =.V p-p R L = 5Ω V OUT =.V p-p R L = kω Figure. Frequency Response for Various Output Amplitudes Figure 4. Small Signal Frequency Response for Various RLOAD Values CLOSED-LOOP GAIN (db) C 5 C 5 C CLOSED-LOOP GAIN (db) C 5 C 7 G = V OUT = mv p-p A- 7 G = V OUT = mv p-p 5 C A-4 Figure. AD87 Small Signal Frequency Response vs. Temperature Figure 5. AD88 Small Signal Frequency Response vs. Temperature Rev. C Page 9 of 4

10 CLOSED-LOOP GAI (db) G = V OUT = mv p-p V ICM = V S.3V SELECT = TRI V ICM = V S.V SELECT = HIGH V ICM = V S.V SELECT = TRI V ICM = V SELECT = HIGH OR TRI 8. V ICM = V S.3V SELECT = HIGH Figure 6. Small Signal Frequency Response vs. Input Common-Mode Voltages 337-A-5 VOLTAGE NOISE (nv/ Hz) VOLTAGE CURRENT k k k M M M G FREQUENCY (Hz) 337-A-8 Figure 9. Voltage and Current Noise vs. Frequency CURRENT NOISE (pa/ Hz) CROSSTALK (db) R 5Ω V VI R 5Ω U / AD88 CROSSTALK = log (V OUT /V IN ) B TO A R3 kω 4... A TO B U / AD88 Figure 7. AD88 Crosstalk Output to Output V OUT V OUT = V p-p 6. G = V S = 5V R L = kω 337-A-6 CLOSED-LOOP GAIN (db) G = R L = 5Ω V OUT = mv p-p 5.9. Figure.. db Flatness Frequency Response 337-A-9 OPEN-LOOP GAIN (db) GAIN 5 95 PHASE k k k M M M G 5 FREQUENCY (Hz) 337-A-7 Figure 8. Open-Loop Gain and Phase vs. Frequency PHASE (Degrees) DISTORTION (db) G = V OUT = V p-p R L = kω SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE V S = 5V V S = 3V V S = ±5V A- Figure. Harmonic Distortion vs. Frequency and Supply Voltage Rev. C Page of 4

11 DISTORTION (db) G = (R F = 4.9Ω) FREQUENCY = khz R L = kω V S = 3V V S = 5V V S = ±5V SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE OUTPUT VOLTAGE (V p-p) Figure. Harmonic Distortion vs. Output Amplitude 337-A- DISTORTION (db) G = (R F = 4.9Ω) V OUT =.V MHz SELECT = HIGH SELECT = TRI 5 SELECT = TRI SELECT = HIGH 5 SECOND HARMONIC: SOLID LINE THIRD HARMONIC: DASHED LINE INPUT COMMON-MODE VOLTAGE (V) 337-A-4 Figure 5. Harmonic Distortion vs. Input Common-Mode Voltage, VS = 5 V DISTORTION (db) G = (R F = 4.9Ω) V OUT =.V khz R L = kω V S = 3V V S = 5V DISTORTION (db) G = (R F = 4.9Ω) V OUT =.V khz V S = 3V V S = 5V 3 SECOND HARMONIC: SOLID LINE 4 THIRD HARMONIC: DASHED LINE INPUT COMMON-MODE VOLTAGE (V) 337-A- Figure 3. Harmonic Distortion vs. Input Common-Mode Voltage, SELECT = High 3 SECOND HARMONIC: SOLID LINE 4 THIRD HARMONIC: DASHED LINE INPUT COMMON-MODE VOLTAGE (V) 337-A-5 Figure 6. Harmonic Distortion vs. Input Common-Mode Voltage, SELECT = Three-State or Open G = (RF = 4.9Ω) V OUT =.V p-p SECOND HARMONIC: SOLID LINE 4 THIRD HARMONIC: DASHED LINE R L = kω VS = 5 V OUT =.V p-p SECOND HARMONIC: SOLID LINE 4 THIRD HARMONIC: DASHED LINE G = DISTORTION (db) 6 8 R L = 5Ω DISTORTION (db) 6 8 G = G = 4. Figure 4. Harmonic Distortion vs. Frequency and Load 337-A A-6 Figure 7. Harmonic Distortion vs. Frequency and Gain Rev. C Page of 4

12 ..5. G = V S = ±.5V..5. G = V S = ±.5V C L = pf C L = 5pF mV/DIV ns/div.5 5mV/DIV ns/div. 337-A A-3 Figure 8. Small Signal Transient Response Figure 3. Small Signal Transient Response with Capacitive Load.... G = V S = ±.5V V OUT = 4V p-p V OUT = V p-p mV/DIV ns/div 3.5 5mV/DIV 5ns/DIV 337-A A-3 Figure 9. Large Signal Transient Response, G = G = R L = kω V S = ±.5V Figure 3. Output Overdrive Recovery G = V S = ±.5V 5mV/DIV V OUT = 4V p-p V OUT = V p-p ns/div Figure 3. Large Signal Transient Response, G = 337-A G = R L = kω V S = ±.5V 5mV/DIV Figure 33. Input Overdrive Recovery 5ns/DIV 337-A-3 Rev. C Page of 4

13 G = V IN (mv/div) V OUT V IN (mv/div).%.% INPUT BIAS CURRENT (μa) V S = 3V SELECT = HIGH V S = 5V SELECT = TRI V S = ±5V Figure 34. Long-Term Settling Time 5μs/DIV 337-A INPUT COMMON-MODE VOLTAGE (V) 337-A-36 Figure 37. Input Bias Current vs. Input Common-Mode Voltage V IN (mv/div) 5 COUNT = 78 SELECT MEAN STD. DEV HIGH 49μV 93μV TRI 55μV 5μV SELECT = TRI V OUT (4mV/DIV).% FREQUENCY 5 SELECT = HIGH.% V OUT V IN (.%/DIV) 5 ns/div Figure 35..% Short-Term Settling Time 337-A INPUT OFFSET VOLTAGE (μv) 337-A-37 Figure 38. Input Offset Voltage Distribution INPUT BIAS CURRENT (SELECT = HIGH) (μa) SELECT = HIGH 3.5 V S = ±5V V S = 3V V S = 5V 3. SELECT = TRI TEMPERATURE ( C) Figure 36. Input Bias Current vs. Temperature 337-A INPUT BIAS CURRENT (SELECT = TRI) (μa) INPUT OFFSET VOLTAGE (μv) SELECT = TRI 4 V S = ±5V V S = 3V SELECT = HIGH 8 V S = 5V TEMPERATURE ( C) Figure 39. Input Offset Voltage vs. Temperature 337-A-38 Rev. C Page 3 of 4

14 9 V S = ±5V 7 INPUT OFFSET VOLTAGE (μv) SELECT = HIGH SELECT = TRI CMRR (db) INPUT COMMON-MODE VOLTAGE (V) 337-A-39 Figure 4. Input Offset Voltage vs. Input Common-Mode Voltage, VS = ±5 k k k M M M FREQUENCY (Hz) Figure 43. CMRR vs. Frequency 337-A V S = 5V INPUT OFFSET VOLTAGE (μv) SELECT = HIGH 4 PSRR 5 PSRR 6 SELECT = TRI PSSR (db) INPUT COMMON-MODE VOLTAGE (V) 337-A-4 Figure 4. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 5 k k k M M M G FREQUENCY (Hz) Figure 44. PSRR vs. Frequency 337-A V S = 3V VIN =.V p-p G = 3 SELECT = LOW INPUT OFFSET VOLTAGE (μv) SELECT = HIGH SELECT = TRI OFF ISOLATION (db) INPUT COMMON-MODE VOLTAGE (V) 337-A-4 Figure 4. Input Offset Voltage vs. Input Common-Mode Voltage, VS = 3 k k M M M G FREQUENCY (Hz) Figure 45. Off Isolation vs. Frequency 337-A-44 Rev. C Page 4 of 4

15 OUTPUT SATURATION VOLTAGE (mv) V S = 3V V S = 5V V S = ±5V LOAD RESISTANCE TIED TO MIDSUPPLY V OL V S V OH V S OPEN-LOOP GAIN (db) V ±5V 5V LOAD RESISTANCE (Ω) Figure 46. Output Saturation Voltage vs. Output Load 337-A I LOAD (ma) Figure 49. Open-Loop Gain vs. Load Current 337-A-48 M SELECT = LOW k OUTPUT IMPEDANCE (Ω) G = 5 OUTPUT IMPEDANCE (Ω) k. k G = G =.. k k k M M M G FREQUENCY (Hz) 337-A-46 Figure 47. Output Enabled Impedance vs. Frequency k M M M G FREQUENCY (Hz) Figure 5. Output Disabled Impedance vs. Frequency 337-A-49 OUTPUT SATURATION VOLTAGE (mv) V S = 5V R L = kω TIED TO MIDSUPPLY V OL V S V S V OH SELECT CURRENT (μa) V S = 5V V S = 5 C 5 C 5 C 4 C TEMPERATURE ( C) Figure 48. Output Saturation Voltage vs. Temperature 337-A SELECT VOLTAGE (V) Figure 5. SELECT Pin Current vs. SELECT Pin Voltage and Temperature 337-A-5 Rev. C Page 5 of 4

16 OUTPUT VOLTAGE (V) R L = Ω R L = kω R L = kω. G = V S = ±.5V V IN =.V TIME (ns) SELECT PIN (.V TO.5V) OUTPUT Figure 5. Enable Turn-On Timing 337-A-5 SUPPLY CURRENT (ma) V S = ±5V V S = 3V TEMPERATURE ( C) V S = 5V 337-A-53 Figure 54. Quiescent Supply Current vs. Supply Voltage and Temperature.5. OUTPUT SELECT PIN (.V TO.5V) OUTPUT VOLTAGE (V).5.5. R L = Ω R L = kω R L = kω G = V S = ±.5V V IN =.V TIME (μs) 337-A-5 Figure 53. Disable Turn-Off Timing Rev. C Page 6 of 4

17 THEORY OF OPERATION The are rail-to-rail input/output amplifiers designed in the Analog Devices XFCB process. The XFCB process enables the to run on.7 V to V supplies with 9 MHz of bandwidth and over V/μs of slew rate. The have 4.3 nv/ Hz of wideband noise with 7 nv/ Hz noise at Hz. This noise performance, with an offset and drift performance of less than 9 μv maximum and.5 μv/ C typical, respectively, makes the ideal for high speed, precision applications. Additionally, the input stage operates mv beyond the supply rails and shows no phase reversal. The amplifiers feature overvoltage protection on the input stage. Once the inputs exceed the supply rails by.7 V, ESD protection diodes are turned on, drawing excessive current through the differential input pins. A series input resistor should be included to limit the input current to less than ma. The NPN input pair can now operate at mv above the positive rail. Both input pairs are protected from differential input signals above.4 V by four diodes across the input (see Figure 55). In the event of differential input signals that exceed.4 V, the diodes conduct and excessive current flows through them. A series input resistor should be included to limit the input current to ma. CROSSOVER SELECTION The have a feature called crossover selection, which allows the user to choose the crossover point between the PNP/NPN differential pairs. Although the crossover region is small, operating in this region should be avoided, because it can introduce offset and distortion to the output signal. To help avoid operating in the crossover region, the allow the user to select from two preset crossover locations (voltage levels) using the SELECT pin. As shown in Figure 55, INPUT STAGE the crossover region is about mv and is defined by the The rail-to-rail input performance is achieved by operating voltage level at the base of Q5. Internally, two separate voltage complementary input pairs. Which pair is on is determined by sources are created approximately. V from either rail. One or the common-mode level of the differential input signal. As the other is connected to Q5, based on the voltage applied to the shown in Figure 55, a tail current (ITAIL) is generated that SELECT pin. This allows either dominant PNP pair operation, sources the PNP differential input structure consisting of Q when the SELECT pin is left open, or dominant NPN pair and Q. A reference voltage is generated internally that is operation, when the SELECT pin is pulled high. connected to the base of Q5. This voltage is continually compared against the common-mode input voltage. When the The SELECT pin also provides the traditional power-down common-mode level exceeds the internal reference voltage, function when it is pulled low. This allows the designer to Q5 diverts the tail current (ITAIL) from the PNP input pair to a achieve the best precision and ac performance for high-side and current mirror that sources the NPN input pair consisting of low-side signal applications. See Figure 5 through Figure 53 for Q3 and Q4. SELECT pin characteristics. VCC.V I TAIL VOUTP VSEL LOGIC Q5 Q3 Q Q Q4 VP VN I CMFB VEE VOUTN VCC I CMFB VEE.V 337-A-54 Figure 55. Simplified Input Stage Rev. C Page 7 of 4

18 B In the event that the crossover region cannot be avoided, specific attention has been given to the input stage to ensure constant transconductance and minimal offset in all regions of operation. The regions are PNP input pair running, NPN input pair running, and both running at the same time (in the mv crossover region). Maintaining constant transconductance in all regions ensures the best wideband distortion performance when going between these regions. With this technique, the can achieve greater than 8 db SFDR for a V p-p, MHz, and G = signal on ±.5 V supplies. Another requirement needed to achieve this level of distortion is that the offset of each pair must be laser trimmed to achieve greater than 8 db SFDR, even for low frequency signals. DC ERRORS The use two complementary input stages to achieve rail-to-rail input performance, as mentioned in the Input Stage section. To use the dc performance over the entire common-mode range, the input bias current and input offset voltage of each pair must be considered. The size of the discontinuity is defined as V DIS = ( ) RG RF VOS, PNP VOS, NPN RG Using the crossover select feature of the helps to avoid this region. In the event that the region cannot be avoided, the quantity (VOS, PNP VOS, NPN) is trimmed to minimize this effect. Because the input pairs are complementary, the input bias current reverses polarity when going through the crossover region shown in Figure 37. The offset between pairs is described by ( ) R G RF V OS, PNP VOS,NPN = IB,PNP IB,NPN RS RF OUTPUT STAGE RG The use a common-emitter output structure IB, PNP is the input bias current of either input when the PNP to achieve rail-to-rail output capability. The output stage is input pair is active, and IB, NPN is the input bias current of either designed to drive 5 ma of linear output current, 4 ma within input pair when the NPN pair is active. If RS is sized so that mv of the rail, and.5 ma within 35 mv of the rail. when multiplied by the gain factor it equals RF, this effect is Loading of the output stage, including any possible feedback eliminated. It is strongly recommended to balance the impedances in this manner when traveling through the crossover network, lowers the open-loop gain of the amplifier. Refer to Figure 49 for the loading behavior. Capacitive load can degrade region to minimize the dc error and distortion. As an example, the phase margin of the amplifier. The can assuming that the PNP input pair has an input bias current of drive up to pf, G =, as shown in Figure. A small (5 Ω 6 μa and the NPN input pair has an input bias current of to 5 Ω) series resistor, RSNUB, should be included, if the μa, a μv shift in offset occurs when traveling through capacitive load is to exceed pf for a gain of. Increasing the the crossover region with RF equal to Ω and RS equal to 5 Ω. closed-loop gain increases the amount of capacitive load that can be driven before a series resistor needs to be included. In addition to the input bias current shift between pairs, each input pair has an input bias current offset that contributes to the total offset in the following manner: Δ V OS = I R R G F B RS R G R F I B R F Referring to Figure 56, the output offset voltage of each pair is calculated by V = VOS, R G R RG F OS, PNP, OUT PNP, = V V OS, NPN, OUT OS, NPN R G R RG F V R OS G I B V AD87/ AD88 V I R S SELECT I B V Figure 56. Op Amp DC Error Sources V OUT 337-A-55 where the difference of the two is the discontinuity experienced when going through the crossover region. Rev. C Page 8 of 4

19 WIDEBAND OPERATION Voltage feedback amplifiers can use a wide range of resistor values to set their gain. Proper design of the application s feedback network requires consideration of the following issues: Poles formed by the amplifier s input capacitances with the resistances seen at the amplifier s input terminals Effects of mismatched source impedances Resistor value impact on the application s voltage noise Amplifier loading effects V IN R G R = R F R G R F V AD87/ AD88 C F C.μF C μf C3 μf SELECT V OUT The have an input capacitance of pf. This input capacitance forms a pole with the amplifier s feedback network, destabilizing the loop. For this reason, it is generally desirable to keep the source resistances below 5 Ω, unless some capacitance is included in the feedback network. Likewise, keeping the source resistances low also takes advantage of the s low input referred voltage noise of 4.3 nv/ Hz. Balanced input impedances can help to improve distortion With a wide bandwidth of over 9 MHz, the performance. When the amplifier transitions from PNP pair to have numerous applications and configurations. The AD87/ NPN pair operation, a change in both the magnitude and AD88 part shown in Figure 57 is configured as a noninverting amplifier. An easy selection table of gain, resistor values, times imbalanced input impedances, a change in offset can direction of the input bias current occurs. When multiplied bandwidth, slew rate, and noise performance is presented in result. The key to minimizing this distortion is to keep the input Table 5, and the inverting configuration is shown in Figure 58. impedances balanced on both inputs. Figure 59 shows the effect R F V C.μF C5 R V C4.μF 337-A-57 Figure 58. Wideband Inverting Gain Configuration CIRCUIT CONSIDERATIONS Balanced Input Impedances of the imbalance and degradation in distortion performance for a 5 Ω source impedance, with and without a 5 Ω balanced feedback path. V IN R G R R = R F R G AD87/ AD88 V C μf C3 μf C4.μF SELECT V OUT 337-A-56 Figure 57. Wideband Noninverting Gain Configuration Table 5. Component Values, Bandwidth, and Noise Performance (VS = ±.5 V) Noise Gain (Noninverting) RSOURCE (Ω) RF (Ω) RG (Ω) 3 db SS BW (MHz) 5 N/A Output Noise with Resistors (nv/ Hz) DISTORTION (db) G = V OUT = V p-p 3 R L = kω V S = 3V R F = Ω R F = 4.9Ω 9 R F = 49.9Ω. Figure 59. SFDR vs. Frequency and Various RF 337-A-58 Rev. C Page 9 of 4

20 PCB Layout As with all high speed op amps, achieving optimum performance from the requires careful attention to PCB layout. Particular care must be exercised to minimize lead lengths of the bypass capacitors. Excess lead inductance can influence the frequency response and even cause high frequency oscillations. The use of a multilayer board with an internal ground plane can reduce ground noise and enable a tighter layout. To achieve the shortest possible lead length at the inverting input, the feedback resistor, RF, should be located beneath the board and span the distance from the output, Pin 6, to the input, Pin. The return node of the resistor, RG, should be situated as closely as possible to the return node of the negative supply bypass capacitor connected to Pin 4. On multilayer boards, all layers underneath the op amp should be cleared of metal to avoid creating parasitic capacitive elements. This is especially true at the summing junction (the input). Extra capacitance at the summing junction can cause increased peaking in the frequency response and lower phase margin. Grounding To minimize parasitic inductances and ground loops in high speed, densely populated boards, a ground plane layer is critical. Understanding where the current flows in a circuit is critical in the implementation of high speed circuit design. The length of the current path is directly proportional to the magnitude of the parasitic inductances and, therefore, the high frequency impedance of the path. Fast current changes in an inductive ground return can create unwanted noise and ringing. The length of the high frequency bypass capacitor pads and traces is critical. A parasitic inductance in the bypass grounding works against the low impedance created by the bypass capacitor. Because load currents flow from supplies as well as ground, the load should be placed at the same physical location as the bypass capacitor ground. For large values of capacitors, which are intended to be effective at lower frequencies, the current return path length is less critical. Power-Supply Bypassing Power-supply pins are actually inputs, and care must be taken to provide a clean, low noise, dc voltage source to these inputs. The bypass capacitors have two functions: Provide a low impedance path for unwanted frequencies from the supply inputs to ground, thereby reducing the effect of noise on the supply lines. Provide sufficient localized charge storage, for fast switching conditions and minimizing the voltage drop at the supply pins and the output of the amplifier. This is usually accomplished with larger electrolytic capacitors. Decoupling methods are designed to minimize the bypassing impedance at all frequencies. This can be accomplished with a combination of capacitors in parallel to ground. Good-quality ceramic chip capacitors should be used and always kept as close as possible to the amplifier package. A parallel combination of a. μf ceramic and a μf electrolytic covers a wide range of rejection for unwanted noise. The μf capacitor is less critical for high frequency bypassing, and, in most cases, one per supply line is sufficient. Rev. C Page of 4

21 APPLICATIONS USING THE SELECT PIN The s unique SELECT pin has two functions: The power-down function places the into low power consumption mode. In power-down mode, the amplifiers draw 45 μa (typical) of supply current. In this application, the SELECT pins are biased to avoid the crossover region of the AD88 for low distortion operation. Summary test data for the schematic shown in Figure 6 is listed in Table 8. The second function, as mentioned in the Theory of Operation section, shifts the crossover point (where the NPN/PNP input differential pairs transition from one to the other) closer to either the positive supply rail or the negative supply rail. This selectable crossover point allows the user to minimize distortion based on the input signal and environment. The default state is. V from the positive power supply, with the SELECT pin left floating or in three-state. ANALOG INPUT INPUT RANGE (.5V TO.65V) Table 6 lists the SELECT pin s required voltages and modes. AD88 ANALOG INPUT Table 6. SELECT Pin Mode Control.7nF 4MHz LPF SELECT Pin Voltage (V) SELECT Mode VS = ±5 V VS = 5 V VS = 3 V (OPEN) 337-A-59 Disable 5 to 4. to.8 to.8 Figure 6. Unity Gain Differential Drive Crossover Referenced 4. to.8 to.7.8 to.7. V to Positive 3.3 Supply Table 8. ADC Driver Performance, fc = khz, VOUT = 4.7 V p-p Crossover Referenced 3.3 to 5.7 to 5..7 to 3.. V to Negative Parameter Measurement Supply Second Harmonic Distortion 5 db Third Harmonic Distortion db When the input stage transitions from one input differential THD db pair to the other, there is virtually no noticeable change in the SFDR 5 dbc output waveform. 5V AD88 SELECT (OPEN).μF 5V.μF 5Ω.7nF 5Ω 4MHz LPF 5V AD BITS The disable time of the amplifiers is loaddependent. Typical data is presented in Table 7. See Figure 5 and Figure 53 for the actual switching measurements. Table 7. DISABLE Switching Speeds Supply Voltages (RL = kω) Time ±5 V 5 V 3 V ton 45 ns 5 ns 5 ns toff 98 ns ns 5 ns DRIVING A 6-BIT ADC With the adjustable crossover distortion selection point and low noise, the AD88 is an ideal amplifier for driving or buffering input signals into high resolution ADCs such as the AD7767, a 6-bit, LSB INL, MSPS differential ADC. Figure 6 shows the typical schematic for driving the ADC. The AD88 driving the AD7677 offers performance close to non-rail-to-rail amplifiers and avoids the need for an additional supply other than the single 5 V supply already used by the ADC. As shown in Figure 6, the AD88 and AD7677 combination offers excellent integral nonlinearity (INL). INL (LSB) CODE Figure 6. Integral Nonlinearity 337-A-6 Rev. C Page of 4

22 BAND-PASS FILTER In communication systems, active filters are used extensively in signal processing. The are excellent choices for active filter applications. In realizing this filter, it is important that the amplifier have a large signal bandwidth of at least the center frequency, fo. Otherwise, a phase shift can occur in the amplifier, causing instability and oscillations. The test data shown in Figure 63 indicates that this design yields a filter response with a center frequency of fo = MHz, and a bandwidth of 45 khz. CH S LOG 5dB/REF 6.34dB :6.3348dB. MHz In Figure 6, the part is configured as a MHz band-pass filter. The target specifications are fo = MHz and a 3 db pass band of 5 khz. To start the design, select fo, Q, C, and R4. Then use the following equations to calculate the remaining variables: fo (MHz) Q = Band Pass (MHz) k = πfoc. FREQUENCY MHz 337-A-6 C =.5C Figure 63. Band-Pass Filter Response R = /k, R = /(3k), R3 = 4/k V IN R 36Ω C 5pF R3 634Ω AD87/ AD88 SELECT V OUT DESIGN TOOLS AND TECHNICAL SUPPORT H = /3(6.5 /Q) Analog Devices, Inc. (ADI) is committed to simplifying the design process by providing technical support and online R5 = R4/(H ) design tools. ADI offers technical support via free evaluation boards, sample ICs, interactive evaluation tools, data sheets, R 5 5Ω C3 spice models, application notes, and phone and support.μf C available at analog.com. pf 5 C4.μF R5 53Ω R4 53Ω 337-A-6 Figure 6. Band-Pass Filter Schematic Rev. C Page of 4

23 OUTLINE DIMENSIONS 5. (.968) 4.8 (.89) 4. (.574) 3.8 (.497) (.44) 5.8 (.84).5 (.98). (.4) COPLANARITY..7 (.5) BSC SEATING PLANE.75 (.688).35 (.53).5 (.).3 (.).5 (.98).7 (.67) 8.5 (.96).5 (.99) 45.7 (.5).4 (.57) COMPLIANT TO JEDEC STANDARDS MS-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches).9 BSC BSC.8 BSC 3 PIN.95 BSC.9.3 BSC MAX MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-78AB Figure Lead Small Outline Transistor Package [SOT-3] (RT-6) Dimensions shown in millimeters 3. BSC 3. BSC BSC 5 PIN.5 BSC COPLANARITY.. MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-87BA Figure 66. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters Rev. C Page 3 of 4

24 ORDERING GUIDE Model Minimum Ordering Quantity Temperature Range Package Description Package Option Branding AD87AR 4 C to 5 C 8-Lead SOIC R-8 AD87AR-REEL,5 4 C to 5 C 8-Lead SOIC R-8 AD87AR-REEL7, 4 C to 5 C 8-Lead SOIC R-8 AD87ARZ 4 C to 5 C 8-Lead SOIC R-8 AD87ARZ-REEL,5 4 C to 5 C 8-Lead SOIC R-8 AD87ARZ-REEL7, 4 C to 5 C 8-Lead SOIC R-8 AD87ART-R 5 4 C to 5 C 6-Lead SOT-3 RT-6 H4B AD87ART-REEL, 4 C to 5 C 6-Lead SOT-3 RT-6 H4B AD87ART-REEL7 3, 4 C to 5 C 6-Lead SOT-3 RT-6 H4B AD87ARTZ-R 5 4 C to 5 C 6-Lead SOT-3 RT-6 H4B# AD87ARTZ-REEL, 4 C to 5 C 6-Lead SOT-3 RT-6 H4B# AD87ARTZ-REEL7 3, 4 C to 5 C 6-Lead SOT-3 RT-6 H4B# AD88AR 4 C to 5 C 8-Lead SOIC R-8 AD88AR-REEL,5 4 C to 5 C 8-Lead SOIC R-8 AD88AR-REEL7, 4 C to 5 C 8-Lead SOIC R-8 AD88ARZ 4 C to 5 C 8-Lead SOIC R-8 AD88ARZ-REEL,5 4 C to 5 C 8-Lead SOIC R-8 AD88ARZ-REEL7, 4 C to 5 C 8-Lead SOIC R-8 AD88ARM 4 C to 5 C -Lead MSOP RM- H5B AD88ARM-REEL 3, 4 C to 5 C -Lead MSOP RM- H5B AD88ARM-REEL7, 4 C to 5 C -Lead MSOP RM- H5B AD88ARMZ 4 C to 5 C -Lead MSOP RM- H5B# AD88ARMZ-REEL 3, 4 C to 5 C -Lead MSOP RM- H5B# AD88ARMZ-REEL7, 4 C to 5 C -Lead MSOP RM- H5B# Z = Pb-free part, # denotes lead-free, may be top or bottom marked. 5 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C3373/5(C) Rev. C Page 4 of 4