Low Distortion, Precision, Wide Bandwidth Op Amp AD9617

Transcription

1 a FEATURES Usable Closed-Loop Gain Range: to 4 Low Distortion: 67 dbc (2nd) at 2 MHz Small Signal Bandwidth: 9 MHz (A V = +3) Large Signal Bandwidth: 5 MHz at 4 V p-p Settling Time: ns to.%; 4 ns to.2% Overdrive and Output Short Circuit Protected Fast Overdrive Recovery DC Nonlinearity ppm APPLICATIONS Driving Flash Converters D/A Current-to-Voltage Converters IF, Radar Processors Baseband and Video Communications Photodiode, CCD Preamps Low Distortion, Precision, Wide Bandwidth Op Amp AD967 PIN CONFIGURATION AD967 NC INPUT +INPUT * +V S OUTPUT V S 4 NC = NO CONNECT *OPTIONAL +V S **OPTIONAL V S NOTE: FOR BEST SETTLING TIME AND DISTORTION PERFORMANCE, USE OPTIONAL SUPPLY CONNECTIONS. PERFORMANCE INDICATED IN SPECIFICATIONS IS BASED ON SUPPLY CONNECTIONS TO THESE PINS. 5 ** GENERAL DESCRIPTION The AD967 is a current feedback amplifier which utilizes a proprietary architecture to produce superior distortion and dc precision. It achieves this along with fast settling, very fast slew rate, wide bandwidth (both small signal and large signal) and exceptional signal fidelity. The device achieves 67 dbc 2nd harmonic distortion at 2 MHz while maintaining 9 MHz small signal and 5 MHz large signal bandwidths. These attributes position the AD967 as an ideal choice for driving flash ADCs and buffering the latest generation of DACs. Optimized for applications requiring gain between ± to ±5, the AD967 is unity gain stable without external compensation. The AD967 offers outstanding performance in high fidelity, wide bandwidth applications in instrumentation ranging from network and spectrum analyzers to oscilloscopes, and in military systems such as radar, SIGINT and ESM systems. The superior slew rate, low overshoot and fast settling of the AD967 allow the device to be used in pulse applications such as communications receivers and high speed ATE. Most monolithic op amps suffer in these precision pulse applications due to slew rate limiting. The AD967J operates over the range of C to +7 C and is available in either an 8-lead plastic DIP or an 8-ead plastic small outline package (SOIC). REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 96, Norwood, MA , U.S.A. Tel: 78/ World Wide Web Site: Fax: 78/ Analog Devices, Inc., 999

2 AD967 SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supply Voltages (±V S ) V Common-Mode Input Voltage ±Vs Differential Input Voltage V Continuous Output Current ma Operating Temperature Ranges AD967JN/JR C to +7 C Storage Temperature AD967JN/JR C to +25 C Junction Temperature 3 AD967JN/JR C Lead Soldering Temperature ( Seconds) C NOTES Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Output is short circuit protected to ground, but not to supplies. Continuous short circuit to ground may affect device reliability. 3 Typical thermal impedances (part soldered onto board): Plastic DIP: θ JA = 4 C/W; θ JC = 3 C/W. SOIC Package: θ JA = 55 C/W; θ JC = 4 C/W. DC ELECTRICAL CHARACTERISTICS Test AD967JN/JR AD967AQ/SQ* AD967BQ/TQ* Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Units Input Offset Voltage, C I mv Input Offset Voltage TC 2 Full IV µv/ C Input Bias Current 2 Inverting +25 C I µa Noninverting +25 C I µa Input Bias Current TC 2 Noninverting Full IV na/ C Inverting Full IV na/ C Input Resistance Noninverting +25 C V kω Input Capacitance Noninverting +25 C V pf Common-Mode Input Range 3 T = T MAX II ±.4 ±.5 ±.4 ±.5 ±.4 ±.5 V T = T MIN to +25 C II ±.7 ±.8 ±.7 ±.8 ±.7 ±.8 V Common-Mode Rejection Ratio 4 T = T MIN to T MAX II db T = T MIN to +25 C II db Power Supply Rejection Ratio V S = ±5% Full II db Open Loop Gain T O At DC +25 C V kω Nonlinearity At DC +25 C IV ppm Output Voltage Range +25 C II ±3.4 ±3.8 ±3.4 ±3.8 ± V Output Impedance At DC +25 C V Ω Output Current (5 Ω Load) T = +25 C to T MAX II ma T = T MIN II ma NOTES *Pending obsoletion: last-time buy October 25, 999. Measured with respect to the inverting input. 2 Typical is defined as the mean of the distribution. 3 Measured in voltage follower configuration. 4 Measured with V IN = +.25 V. Specifications subject to change without notice. (Unless otherwise noted, A V = +3; V S = 5 V; R F = 4 ; R LOAD = ) 2 REV. B

3 AC ELECTRICAL CHARACTERISTICS AD967 Test AD967JN/JR AD967AQ/SQ* AD967BQ/TQ* Parameter Conditions Temp Level Min Typ Max Min Typ Max Min Typ Max Units FREQUENCY DOMAIN Bandwidth ( 3 db) Small Signal V OUT 2 V p-p Full II MHz Large Signal V OUT = 4 V p-p Full IV MHz Bandwidth Variation vs. A V A V = to ±5 +25 C V MHz Amplitude of Peaking (<5 MHz) T = T MIN to +25 C II.3.3 db T = T MAX II.6.6 db Amplitude of Peaking (>5 MHz) T = T MIN to +25 C II.8.8 db T = T MAX II.. db Amplitude of Roll-Off (<6 MHz) Full II db Phase Nonlinearity DC to 75 MHz +25 C V Degree 2nd Harmonic Distortion 2 V p-p; 4.3 MHz Full IV dbc 2 V p-p; 2 MHz Full IV dbc 2 V p-p; 6 MHz Full II dbc 3rd Harmonic Distortion 2 V p-p; 4.3 MHz Full IV dbc 2 V p-p; 2 MHz Full IV dbc 2 V p-p; 6 MHz Full II dbc Input Noise Voltage MHz +25 C V nv/ Hz Inverting Input Noise Current MHz +25 C V pa/ Hz Average Equivalent Integrated Input Noise Voltage. MHz to 2 MHz +25 C V µv, rms TIME DOMAIN Slew Rate V OUT = 4 V Step Full IV V/µs Rise/Fall Time V OUT = 2 V Step Full IV ns V OUT = 4 V Step T = +25 C to T MAX IV ns V OUT = 4 V Step T = T MIN IV ns Overshoot V OUT = 2 V Step Full IV % Settling Time To.% V OUT = 2 V Step Full IV 5 5 ns To.2% V OUT = 2 V Step Full IV ns To.% V OUT = 4 V Step Full IV 6 6 ns To.2% V OUT = 4 V Step Full IV ns 2 Overdrive Recovery to ±2 mv of Final Value V IN =.7 V Step +25 C V ns Propagation Delay +25 C V ns Differential Gain Full V <. <. <. % Differential Phase Full V... Degree POWER SUPPLY REQUIREMENTS Quiescent Current +I S Full II ma I S Full II ma NOTES *Pending obsoletion: last-time buy October 25, 999. Frequency = 4.3 MHz; R L = 5 Ω; A V = +3. Specifications subject to change without notice. (Unless otherwise noted, A V = +3; V S = 5 V; R F = 4 ; R LOAD = ) REV. B 3

4 AD967 EXPLANATION OF TEST LEVELS Test Level I - % production tested. II - % production tested at +25 C and sample tested at specified temperatures. AC testing of J grade devices done on sample basis. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - All devices are % production tested at +25 C. % production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. INPUT +INPUT DIE CONNECTIONS +V S TOP VIEW (Not to Scale) V S V S DIE SIZE = mils +V S OUTPUT ORDERING GUIDE Temperature Package Package Model Range Description Option AD967JN C to +7 C Plastic DIP N-8 AD967JR C to +7 C SOIC SO-8 AD967JR-REEL C to +7 C 3" Tape and Reel SO-8 4 REV. B

5 AD967 Typical Performance Characteristics (A V = +3; V S = 5 V; R F = 4 V, unless otherwise noted) 3 8 MAGNITUDE db A V = +5 A V = PHASE Degrees db CMRR 6 A V = Figure. Noninverting Frequency Response 55 6 PSRR k k k M M M FREQUENCY Hz Figure 4. CMRR and PSRR 3 8. MAGNITUDE db A V = 5 A V = 2 A V = PHASE Degrees 35 8 SETTLING PERCENTAGE % TEST CIRCUIT 6pF V OUT = 4V STEP Figure 2. Inverting Frequency Response TIME s Figure 5. Settling Time 2 5 GAIN 3..8 TEST CIRCUIT GAIN db PHASE TEST CIRCUIT RELATIVE PHASE Degrees SETTLING PERCENTAGE % pF V OUT = 4V STEP k 24 k M M M G FREQUENCY Hz Figure 3. Open Loop Transimpedance Gain [T(s) Relative to Ω] TIME s Figure 6. Long Term Settling Time REV. B 5

6 AD V OUT = 2V p-p = 2ND HARMONIC = 3RD HARMONIC 5 5 dbc LOAD 5 LOAD INTERCEPT +dbm 4 3 TEST CIRCUIT Figure 7. Harmonic Distortion Figure. Intermodulation Distortion (IMD) MAGNITUDE db R L = R L = 5 R L = PHASE Degrees ANALOG INPUT Volts A V = +3 TEST CIRCUIT 6pF Figure 8. Frequency Response vs. R LOAD 2. A V = ns/div Figure. Large Signal Pulse Response 5 7 A V = +3 pa/ Hz pa/ Hz (INVERTING) nv/ Hz nv/ Hz ANALOG INPUT Volts TEST CIRCUIT 6pF k k k Figure 9. Equivalent Input Noise A V = 3 ns/div Figure 2. Small Signal Pulse Response 6 REV. B

7 AD967 THEORY OF OPERATION The AD967 has been designed to combine the key attributes of traditional low frequency precision amplifiers with exceptional high frequency characteristics that are independent of closedloop gain. Previous high frequency closed-loop amplifiers have low open loop gain relative to precision amplifiers. This results in relatively poor dc nonlinearity and precision, as well as excessive high frequency distortion due to open loop gain roll-off. Operational amplifiers use two basic types of feedback correction, each with advantages and disadvantages. Voltage feedback topologies exhibit an essentially constant gain bandwidth product. This forces the closed-loop bandwidth to vary inversely with closed-loop gain. Moreover, this type design typically slew rate limits in a way that causes the large signal bandwidth to be much lower than its small signal characteristics. A newer approach is to use current feedback to realize better dynamic performance. This architecture provides two key attributes over voltage feedback configurations: () avoids slew rate limiting and therefore large signal bandwidth can approach small signal performance; and (2) low bandwidth variation versus gain settings, due to the inherently low open loop inverting input resistance (R S ). The AD967 uses a new current feedback topology that overcomes these limitations and combines the positive attributes of both current feedback and voltage feedback designs. These devices achieve excellent high frequency dynamics (slew, BW and distortion) along with excellent low frequency linearity and good dc precision. DC GAIN CHARACTERISTICS A simplified equivalent schematic is shown below. When operating the device in the inverting mode, the input signal error current (I E ) is amplified by the open loop transimpedance gain (T O ). The output signal generated is equal to T O I E. Negative feedback is applied through R F such that the device operates at a gain (G) equal to R F /. Noninverting operation is similar, with the input signal applied to the high impedance buffer (noninverting) input. As before, an output (buffer) error current (I E ) is generated at the low impedance inverting input. The signal generated at the output is fed back to the inverting input such that the external gain is (l + R F / ). The feedback mechanics are identical to the voltage feedback topology when exact equations are used. The major difference lies in the front end architecture. A voltage feedback amplifier has symmetrical high resistance (buffered) inputs. A current feedback amplifier has a high noninverting resistance (buffered) input and a low inverting (buffer output) input resistance. The feedback mechanics can be easily developed using current feedback and transresistance open loop gain T(s) to describe the I/O relationship. (See typical specification chart.) DC closed-loop gain for the AD967 can be calculated using the following equations: G = V O V I R F / +/LG G = V O + R F / V N +/LG where inverting () noninverting (2) ( ) (3) ()R ( S ) LG R S R F + R S T s Because the noninverting input buffer is not ideal, input resistance R S (at dc) is gain dependent and is typically higher for noninverting operation than for inverting operation. R S will approach the same value ( 7 Ω) for both at input frequencies above 5 MHz. Below the open loop corner frequency, the noninverting R S can be approximated as: R S () ( noninverting ) 7+ T s A O =7+ T O A Odc (4) where: A O = Open Loop Voltage Gain G 6 Inverting R S below the open loop corner frequency can be approximated as: R S () ( inverting ) 7+ T s A O =7+ T O A Odc (5) where: A O = 4,. The AD967 approaches this condition. With T O = 6 Ω, R L = 5 Ω and R S = 25 Ω (dc), a gain error no greater than.5% typically results for G = and.5% for G = 4. Moreover, the architecture linearizes the open loop gain over its operating voltage range and temperature resulting in 6 bits of linearity. R L = V N V I C I + L S R S I E C C T O V O ERROR RELATIVE TO FS.2%/DIVISION % R F Figure 3. Equivalent Circuit 2 2 V OUT Volts Figure 4. DC Nonlinearity vs. V OUT REV. B 7

8 AD967 AC GAIN CHARACTERISTICS Closed-loop bandwidth at high frequencies is determined primarily by the roll-off of T(s). But circuit layout is critical to minimize external parasitics which can degrade performance by causing premature peaking and/or reduced bandwidth. The inverting and noninverting dynamic characteristics are similar. When driving the noninverting input, the inverting input capacitance (C I ) will cause the noninverting closed-loop bandwidth to be higher than the inverting bandwidth for gains less than two (2). In the remaining cases, inverting and noninverting responses are nearly identical. For best overall dynamic performance, the value of the feedback resistor (R F ) should be 4 ohms. Although bandwidth reduces as closed-loop gain increases, the change is relatively small due to low equivalent series input impedance, Z S. (See typical performance charts.) The simplified equations governing the device s dynamic performance are shown below. Closed-Loop Gain vs. Frequency: (noninverting operation) V O V I + R F s + R S + where: = R F C C =.9 ns (R F = 4 Ω) Slew Rate where: K = + R S (6) V O R F KC C e τ/r FKC C (7) Increasing Bandwidth at Low Gains By reducing R F, wider bandwidth and faster pulse response can be attained beyond the specified values, although increased overshoot, settling time and possible ac peaking may result. As a rule of thumb, overshoot and bandwidth will increase by % and 8%, respectively, for a 5% reduction in R F at gains of ±. Lower gains will increase these sensitivities. Equations 6 and 7 are simplified and do not accurately model the second order (open loop) frequency response term which is the primary contributor to overshoot, peaking and nonlinear bandwidth expansion. (See Open Loop Bode Plots.) The user should exercise caution when selecting R F values much lower than 4 Ω. Note that a feedback resistor must be used in all situations, including those in which the amplifier is used in a noninverting unity gain configuration. Increasing Bandwidth at High Gains Closed loop bandwidth can be extended at high closed loop gain by reducing R F. Bandwidth reduction is a result of the feedback current being split between R S and. As the gain increases (for a given R F ), more feedback current is shunted through, which reduces closed loop bandwidth (see Equation 6). To maintain specified BW, the following equations can be used to approximate R F and for any gain from ±l to ±5. R F = 424 ± 8 G (8) (+ for inverting and for noninverting) G G G G G = Closed Loop Gain. (noninverting) (9) (inverting) () Bandwidth Reduction The closed loop bandwidth can be reduced by increasing R F. Equations 6 and 7 can be used to determine the closed loop bandwidth for any value R F. Do not connect a feedback capacitor across R F, as this will degrade dynamic performance and possibly induce oscillation. DC Precision and Noise Output offset voltage results from both input bias currents and input offset voltage. These input errors are multiplied by the noise gain term ( + R F / ) and algebraically summed at the output as shown below. V O = V IO + R F R ± IBn R N + R F I R ± IBi R F () I Since the inputs are asymmetrical, IBi and IBn do not correlate. Canceling their output effects by making R N = R F will not reduce output offset errors, as it would for voltage feedback amplifiers. Typically, IBn is 5 µa and V IO is +.5 mv (I sigma =.3 mv), which means that the dc output error can be reduced by making R N Ω. Note that the offset drift will not change significantly because the IBn TC is relatively small. (See specification table.) IBi/IBn A 5 5 R N IBi IBn R F V OUT Figure 5. Output Offset Voltage IBn V IO IBi..5 V IO ma.5 55 C 25 C Figure 6. DC Accuracy. 25 C 8 REV. B

9 AD967 The effective noise at the output of the amplifier can be determined by taking the root sum of the squares of Equation and applying the spectral noise values found in the typical graph section. This applies to noise from the op amp only. Note that both the noise figure and equivalent input offset voltages improve as the closed loop gain is increased (by keeping R F fixed and reducing with R N = Ω). In CLI 4 R SERIES R L 5 CL Figure 7. Capacitive Load Figure Capacitive Load Considerations Due to the low inverting input resistance (R S ) and output buffer design, the AD967 can directly handle input and/or output load capacitances of up to 2 pf. See the chart below. A small series resistor can be used at the output of the amplifier and outside of the feedback loop to facilitate driving larger capacitive loads or for obtaining faster settling time. For capacitive loads above 2 pf, R SERIES should be considered. APPLYING THE AD967 The superior frequency and time domain specifications of the AD967 make it an obvious choice for driving flash converters and buffering the outputs of high speed DACs. Its outstanding distortion and noise performance make it well suited as a driver for analog to digital converters (ADCs) with resolutions as high as 6 bits. Typical circuits for inverting and noninverting applications are shown in Figures 2 and 2. Closed-loop gain for noninverting configurations is determined by the value of RI according to the equation: G = + R F (2) V IN N +V S. F AD F. F V OUT SETTLING TIME TO.2% ns V OUT = 4V STEP CL = pf V OUT = 4V STEP CLI = pf 5pF 4pF/DIV 25pF pf 4pF/DIV 3pF INPUT CAPACITANCE CLI INPUT CAPACITANCE CL R SERIES = Figure 8. Input/Output Capacitance Comparisons F. F 3.3 F V S Figure 2. Noninverting Operation +V S 3.3 F. F. F 2 AD967 V OUT R SERIES 5 V IN R TERM 4. F 5. F CL pf Figure 9. Recommended R SERIES vs. CL V S 3.3 F Figure 2. Inverting Operation REV. B 9

10 AD967 LAYOUT CONSIDERATIONS As with all high performance amplifiers, printed circuit layout is critical in obtaining optimum results with the AD967. The ground plane in the area of the amplifier should cover as much of the component side of the board as possible. Each power supply trace should be decoupled close to the package with at least a 3.3 µf tantalum and a low inductance,. µf ceramic capacitor. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). All lead lengths for input, output and the feedback resistor should be kept as short as possible. All gain setting resistors should be chosen for low values of parasitic capacitance and inductance, i.e., microwave resistors and/or carbon resistors. Stripline techniques should be used for lead lengths in excess of one inch. Sockets should be avoided if possible because of their stray inductance and capacitance. C353b 9/99 Small Outline Package (SO-8).98 (5.).88 (4.74).58 (4.).5 (3.8) (6.2).228 (5.8) PIN. (.25).4 (.) SEATING PLANE.5 (.27) BSC.8 (.46).4 (.36).69 (.75).53 (.35).5 (.38).7 (.8).25 (5.2).8 (4.6) 8.45 (.5).2 (.5) Plastic DIP (N-8).43 (.92).348 (8.84) (7.).24 (6.) PIN.2 (5.33) MAX.2 (5.5).25 (3.8). (2.54) BSC.22 (.558).4 (.356).7 (.77).45 (.5).6 (.52).5 (.38).5 (3.8) MIN SEATING PLANE (8.25).3 (7.62).5 (.38).8 (.24) PRINTED IN U.S.A. REV. B