FHP3194 4:1 High-Speed Multiplexer

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1 FHP9 : High-Speed Multiplexer Features.dB gain flatness to V pp.%/. differential gain/phase error MHz large signal -db bandwidth at G = V/µs slew rate 7mA output current (easily drives two video loads) 7dB channel-to-channel isolation ma supply current.ma supply current in disable mode.ma supply current in shutdown mode Fully specified at ±V supplies Lead-free SOIC- and TSSOP- packages Applications Video switchers and routers Multiple input HDTV switching Picture-in-picture video switch Multi-channel ADC driver Description October The FHP9 is a : analog multiplexer designed for high-speed video applications. The output amplifier is a high-speed current feedback amplifier that offers stellar large signal performance of MHz -db bandwidth and 9MHz.dB bandwidth. The gain of the output amplifier is selectable through two external resistors (R f and R g ), allowing further design flexibility. The V pp bandwidth performance and V/μs slew rate exceed the requirements of high-definition television (HDTV) and other multimedia applications. The output amplifier also provides ample output current to drive multiple video loads. Two address bits (A and A) are used to select one of the four inputs. The FHP9 offers better than 7dB channel isolation. The FHP9 offers both shutdown and disable capability. During shutdown, the FHP9 consumes only.ma of supply current. During disable mode, only the output amplifier is disabled, reducing output glitches and allowing for multiplexer expansion. Functional Block Diagram SOIC/TSSOP IN +Vs GND OUT IN -VIN GND SD IN -Vs LOGIC 9 EN A IN 7 A Ordering Information Part Number Package Pb-Free Operating Temperature Range Packaging Method FHP9IMX SOIC- Yes - C to + C Reel FHP9IMTCX TSSOP- Yes - C to + C Reel Moisture sensitivity level for all parts is MSL-. Fairchild Semiconductor Corporation FHP9 Rev...

2 Pin Configuration IN GND IN GND IN -Vs IN FHP9 SOIC/TSSOP 7 LOGIC +Vs 9 OUT -VIN SD EN A A Pin Assignments Pin# Pin Name Description IN Input, channel GND Must be connected to ground IN Input, channel GND Must be connected to ground IN Input, channel -Vs Negative supply 7 IN Input, channel A Logic input A 9 A Logic input A EN Enable pin, = Disable, = Enable; Enabled when left floating SD Shutdown pin, = Shutdown, = Active; Active when left floating -VIN Inverting Input of output amplifier OUT Output +Vs Positive supply Truth Table A A EN SD OUT CH CH CH CH X X Disable X X X Shutdown Fairchild Semiconductor Corporation FHP9 Rev...

3 Absolute Maximum Ratings The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table defines the conditions for actual device operation. Parameter Min. Max. Unit Supply Voltage. V Input Voltage Range -V s -.V +V s +.V V Reliability Information Parameter Min. Typ. Max. Unit Junction Temperature C Storage Temperature Range - C Lead Temperature (Soldering, s) C Package Thermal Resistance -Lead TSSOP C/W -Lead SOIC C/W Notes:. Package thermal resistance (q JA ), JDEC standard, multi-layer test boards, still air. ESD Protection Product SOIC- TSSOP- Human Body Model (HBM).kV kv Charged Device Model (CDM) kv kv Recommended Operating Conditions Parameter Min. Typ. Max. Unit Operating Temperature Range - + C Supply Voltage Range V Fairchild Semiconductor Corporation FHP9 Rev...

4 Electrical Characteristics at ±V T A = C, V s = ±V, R f =, R L =Ω, G = ; unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units Frequency Domain Response UGBW -db Bandwidth G = +, R f =.kω V OUT =.V pp MHz BW SS -db Bandwidth G = +, V OUT =.V pp MHz BW LS Full Power Bandwidth G = +, V OUT = V pp MHz Time Domain Response.dB Gain Flatness G = +, V OUT =.V pp MHz.dB Gain Flatness G = +, V OUT = V pp 9 MHz t R, t F Rise and Fall Time V OUT = V step; (% to 9%) ns t S Settling Time to.% V OUT = V step ns OS Overshoot V OUT =.V step % SR Slew Rate V step V/µs Distortion / Noise Response HD nd Harmonic Distortion V pp, MHz, worst channel - dbc HD rd Harmonic Distortion V pp, MHz, worst channel -9 dbc THD Total Harmonic Distortion V pp, MHz, worst channel -7 db DG Differential Gain NTSC (.MHz), DC-coupled. % DP Differential Phase NTSC (.MHz), DC-coupled. e n Input Voltage Noise > MHz 7 nv/ Hz i n+ Input Current Noise (+) > MHz pa/hz i n- Input Current Noise (-) > MHz pa/hz X TALK All Hostile Crosstalk Channel-to-channel MHz/ MHz, worst CH combination DC Performance -/- db V IO Input Offset Voltage () mv dv IO Average Drift. µv/ C V IOM Input Offset Voltage Matching () Channel-to-channel -. mv I bn Input Bias Current Non-inverting () Pins,,,7 - µa di bn Average Drift na/ C I bi Input Bias Current Inverting () Pin - µa di bni Average Drift na/ C GM Gain Matching Channel-to-channel. % PSRR Power Supply Rejection Ratio () DC db I S Supply Current () ma I EN Disable Supply Current () Disable mode. ma I SD Shutdown Supply Current () Shutdown mode. ma Switching Characteristics T S Switching Time % Logic to: 9% output (% output settling) () 99% output (% output settling) () Channel-to-channel IN, IN = +.V; IN, IN = -.V IN, IN = +.V; IN, IN = -.V ns ns V SW Channel Switch. Trans. (Glitch) All inputs grounded 7 mv pp Notes:. % tested at C Fairchild Semiconductor Corporation FHP9 Rev...

5 Electrical Characteristics at ±V (Continued) T A = C, V s = ±V, R f =, R L =Ω, and G = unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit Digital Inputs V IH Logic-High Threshold A, A, EN, and SD pins. V V IL Logic-Low Threshold A, A, EN, and SD pins. V I IH Logic Pin Input Current High A, A, EN, and SD pins Logic input =V I IL Logic Pin Input Current Low A, A, EN, and SD pins Logic input =V Disable Characteristics μa μa EN ISO Disable Isolation MHz/MHz, worst comb. -7/- db SD ISO Shutdown Isolation MHz/MHz, worst comb. -7/- db CH ISO CH-to-CH Isolation () MHz/MHz, worst comb. -7/- db ENT ON Turn-on time (Disable to ON) V IN = mv ns ENT OFF Turn-off time (ON to Disable) V IN = mv ns SDT ON Turn-on time (Shutdown to ON) V IN = mv ns SDT OFF Turn-off time (ON to Shutdown) V IN = mv ns Input Characteristics R IN Input Resistance kw C IN Input Capacitance.7 pf CMIR Input Common Mode V Range ±. V CMRR Common Mode Rejection Ratio () DC db Output Characteristics V OUT Output Voltage Swing R L = kw ±. V R L = W () ±. ±. V I OUT Linear Output Current V IN = ±7 ma I SC Short-Circuit Output Current V OUT = GND, R L = Ω ± ma R OUT Output Resistance Enabled. Ω Disabled kω C OUT Output Capacitance.7 pf Notes:. % tested at C. SD and EN pins are grounded. IN and IN = +.V, IN and IN = -.V, see truth table to properly set A and A based on the channels driven. Switching time is the transition time from % of A or A input value (+.V) to the time at which the switched channel is at 9% (or 99%) of its final value.. Driving one channel and looking at worst case value from remaining channels. Fairchild Semiconductor Corporation FHP9 Rev...

6 Typical Performance Characteristics T A = C, V s = ±V, R f =, R L =Ω, and G = unless otherwise noted. Normalized Gain (db) G = R F =.kω G = R F = G = R F = Ω G = R F = Ω V o =.V pp -. Figure. Non-Inverting Freq. Response Normalized Gain (db) V o = V pp V S = V Figure. Gain Flatness vs. Frequency Rf Value 7 9 Gain (V/V) Figure. Recommended R f vs. Gain Normalized Gain (db) V o = V pp -. Figure. Gain Flatness vs. Frequency Normalized Gain (db) - - C L = pf R s = Ω - C L = pf - R s = Ω - - C L = pf R s = Ω -7 - V o =.V pp -9. Normalized Gain (db) V OUT = V pp V OUT = V pp V OUT = V pp Figure. Frequency Response vs. C L Figure. Frequency Response vs. V OUT Fairchild Semiconductor Corporation FHP9 Rev...

7 Typical Performance Characteristics T A = C, V s = ±V, R f =, R L =Ω, and G = unless otherwise noted. PSRR (db) 7 k Worst Channel k M M Frequency (Hz) M G CMRR (db) k k M M Frequency (Hz) M G Figure 7. PSRR vs. Frequency Figure. CMRR vs. Frequency - - R L = Ω V o = V pp Transimpedance (Ω) Transimpedance Phase - Phase (deg) HD (dbc) Worst CH Best CH - k k M M M Frequency (Hz) G - - Figure 9. Open Loop Transimpedance Gain and Phase Figure. HD vs. Frequency R L = Ω V o = V pp All Channels Worst CH MHz Worst CH MHz HD (dbc) HD (dbc) Best CH MHz Best CH MHz Worst CH MHz Best CH MHz V OUT (V pp ) Figure. HD vs. Frequency Figure. HD vs. V OUT Fairchild Semiconductor Corporation FHP9 Rev...

8 Typical Performance Characteristics T A = C, V s = ±V, R f =, R L =Ω, and G = unless otherwise noted. HD (dbc) All Channels MHz MHz MHz.... V OUT (V pp ) Differential Gain (%) AC Coupled, µf Phase Gain Input Amplitude (V) Differential Phase (deg) Figure. HD vs. VOUT Figure. Differential Gain and Phase Differential Gain (%) DC Coupled Phase Gain Differential Phase (deg) VOUT (V) R L = R L = kω R L = Ω R L = Ω R L = kω Input Amplitude (V) V IN (V) Figure. Differential Gain and Phase Figure. Output Swing vs. R L. V s = V Figure 7. Pulse Response Figure. Pulse Response Fairchild Semiconductor Corporation FHP9 Rev...

9 Typical Performance Characteristics T A = C, V s = ±V, R f =, R L =Ω, and G = unless otherwise noted Figure 9. Pulse Response A Input (V) - A Input Output Figure. Channel Switching Time A Input (V) A Input..... Output Figure. A Switching Glitch. -. A Input (V) A Input..... Output Figure. A Switching Glitch. -. SD Input (V) - SD Input Output 7 Figure. Shutdown Switching Time SD Input (V) 7. SD Input.... Output Figure. Shutdown Switching Glitch Fairchild Semiconductor Corporation 9 FHP9 Rev...

10 Typical Performance Characteristics T A = C, V s = ±V, R f =, R L =Ω, and G = unless otherwise noted. EN Input (V) - EN Input Output 7 Figure. Enable Switching Time EN Input (V) EN Input Output Figure. Enable Switching Glitch Off Isolation (db) Selected input to output SD EN Crosstalk (db) Unselected input to output Worst condition shown Figure 7. Off Isolation vs. Frequency Figure. Crosstalk vs. Frequency Input Voltage Noise (nv/ Hz) IZi (Ω) - - Disabled Enabled k k M M M Frequency (Hz) G Figure 9. Input Voltage Noise Figure. Closed-Loop Output Impedance Fairchild Semiconductor Corporation FHP9 Rev...

11 Application Information Circuit Diagrams IN IN IN.µF db (G = ) Configuration LOGIC 9 +V.µF.µF A EN RT* SD RT* OUT RF = RG =.µf 7 A RT* IN -V RT* *Termination resistors (RT = Ω) are optional. Figure. Typical Application Circuit db Gain (G = ) +V.µF db (G = ) Configuration IN.µF OUT IN RF =.k SD IN.µF LOGIC 9 A EN RT* RT*.µF 7 A RT* IN -V RT* *Termination resistors (RT = Ω) are optional. Figure. Typical Application Circuit db Gain (G = ) Fairchild Semiconductor Corporation FHP9 Rev...

12 Application Information General Description The FHP9 : multiplexer has four analog switches that drive the positive input of a high-speed current feedback amplifier. It is designed so that only one channel is on at a time. Tie unused inputs to ground. Figures and show typical application circuits for the FHP9 in db (G = ) and db (G = ) configurations. R f and R g Selection The output of the FHP9 is a current feedback amplifier. The gain of this amplifier is set by two external resistors: R f and R g. The frequency response and closed-loop bandwidth of the current feedback amplifier are highly dependant on the value of R f. For a gain of two, use R f =. For other gains, refer to the R f vs. GAIN plot in Figure. In general, a lower R f peaks the frequency response and increases bandwidth, while a higher R f will decrease bandwidth and roll off the frequency response. A feedback resistor is required for unity gain (G = ); the recommended value is.kω. A, A The A and A logic pins are TTL/CMOS compatible and are used to select which of the four inputs connects to the output. Refer to the TRUTH TABLE on page for more information. Channel is selected if both pins are left floating. At a single V supply, the CMIR becomes.9v to.v. The same theory can be applied to the V OUT range. Driving Video The FHP9 is designed to drive high-speed video. 9MHz.dB bandwidth at V pp output,. /.% differential gain/phase, and ±7mA output current make the FHP9 suitable for driving standard-definition, highdefinition, or PC graphics video. Driving Video with a Single V Supply The FHP9 drives video signals from a single V supply at G = only. At higher gains, the CMIR and V o range is not suitable for passing video without clipping the signal. Driving Capacitive Loads The FREQUENCY RESPONSE VS. C L plot in Figure, illustrates the response of the FHP9. A small series resistance (R s ) at the output of the amplifier, illustrated in Figure, improves stability and settling performance. R s values in the FREQUENCY RESPONSE VS. C L plot were chosen to achieve maximum bandwidth with less than db of peaking. For maximum flatness, use a larger R s. R g + - R f R s C L R L EN, SD The FHP9 offers both shutdown and disable capability. The EN (enable) pin is active low. During disable mode (EN = ), only the output amplifier is disabled, reducing output glitches and allowing for multiplexer expansion. The FHP9 is enabled when the EN pin is left floating or grounded. The SD (shutdown) pin is active high. During shutdown (SD = ), the FHP9 consumes only.ma of supply current. The FHP9 is enabled when the SD pin is left floating or grounded. Supply Voltage The FHP9 operates from a single supply of V to V or dual supplies of ±.V to ±.V. For low supply voltage operation, ensure that the common mode input voltage range (CMIR) or output voltage range (V o ) are not exceeded. Exceeding the CMIR or V o range puts the FHP9 into an overdrive condition. For example, the typical CMIR for the FHP9 is ±.V at ±V supply, which means.9v of headroom is required from each supply. Figure. Typical Topology for Driving Capacitive Loads Power Dissipation The maximum internal power dissipation allowed is directly related to the maximum junction temperature. If the maximum junction temperature exceeds C for an extended time, device failure may occur. The FHP9 is short-circuit protected; however, this may not guarantee that the maximum junction temperature (+ C) is not exceeded under all conditions. RMS power dissipation can be calculated using the following equation: Power Dissipation = I s * (V s+ - V s- ) + (V s+ - V o(rms) ) * I OUT(RMS) where I s is the supply current, V s+ is the positive supply pin voltage, V s- is the negative supply pin voltage, V o(rms) is the RMS output voltage, and I OUT(RMS) is the RMS output current delivered to the load. Follow the maximum power derating curves shown in Figure to ensure proper operation. Fairchild Semiconductor Corporation FHP9 Rev...

13 Maximum Power Dissipation (W) SOIC- TSSOP- - Ambient Temperature ( C) Figure. Maximum Power Derating Overdrive Recovery For an amplifier, an overdrive condition occurs when the output and/or input ranges are exceeded. The recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. The FHP9 typically recovers in less than 7ns from an overdrive condition. Figure shows the FHP9 in an overdriven condition. Amplitude (V) Output Pos_AV+ Input Pos_V pp Input Neg_V pp Output Neg_AV Time (µs) Figure. Overdrive Recovery Layout Considerations General layout and supply bypassing play major roles in high-frequency performance. Fairchild has evaluation boards to use as a guide for high-frequency layout and as aid in device testing and characterization. Follow the guidelines below as a basis for high-frequency layout: Include.µF and.µf ceramic capacitors. Place the.µf capacitor within.7 inches of the power pin. Place the.µf capacitor within. inches of the power pin. Remove the ground plane under and around the part, especially near the input and output pins and under R f and R g, to reduce parasitic capacitance. Minimize all trace lengths to reduce series inductances. For current feedback amplifiers, stray capacitance from the inverting input (pin ) to ground or to the output (pin ) increases peaking in the AC response. For optimum performance, place R f and R g as close to the FHP9 as possible. Small-size surface-mount resistors are recommended. Avoid the use of vias near the device; vias add unwanted inductance. If traces of greater than one inch are required, use stripline or microstrip techniques designed with characteristic impedances of Ω or that are properly terminated with impedance-matching elements at each end. Refer to the evaluation board layouts for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board KEB KEB Products FHP9IMX FHP9IMTCX Fairchild Semiconductor Corporation FHP9 Rev...

14 Figure. KEB Top-Side Figure. KEB Top-Side Figure 7. KEB Bottom-Side Figure 9. KEB Bottom-Side V CC R- C.µF IN - + C.µF OUT + - IN IN R- R- C -.µf C.µF 7 FHP9 NI VS+ GND OUT NI VINV GND SD NI EN VEE A NI A R- 9 R R OUT RF A RG R Ω SD EN V EE PWR IN Ω R Ω R Ω A *Choose R-, R-, R-, R-, and R OUT for proper impedance matching. R, R, R, and R are optional. Figure. FHP9 Schematic Diagram Fairchild Semiconductor Corporation FHP9 Rev...

15 Mechanical Dimensions Figure. SOIC- Package Fairchild Semiconductor Corporation FHP9 Rev...

16 Mechanical Dimensions Figure. TSSOP- Package Fairchild Semiconductor Corporation FHP9 Rev...

17 Rev. I Fairchild Semiconductor Corporation

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