DATASHEET EL9200, EL9201, EL9202. Features. Typical Block Diagram. Applications. Pinouts. Programmable VCOM. FN7438 Rev 1.

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1 DATASHEET EL92, EL92, EL922 Programmable VCOM FN748 Rev. The EL92, EL92, and EL922 represent programmable V COM amplifiers for use in TFT-LCD displays. Featuring, 2, and 4 channels of V COM amplification, respectively, each device features just a single programmable current source for adding offset to one V COM output. This current source is programmable using a single wire interface to one of 28 levels. The value is stored on an internal EEPROM memory. The EL92 is available in the 2 LD DFN package and the EL92 and EL922 are available in 24 LD QFN packages. All are specified for operation over the -4 C to +8 C temperature range. V SD Typical Block Diagram CE V S + EEPROM INN - + R F V OUT INP R G R R 2 Features 28 Step Adjustable Sink Current EEPROM Memory 2-pin Adjustment and Disable Single, Dual or Quad Amplifiers - 44MHz Bandwidth - 8V/µs Slew Rate - 6mA Continuous Output - 8mA Peak Output Up to 8V Operation 2.6V to.6vlogic Control Pb-free Available (RoHS compliant) Applications TFT-LCD V COM Supplies For - LCD-TVs - LCD Monitors CTL CONTROL UP/DOWN COUNTER ANALOG POT I OUT SET R SET Pinouts EL92 (2 LD DFN) TOP VIEW EL92 (24 LD QFN) TOP VIEW EL922 (24 LD QFN) TOP VIEW THERMAL PAD 2 VS+ VOUTA SET 9 CE 8 CTL 7 VSD VINB+ IOUT AVDD VINA- VINA+ IOUT AVDD 9 8 VOUTA 7 VS+ 6 VOUTB VINB- 4 SET CE VSD CTL VINA+ VINA- THERMAL PAD VOUTA VOUTD VIND- VIND+ AVDD CTL 9 VOUTB 8 VOUTC 7 VI- 6 VI+ 4 AVDD VINA+ VS+ VINB+ VINA- VINB- THERMAL PAD CE SET IOUT FN748 Rev. Page of

2 Ordering Information PART NUMBER PART MARKING TEMP RANGE ( C) PACKAGE PKG. DWG. # EL92IL 92IL -4 to +8 2 LD DFN L2.4x4B EL92IL-T7* 92IL -4 to +8 2 LD DFN L2.4x4B EL92IL-T* 92IL -4 to +8 2 LD DFN L2.4x4B EL92ILZ (Note) 92ILZ -4 to +8 2 LD DFN EL92ILZ-T7* (Note) 92ILZ -4 to +8 2 LD DFN EL92ILZ-T* (Note) 92ILZ -4 to +8 2 LD DFN L2.4x4B L2.4x4B L2.4x4B EL92IL 92IL -4 to LD QFN MDP46 EL92IL-T7* 92IL -4 to LD QFN MDP46 EL92IL-T* 92IL -4 to LD QFN MDP46 EL92ILZ ( Note) 922ILZ -4 to LD QFN EL92ILZ-T7* ( Note) 922ILZ -4 to LD QFN EL92ILZ-T* (Note) 922ILZ -4 to LD QFN MDP46 MDP46 MDP46 EL922IL 922IL -4 to LD QFN MDP46 EL922IL-T7* 922IL -4 to LD QFN MDP46 EL922IL-T* 922IL -4 to LD QFN MDP46 EL922ILZ (Note) 922ILZ -4 to LD QFN MDP46 EL922ILZ-T7* (Note) 922ILZ -4 to LD QFN MDP46 EL922ILZ-T* (Note) 922ILZ -4 to LD QFN MDP46 *Add -T suffix for tape and reel *Please refer to TB47 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. FN748 Rev. Page 2 of

3 Absolute Maximum Ratings (T A = +2 C) V S + Supply Voltage between V S + and v Supply Voltage between V SD and v Maximum Continuous Output Current mA Input Voltages to SET, CE V to +4V CTL V to +6V Output Voltages to OUT V to +2V V to +2V ESD Rating Human Body Model kV Thermal Information Maximum Die Temperature C Storage Temperature C to + C Pb-Free Reflow Profile see link below Operating Conditions Ambient Operating Temperature C to +8 C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V SD = V, V S + = V, = V, R SET = 24.9k, and T A = +2 C unless otherwise specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT V S+ Supply Voltage V I S+ Quiescent Current EL ma EL ma EL ma V SD Logic Supply Voltage For programming.6 V For operation V I SD Quiescent Logic Current CE =.6V µa CE = 2 µa Program (charge pump current) (Note ) 2 ma Read (Note ) ma I ADD Supply Current (Note 2) 2 µa CTL IH CTL High Voltage 2.6V < V SD <.6V.7*V SD.8*V SD V CTL IL CTL Low Voltage 2.6V < V SD <.6V.2*V SD.*V SD V CTL IHRPW CTL High Rejected Pulse Width 2 µs CTL ILRPW CTL Low Rejected Pulse Width 2 µs CTL IHMPW CTL High Minimum Pulse Width 2 µs CTL ILMPW CTL Low Minimum Pulse Width 2 µs CTL MTC CTL Minimum Time Between Counts µs ICTL CTL Input Current CTL = µa CTL = V SD µa CTL CAP CTL Input Capacitance pf CE IL CE Input Low Voltage 2.6V < V SD <.6V.4 V CE IH CE Input High Voltage 2.6V < V SD <.6V.6 V CE ST CE Minimum Start-Up Time (Note ) ms CTL PROM CTL EEPROM Program Voltage 2.6V < V SD <.6V (Note 2) V CTL PT CTL EEPROM Programming Signal Time > 4.9V 2 µs P T Programming Time ms EE WC EE Write Cycles (Note ) cycles FN748 Rev. Page of

4 Electrical Specifications V SD = V, V S + = V, = V, R SET = 24.9k, and T A = +2 C unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT SET DN SET Differential Nonlinearity Monotonic over-temperature ± LSB SET ZSE SET Zero-Scale Error (Note ) ±2 LSB SET FSE SET Full-Scale Error (Note ) ±8 LSB I SET SET Current Through R SET (Note ) 2 µa SET ER SET External Resistance To, = 2V (Note ) 2 k To, = 4.V (Note ) k to SET to SET Voltage Attenuation :2 V/V OUT ST OUT Settling Time To ±. LSB error band (Note ) 2 µs V OUT OUT Voltage Range (Note ) V SET +.V V OUT VD OUT Voltage Drift (Note ) mv AMPLIFIER CHARACTERISTICS INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = V mv TCV OS Average Offset Voltage Drift (Note ) 7 µv/ C I B Input Bias Current V CM = V 2 6 na R IN Input Impedance G C IN Input Capacitance 2 pf CMRR Common-Mode Rejection Ratio For V IN from -.V to +.V 7 db A VOL Open-Loop Gain -4.V V OUT +4.V 6 7 db OUTPUT CHARACTERISTICS V OL Output Swing Low R L =.k to.9. V V OH Output Swing High V I SC Short-Circuit Current ± ±8 ma I OUT Output Current ±6 ma POWER SUPPLY PERFORMAE PSRR Power Supply Rejection Ratio V S+ is moved from 4.V to.v 8 db DYNAMIC PERFORMAE SR Slew Rate (Note 4) -4.V V OUT 4.V, 2% to 8% 6 8 V/µs t S Settling to +.% (A V = +) (A V = +), V OUT = 2V step 8 ns BW -db Bandwidth 44 MHz GBWP Gain-Bandwidth Product 2 MHz PM Phase Margin CS Channel Separation f = MHz (EL92 and EL922 only) db d G Differential Gain (Note ) R F = R G = k and V OUT =.4V.7 % d P Differential Phase (Note ) R F = R G = k and V OUT =.4V.24 NOTES:. Simulated and determined via design and not directly tested 2. Tested at = 2V. Wafer sort only 4. NTSC signal generator used. Limits established by characterization and are not production tested. FN748 Rev. Page 4 of

5 Pin Descriptions PIN IN/OUT DESCRIPTION EQUIVALENT CIRCUIT VINx- Input Amplifier x inverting input, where: x = A for EL92 x = A, B for EL92 x = A, B, C, D for EL922 V S+ CIRCUIT VINx+ Input Amplifier x non-inverting input, where: x = A for EL92 x = A, B for EL92 x = A, B, C, D for EL922 Reference Circuit VS+ Supply Op amp supply; bypass to with.µf capacitor VOUTX Output Amplifier X output, where: x = A for EL92 x = A, B for EL92 x = A, B, C, D for EL922 V S+ CIRCUIT 2 - No connect; not internally connected Supply Ground connection IOUT Output Adjustable sink current output pin; the current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 28; see SET pin function description for the maxim adjustable sink current setting SET Output Maximum sink current adjustment point; connect a resistor from SET to to set the maximum adjustable sink current of the OUT pin; the maximum adjustable sink current is equal to ( /2) divided by R SET CE Input Counter enable pin; connect CE to V DD to enable counting of the internal counter; connect CE to to inhibit counting CTL Input Internal counter up/down control and internal EEPROM programming control input; if CE is high, a mid-to-low transition increments the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT; a mid-to-high transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage at OUT; applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter; see EEPROM Programming section for details AVDD Supply Analog voltage supply; bypass to with.µf capacitor VSD Supply System power supply input; bypass to with.µf capacitor FN748 Rev. Page of

6 Amplifier Typical Performance Curves QUANTITY (AMPLIFIERS) 4 2 T A = +2 C TYPICAL PRODUCTION DISTRIBUTION INPUT BIAS CURRENT (µa) INPUT OFFSET VOLTAGE (mv) TEMPERATURE ( C) FIGURE. INPUT OFFSET VOLTAGE DISTRIBUTION FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE QUANTITY (AMPLIFIERS) 2 2. TYPICAL PRODUCTION DISTRIBUTION OUTPUT HIGH VOLTAGE (V) I OUT = ma INPUT OFFSET VOLTAGE DRIFT, TCV OS (µv/ C) FIGURE. INPUT OFFSET VOLTAGE DRIFT TEMPERATURE ( C) FIGURE 4. OUTPUT HIGH VOLTAGE vs TEMPERATURE INPUT OFFSET VOLTAGE (mv) OUTPUT LOW VOLTAGE (V) I OUT = ma TEMPERATURE ( C) FIGURE. INPUT OFFSET VOLTAGE vs TEMPERATURE TEMPERATURE ( C) FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE FN748 Rev. Page 6 of

7 Amplifier Typical Performance Curves (Continued) OPEN-LOOP GAIN (db) V S = ±V SLEW RATE (V/µs) V S = ±V TEMPERATURE ( C) FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE TEMPERATURE ( C) FIGURE 8. SLEW RATE vs TEMPERATURE DIFFERENTIAL GAIN (%) A V = 2 DIFFERENTIAL PHASE ( ) IRE FIGURE 9. DIFFERENTIAL GAIN 2 IRE FIGURE. DIFFERENTIAL PHASE DISTORTION (db) A V = 2 FREQ = MHz 2nd HD rd HD GAIN (db) GAIN PHASE PHASE ( ) V OP-P (V) FIGURE. HARMONIC DISTORTION vs V OP-P -2 - k k k M M M FREQUEY (Hz) FIGURE 2. OPEN LOOP GAIN AND PHASE FN748 Rev. Page 7 of

8 Amplifier Typical Performance Curves (Continued) MAGNITUDE (NORMALIZED) (db) - A V = C LOAD = pf k A V = - -2 k M M M k MAGNITUDE (NORMALIZED) (db) 2 - pf M pf 47pF pf M M FREQUEY (Hz) FREQUEY (Hz) FIGURE. FREQUEY RESPONSE FOR VARIOUS R L FIGURE 4. FREQUEY RESPONSE FOR VARIOUS C L 4 2 OUTPUT IMPEDAE ( ) 2 2 k k M M M MAXIMUM OUTPUT SWING (V P-P ) A V = DISTORTION <% k k M M M FREQUEY (Hz) FIGURE. CLOSED LOOP OUTPUT IMPEDAE FREQUEY (Hz) FIGURE 6. MAXIMUM OUTPUT SWING vs FREQUEY PSRR+ PSRR- T A = +2 C CMRR (db) - -4 PSRR (db) k k k M M M k k k M M FREQUEY (Hz) FIGURE 7. CMRR FREQUEY (Hz) FIGURE 8. PSRR FN748 Rev. Page 8 of

9 Amplifier Typical Performance Curves (Continued) VOLTAGE NOISE (nv/ Hz) k -4 R L =k A V = V IN = mv RMS -6 k k k M M M k k k M M M XTALK (db) DUAL MEASURED CH A TO B QUAD MEASURED CH A TO D OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION FREQUEY (Hz) FIGURE 9. INPUT VOLTAGE NOISE SPECTRAL DENSITY FREQUEY (Hz) FIGURE 2. CHANNEL SEPARATION OVERSHOOT (%) A V = V IN = mv T A = +2 C STEP SIZE (V) - - A V =.%.% k LOAD CAPACITAE (pf) FIGURE 2. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITAE SETTLING TIME (ns) FIGURE 22. SETTLING TIME vs STEP SIZE V S = ±V T A = +2 C A V = V S = ±V T A = +2 C A V = mv STEP V STEP ns/div FIGURE 2. LARGE SIGNAL TRANSIENT RESPONSE ns/div FIGURE 24. SMALL SIGNAL TRANSIENT RESPONSE FN748 Rev. Page 9 of

10 Amplifier Typical Performance Curves (Continued) JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD- 4. JEDEC JESD- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.2 POWER DISSIPATION (W) W QFN24 JA = 7 C/W POWER DISSIPATION (W) mW QFN24 JA = 4 C/W AMBIENT TEMPERATURE ( C) FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Application Information This device provides the ability to reduce the flicker of an LCD panel by adjustment of the V COM voltage during production test and alignment. A 28-step resolution is provided under digital control which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. The adjustment of the output and the programming of the non-volatile memory are provided on one pin while the counter enable (CE) is provided on a separate pin. The output is adjusted via the CTL pin either by counting up with a mid to low transition or by counting down with a mid to high transition. Once the minimum or maximum value is reached on the 28 steps, the device will not overflow or underflow beyond that minimum or maximum value. An increment of the counter will increase the output sink current which will lower the voltage on the external voltage divider. A decrement of the counter will decrease the output sink current, which will raise the voltage on the external voltage divider. Once the desired output level is obtained, the part can store it's setting using the non-volatile memory in the device. See the Non-Volatile Memory (EEPROM) Programming on page 2 for detailed information. Note: Once the desired output level is stored in the EEPROM, the CE pin must go low to preserve the stored value. Adjustable Sink Current Output The device provides an output sink current which lowers the voltage on the external voltage divider. The equations that control the output are given in Equation : Setting A I OUT VDD = R SET R 2 V OUT VAVDD R + R 2 Setting R = 2 R SET NOTE: Where setting is an integer between and Bit Up/Down Counter (EQ. ) The counter sets the level to the digital potentiometer and is connected to the non-volatile memory. When the part is programmed, the counter setting is loaded into the non-volatile memory. This value will be loaded from the non-volatile memory into the counter during power-on. The counter will not exceed its maximum level and will hold that value during subsequent increment requests on the CTL pin. The counter will not exceed its minimum level and will hold that value during subsequent decrement requests on the CTL pin. CTL Pin CTL should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the CE pin is high. The board should have an additional ESD protection circuit, with a series k resistor and a shunt.µf capacitor connected on the CTL pin. In order to increment the setting, pulse CTL low for more than 2µs. The output sink current increases and lowers the V COM lever by one least-significant bit (LSB). On the other hand, to decrement the setting, pulse CTL high for FN748 Rev. Page of

11 more than 2µs. The output sink current will decrease and the V COM level will increase by one LSB. To avoid unintentional adjustment, the EL92, EL92, and EL922 guarantees to reject CTL pulses shorter than 2µs. Since the internal comparators come up in an unknown state, the very first CTL pulse is ignored to avoid the possibility of a false pulse. See Figure 27 for the timing information. TABLE. TRUTH TABLE INPUT OUTPUT CTL CE V DD SET I CC MEMORY Mid to Hi Hi V DD Decrement Normal X Mid to Lo Hi V DD Increment Normal X X Lo V DD No Change Lower X > 4.9V X V DD No Change Increased Program X X to V DD Read Increased Read NOTE: CE should be disabled (pulled low) before powering down the device to assure that the glitches and transients will not cause unwanted EEPROM overwriting. CTL MTC CTL IHRPW CTL HIGH CTL V DD /2 CTL LOW CTL IHMPW CTL ILMPW CTL ILRPW CE COUNTER OUTPUT UNDEF A 7B 7A V COM FIGURE 27. V COM ADJUSTMENT FN748 Rev. Page of

12 Non-Volatile Memory (EEPROM) Programming When the CTL pin exceeds 4.9V, the non-volatile programming cycle will be activated. The CTL signal needs to remain above 4.9V for more than 2µs. The level and timing needed to program the non-volatile memory is given below. It then takes a maximum of ms for the programming to be completed inside the device (see P T specification in Table Electrical Specifications on page. 4.9V CTL VOLTAGE CTL PT FIGURE 28. EEPROM PROGRAMMING Amplifiers Operating Voltage, Input, and Output The amplifiers are specified with a single nominal supply voltage from V to V or a split supply with its total range from V to V. Correct operation is guaranteed for a supply range of 4.V to 6.V. Most amplifier specifications are stable over both the full supply range and operating temperatures of -4 C to +8 C. Parameter variations with operating voltage and/or temperature are shown in the See Amplifier Typical Performance Curves on page 6. The input common-mode voltage range of the amplifiers extends mv beyond the supply rails. The output swings of the those typically extend to within mv of positive and negative supply rails with load currents of ma. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 27 shows the input and output waveforms for the device in the unity-gain configuration. Operation is from V supply with a k load connected to. The input is a V P-P sinusoid. The output voltage is approximately 9.8V P-P. V µs V A V = T A = +2 C V IN = V P-P TIME OUTPUT INPUT Short-Circuit Current Limit The amplifiers will limit the short circuit current to ±8mA if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±6mA. This limit is set by the design of the internal metal interconnects. Output Phase Reversal The amplifiers are immune to phase reversal as long as the input voltage is limited from V S - -.V to V S + +.V. Figure 28 shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than.6v, electrostatic protection diodes placed in the input stage of the device begin to conduct and over-voltage damage could occur. V µs V V S = 2.V A V = T A = +2 C V IN = 6V P-P FIGURE. OPERATION WITH BEYOND-THE-RAILS INPUT Unused Amplifiers It is recommended that any unused amplifiers in a dual and a quad package be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground plane. Power Supply Bypassing and Printed Circuit Board Layout The amplifiers can provide gain at high frequency. As with any high-frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal operation, a.µf ceramic capacitor should be placed from V S to pin to. A 4.7µF tantalum capacitor should then be connected in parallel, placed in the region of the amplifier. FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND OUTPUT FN748 Rev. Page 2 of

13 Replacing Existing Mechanical Potentiometer Circuits Figures 29 and show the common adjustment mechanical circuits and equivalent replacement with the EL92x. R F R G R A IN- R B R C - + V COM SET EL92 V OUT IN+ OUT R R 2 V COM R SET R = R A R 2 = R B + R C R A R B + R C R SET = R B FIGURE. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING EL92 R F R G R X IN- R Y R Z - + V COM SET EL92 V OUT IN+ OUT R R 2 V COM R SET R = R 2 = R X R Z R X R X + R Y + R Z R SET = R Y FIGURE 2. EXAMPLE OF THE REPLACEMENT FOR THE MECHANICAL POTENTIOMETER CIRCUIT USING THE EL92 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN748 Rev. Page of

14 QFN (Quad Flat No-Lead) Package Family A 2X.7 C (E2) C 2 SEATING PLANE N LEADS L N (N-) (N-2) b (N/2) e PIN # I.D. MARK TOP VIEW (N/2). M C A B (N-2) (N-) N BOTTOM VIEW A DETAIL X 2. C.8 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW C A (c) D (D2) 2 7 (L) NE N LEADS E B 2X.7 C PIN # I.D. MDP46 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-22) MILLIMETERS SYMBOL QFN44 QFN8 QFN2 TOLERAE NOTES A ±. - A /-.2 - b ±.2 - c Reference - D Basic - D /2.48 Reference 8 E Basic - E /.4 Reference 8 e...8. Basic - L..4.. ±. - N Reference 4 ND Reference 6 NE Reference MILLIMETERS TOLER- SYMBOL QFN28 QFN24 QFN2 QFN6 AE NOTES A ±. - A / b ±.2 - c Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ±. - N Reference 4 ND 6 4 Reference 6 NE Reference Rev 2/7 NOTES:. Dimensioning and tolerancing per ASME Y4.M Tiebar view shown is a non-functional feature.. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN748 Rev. Page 4 of

15 Package Outline Drawing L2.4x4B 2 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev, 6/ A 2X 2. 6 PIN INDEX AREA B PIN # INDEX AREA 6 X. 6 2 X (4X). TOP VIEW 2 BOTTOM VIEW 7 4. M C AB 2 x.2 SEE DETAIL "X" (.2).9 MAX. C SEATING PLANE.8 C C SIDE VIEW.6 ( 2.4 ) C.2 REF 2 X.7 ( 2X.2 ). MIN.. MAX. ( X. ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y4.m-994. Unless otherwise specified, tolerance : Decimal ±. Dimension b applies to the metallized terminal and is measured between.mm and.mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. FN748 Rev. Page of