High Speed, +5 V, 0.1 µf CMOS RS-232 Drivers/Receivers ADM222/ADM232A/ADM242*

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1 a FEATURES 00 kb/s Transmission Rate Small (0. µf) Charge Pump Capacitors Single V Power Supply Meets All EIA--E and V. Specifications Two Drivers and Two Receivers On-Board DC-DC Converters ± V Output Swing with + V Supply ±0 V Receiver Input Levels Pin Compatible with MAX/MAXA/MAX APPLICATIONS Computers Peripherals Modems Printers Instruments GENERAL DESCRIPTION The ADM, ADMA, ADM are a family of high speed RS- line drivers/receivers offering transmission rates up to 00 kb/s. Operating from a single + V power supply, a highly efficient on-chip charge pump using small (0. µf) external capacitors allows RS- bipolar levels to be developed. Two RS- drivers and two RS- receivers are provided on each device. The devices are fabricated on BiCMOS, an advanced mixed technology process which combines low power CMOS with high speed bipolar circuitry. This allows for transmission rates up to 00 kb/s yet minimizes the quiescent power supply current to under ma. The ADMA is a pin-compatible, high speed upgrade for the AD and for the ADML. It is available in -pin DIP and in both narrow and wide surface mount (SOIC) packages. The ADM contains an additional shutdown () function which may be used to disable the device thereby reducing the supply current to 0. µa. During shutdown, all transmit/ receive functions are disabled. The ADM is available in -pin DIP and in a wide surface mount (SOIC) package. The ADM combines both shutdown () and enable (EN) functions. The shutdown function reduces the supply curent to 0. ma. During shutdown, the transmitters are disabled but the receivers continue to operate normally. The enable function allows the receiver outputs to be disabled thereby facilitating sharing a common bus. The ADM is available in -pin DIP and in a wide surface mount (SOIC) package. High Speed, + V, 0. µf CMOS RS- Drivers/Receivers ADM/ADMA/ADM* INPUTS* FUNCTIONAL BLOCK DIAGRAM T IN T IN R OUT + TO +V VOLTAGE DOUBLER C C+ + TO V VOLTAGE INVERTER C ADMxx ORDERING GUIDE * INTERNAL 00kΩ PULL-UP RESISTOR ON EACH TTL/MOS INPUT ** INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT Model Temperature Range Package Option ADMAN 0 C to + C N- ADMAR 0 C to + C R-W ADMAAN 0 C to + C N- ADMAARN 0 C to + C R-N ADMAARW 0 C to + C R-W ADMAN 0 C to + C N- ADMAR 0 C to + C R-W T T R R + INPUT EN T OUT T OUT R IN R IN RS- RS- INPUTS** (ADM) (ADM, ADM) *Protected by U.S. Patent No.,,0. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box, Norwood. MA 00-, U.S.A. Tel: /-00 Fax: /-0

2 ADM/ADMA/ADM SPECIFICATIONS (= + V ± %, C C = 0. µf; all specifications T MIN to T MAX unless otherwise noted.) Parameter Min Typ Max Units Test Conditions/Comments RS- TRANSMITTERS Output Voltage Swing ± ± V All Transmitter Outputs Loaded with kω to Ground Input Logic Threshold Low, V INL. 0. V T IN Input Logic Threshold High, V INH.0. V T IN Logic Pullup Current 0 µa T IN = 0 V Data Rate 00 kb/s Output Resistance 00 Ω = = = 0 V, V OUT = ± V Output Short Circuit Current (Instantaneous) ± ± ma RS- RECEIVERS RS- Input Voltage Range 0 +0 V RS- Input Threshold Low 0.. V RS- Input Threshold High.. V RS- Input Hysteresis V = V RS- Input Resistance kω Output Voltage Low, V OL V I OUT =. ma Output Voltage High, V OH. V I OUT =.0 ma Output Short-Circuit Current ma Source Current (V OUT = ) Output Short-Circuit Current 0 ma Sink Current (V OUT = ) Output Leakage Current ±0.0 ± µa = /EN = 0 V V OUT EN Input Threshold Low, V INL. 0. V EN Input Threshold High, V INH.0. V POWER SUPPLY Power Supply Current ma No Load ma kω Load on Both Outputs Shutdown Power Supply Current 0. µa Input Leakage Current ± µa Input Threshold Low, V INL. 0. V Input Threshold High, V INH.0. V AC CHARACTERISTICS Transition Region Slew Rate 0 V/µs C L = 0 pf to 00 pf, R L = kω to k Ω Measured from + V to V or V to + V Transmitter Propagation Delay TTL to RS- 0.. µs t PHLT 0.. µs t PLHT Receiver Propagation Delay RS- to TTL µs t PHLR µs t PLHR Receiver Output Enable Time 00 ns t ER Receiver Output Disable Time 0 00 ns t DR Transmitter Output Enable Time 0 µs Goes high Transmitter Output Disable Time. µs Goes low Transmitter + to Propagation Delay Difference 00 ns Receiver + to Propagation Delay Difference 0 ns Specifications subject to change without notice. REV. 0

3 ADM/ADMA/ADM ABSOLUTE MAXIMUM RATINGS * (T A = + C unless otherwise noted) V ( 0. V) to + V V to V Input Voltages T IN V to ( + 0. V) R IN ±0 V Output Voltages T OUT (, +0. V) to (, 0. V) R OUT V to ( + 0. V) Short Circuit Duration T OUT Continuous Power Dissipation N mw (Derate. mw/ C above +0 C) θ JA, Thermal Impedance C/W Power Dissipation R-N mw (Derate mw/ C above +0 C) θ JA, Thermal Impedance C/W Power Dissipation R-W mw (Derate mw/ C above +0 C) θ JA, Thermal Impedance C/W Power Dissipation N mw (Derate mw/ C above +0 C) θ JA, Thermal Impedance C/W Power Dissipation R-W mw (Derate mw/ C above +0 C) θ JA, Thermal Impedance C/W Operating Temperature Range Industrial (A Version) C to + C Storage Temperature Range C to +0 C Lead Temperature (Soldering, sec) C Vapor Phase (0 sec) C Infrared ( sec) C *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Test Circuits +V +V V IN V IN 0V t PLHT t PHLT t PHLR t PLHR V OUT 0V V OUT 0% Figure. Transmitter Propagation Delay Timing Figure. Receiver Propagation Delay Timing EN INPUT +V 0V EN INPUT V 0V t ER t DR +. V OH V OH 0. RECEIVER OUTPUT RECEIVER OUTPUT +0.V V OL + 0. V OL Figure. Receiver Enable Timing Figure. Receiver Disable Timing REV. 0

4 ADM/ADMA/ADM PIN FUNCTION DESCRIPTION V IN Figure. Shutdown Test Circuit INPUT V 0V TRANSMITTER OUTPUT kω t DT + 0pF V OUT Figure. Transmitter Shutdown Disable Timing C C + INPUT C.V V CC + TO +V VOLTAGE DOUBLER C C+ + TO V VOLTAGE INVERTER C C C Mnemonic Function Power Supply Input, + V ± %. Internally generated positive supply (+ V nominal). Internally generated negative supply ( V nominal). Ground Pin. Must be connected to 0 V. External capacitor, (+ terminal) is connected to this pin. C External capacitor, ( terminal) is connected to this pin. C+ External capacitor, (+ terminal) is connected to this pin. C External capacitor, ( terminal) is connected to this pin. T IN Transmitter (Driver) Inputs. These inputs accept levels. An internal 00 kω pull-up resistor to is connected on each input. T OUT Transmitter (Driver) Outputs. These are RS- levels (typically ± V). R IN Receiver Inputs. These inputs accept RS- signal levels. An internal kω pull-down resistor to is connected on each of these inputs. R OUT Receiver Outputs. These are levels. NC No Connect. No connections are required to this pin. EN (ADM Only) Active Low Digital Input. May be used to enable or disable (three-state) both receiver outputs. (ADM & ADM) Active Low Digital Input. May be used to disable the device so that the power consumption is minimized. On the ADM all drivers and receivers are disabled. On the ADM the drivers are disabled but the receivers remain enabled. INPUTS* T IN T IN R OUT ADM T T R R T OUT T OUT R IN R IN RS- RS- INPUTS** NC C ADM T OUT C+ C TOP VIEW (Not to Scale) R IN T IN * INTERNAL 00kΩ PULL-UP RESISTOR ON EACH TTL/MOS INPUT ** INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT T OUT R IN NC = NO CONNECT T IN R OUT Figure. ADM Typical Operating Circuit Figure. ADM DIP & SOIC Pin Configurations REV. 0

5 ADM/ADMA/ADM EN C C+ C ADMA TOP VIEW (Not to Scale) T OUT R IN T IN C C+ C ADM TOP VIEW (Not to Scale) T OUT R IN T IN T OUT T IN T OUT T IN R IN R OUT R IN R OUT Figure. ADMA DIP/SOIC Pin Configuration Figure. ADM DIP/SOIC Pin Configuration C C C.V + INPUT + TO +V C VOLTAGE DOUBLER C+ + TO V VOLTAGE INVERTER C C C C C C.V + INPUT + TO +V VOLTAGE DOUBLER C C+ + TO V VOLTAGE INVERTER C C C INPUTS* T IN T IN T T T OUT T OUT RS- INPUTS* T IN T IN T T T OUT T OUT RS- R OUT R R ADMA R IN R IN RS- INPUTS** * R OUT EN R R ADM R IN R IN RS- INPUTS** * INTERNAL 00kΩ PULL-UP RESISTOR ON EACH TTL/MOS INPUT ** INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT * INTERNAL 00kΩ PULL-UP RESISTOR ON EACH TTL/MOS INPUT ** INTERNAL kω PULL-DOWN RESISTOR ON EACH RS- INPUT Figure. ADMA Typical Operating Circuit Figure. ADM Typical Operating Circuit REV. 0

6 TRANSMITTER OUTPUT VOLTAGE V, ( ) V ADM/ADMA/ADM Typical Performance Characteristics = ± T A = + C = ± T A = + C TOUT V T OUT LOW T OUT HIGH 0 0 I+, ( I ) ma 0 0 I OUT ma Figure. Charge Pump, vs. Current Figure. Transmitter Output Voltage vs. Current 0kB 0kB A 0.0V 0kB kB = + T A = + C TX = +; TX = 0V SQUARE WAVE BOTH TX LOADED WITH k//cl LOAD CAPACITANCE pf 00kB 00kB 000 0% 0µs Figure. Transmitter Baud Rate vs. Load Capacitance Figure. Charge Pump, Exiting Shutdown A.V A 0. V % 0% µs µs Figure. Transmitter Unloaded Slew Rate Figure. Transmitter Fully Loaded Slew Rate REV. 0

7 ADM/ADMA/ADM GENERAL INFORMATION The ADM/ADMA/ADM are high speed RS- drivers/receivers requiring a single digital + V supply. The RS- standard requires transmitters that will deliver ± V minimum on the transmission channel and receivers that can accept signal levels down to ± V. The parts achieve this by integrating step up voltage converters and level shifting transmitters and receivers onto the same chip. CMOS technology is used to keep the power dissipation to an absolute minimum. All devices contains an internal charge pump voltage doubler and a voltage inverter that generates ± V from the + V input. Four external 0. µf capacitors are required for the internal charge pump voltage converter. The ADM/ADMA/ADM is a modification, enhancement and improvement to the AD0-AD family and derivatives thereof. It is essentially plug-in compatible and does not have materially different applications. CIRCUIT DESCRIPTION The internal circuitry consists of four main sections. These are: A Charge Pump Voltage Converter to RS- Transmitters RS- to Receivers Enable and Shutdown Functions. Charge Pump DC-DC Voltage Converter The Charge Pump Voltage converter consists of an oscillator and a switching matrix. The converter generates a ± V supply from the input V level. This is done in two stages using a switched capacitor technique. The V input supply is doubled to V using capacitor C as the charge storage element. The V level is also generated from the input V supply using C and C as the storage elements. Capacitors C and C are used to reduce the output ripple. Their values are not critical and can be reduced if higher levels of ripple are acceptable. The charge pump capacitors C and C may also be reduced at the expense of higher output impedance on the and supplies. The and supplies may also be used to power external circuitry if the current requirements are small. Please refer to the typical performance characteristics which shows the, output voltage vs. current. In the shutdown mode the charge pump is disabled and decays to while decays to 0 V. Transmitter (Driver) Section The Drivers convert input levels into RS- output levels. With = + V and driving a typical RS- load, the output voltage swing is ± V. Even under worst case conditions the drivers are guaranteed to meet the ± V RS- minimum requirement. The input threshold levels are both TTL and CMOS compatible with the switching threshold set at /. With a nominal = V the switching threshold is. V typical. Unused inputs may be left unconnected, as an internal 00 kω pull- up resistor pulls them high forcing the outputs into a low state. As required by the RS- standard, the slew rate is limited to less than 0 V/µs without the need for an external slew limiting capacitor, and the output impedance in the power-off state is greater than 00 Ω. Receiver Section The receivers are inverting level shifters which accept RS- input levels (± V to ± V) and translate them into V TTL/ CMOS levels. The inputs have internal kω pull-down resistors to ground and are also protected against overvoltages of up to ±0 V. The guaranteed switching thresholds are 0. V minimum and. V maximum which are well within the ± V RS- requirement. The low level threshold is deliberately positive as it ensures that an unconnected input will be interpreted as a low level. The receivers have Schmitt trigger input with a hysteresis level of 0. V. This ensures error free-reception for both noisy inputs and for inputs with slow transition times Enable and Shutdown Functions On the ADM, both receivers are fully disabled during shutdown. On the ADM, both receivers continue to operate normally. This function is useful for monitoring activity so that when it occurs, the device can be taken out of the shutdown mode. The ADM also contains a receiver enable function (EN) which can be used to fully disable the receivers, independent of. APPLICATIONS INFORMATION A selection of typical operating circuits is shown in Figures to % A.0V µs Figure. Transmitter Output Disable Timing REV. 0

8 ADM/ADMA/ADM OUTLINE DIMENSIONS Dimensions shown in inches and (mm). -Pin Plastic DIP (N-) -Lead Narrow SOIC (R-N) PIN 0. (.) 0.00 (.0) 0. (.) 0.0 (0.) 0.0 (0.) 0. (.0) 0.0 (0.) 0.0 (.) 0. (.) 0.0 (.) BSC 0. (.0) 0.0 (.) REF 0.0 (.) 0.0 (.) -Lead Wide SOIC (R-W) 0.00 (.) 0.0 (.) 0.0 (0.) 0. (.) 0. (.) 0.00 (.) 0.0 (0.) 0.0 (.) SEATING PLANE 0.00 (0.) 0.0 (0.) PIN 0. (.) MAX 0.0 (.0) 0. (.) 0. (.) 0.00 (.) 0.0 (0.) 0.00 (0.0) 0. (.) 0. (.) 0.0 (.0) -Pin Plastic DIP (N-) 0. (.) 0. (.) 0.00 (0.) (0.) PIN 0.0 (0.0) (0.) 0.0 (.) 0.0 (.) 0.00 (.) 0.0 (0.) 0.0 (.0) MIN 0. (.00) 0. (.0) (.) BSC 0.0 (0.) 0.0 (0.) -Lead Wide SOIC (R-W) 0. (.) 0. (.) (.) BSC 0. (.) 0.00 (.) 0.0 (0.) 0.00 (0.0) 0. (.) 0. (.) 0.0 (0.) 0.0 (0.) 0.0 (.0) 0. (.0) 0. (.00) 0. (.0) 0.0 (.) 0.0 (.) 0.00 (0.) 0.00 (0.) 0. (.0) 0. (.0) 0. (.) 0. (.00) 0. (.) 0.0 (.) 0.0 (0.) 0.00 (0.) (0.0) 0.00 (0.) (.) 0.00 (0.) 0.0 (0.) 0.00 (0.) x (.) 0.0 (0.0) PRINTED IN U.S.A. C. / 0.0 (0.) 0.0 (0.) 0.0 (.) BSC 0.00 (.) 0.0 (.) SEATING PLANE REV. 0

9 ADM/ADMA/ADM ORDERING GUIDE Model Temperature Range Package Option* ADMAN 0 C to + C N- ADMAR 0 C to + C R-W ADMAAN 0 C to + C N- ADMAARN 0 C to + C R-N ADMAARW 0 C to + C R-W ADMAN 0 C to + C N- ADMAR 0 C to + C R-W *For outline information see Package Information section. REV. 0

10 This datasheet has been download from: Datasheets for electronics components.