Quad Audio Switch REV. B BLOCK DIAGRAM OF ONE SWITCH CHANNEL

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1 a FEATURES CIickless Bilateral Audio Switching Four SPST Switches in a -Pin Package Ultralow khz ( V rms, R L = k ) Low Charge Injection: 3 pc typ High OFF Isolation: db typ (R L = khz) Low Crosstalk: 9 db typ (R L = khz) Low ON Resistance: 8 typ Low Supply Current: 9 A typ Single or Dual Supply Operation: + V to + V or. V to V Guaranteed Break-Before-Make TTL and CMOS Compatible Logic Inputs Low Cost-Per-Switch BLOCK DIAGRAM OF ONE SWITCH CHANNEL DIGITAL LOGIC INTERFACE AND BREAK-BEFORE-MAKE Quad Audio Switch SSM RAMP GENERATOR PIN CONNECTIONS Epoxy Mini-DIP (P Suffix) and SOIC (S Suffix) SW A SW B GENERAL DESCRIPTION The SSM integrates four SPST analog switches in a single -pin package. Developed specifically for high performance audio applications, distortion and noise are negligible over the full operating range of Hz to khz. With very low charge injection of 3 pc, clickless audio switching is possible, even under the most demanding conditions. Switch control is realized by conventional TTL or CMOS logic. Guaranteed break-before-make operation assures that all switches in a large system will open before any switch reaches the ON state. Single or dual supply operation is possible. Additional features include db OFF isolation, 9 db crosstalk and 8 Ω ON resistance. Optional current-mode switching permits an extended signal-handling range. Although optimized for large load impedances, the SSM maintains good audio performance even under low load impedance conditions. SW A SW B SW SW NC* SW B SW A SW SW O TOP VIEW (Not SSM to Scale) SW SW SW3 NC = NO CONNECT SW A SW B SW SW3 *CONNECT TO ANALOG GROUND FOR BEST NOISE ISOLATION SW3 B SW3 A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7/39-7 Fax: 7/3-873

2 SSM SPECIFICATIONS (V S = V, T A = + C, unless otherwise noted. Typical specifications apply at T A = + C.) Parameter Symbol Conditions Min Typ Max Units AUDIO PERFORMANCE Total Harmonic Distortion Plus Noise khz, with 8 khz Filter, R L = kω, V IN = V rms.8 % Spectral Noise Density e n Hz to khz.8 nv/ Hz Wideband Noise Density e n p-p Hz to khz. µv p-p ANALOG SIGNAL SECTION Analog Voltage Range V A V INH =. V, I A = ± ma ± V Analog Current Range I A V INH =. V, V A = V ± ma ON Resistance R ON I A = ± ma, V A = ± V dc 8 Ω R ON Matching R ON Match I A = ± ma, V A = V % ON Leakage Current I S(ON) V A = ± V. + na OFF Leakage Current I S(OFF) V A = ± V. + na Charge Injection Q 3 pc ON-State Input Capacitance C ON V A = V rms 3 pf OFF-State Input Capacitance C OFF V A = V rms 7 pf OFF Isolation I SO(OFF) V A = mv rms, f = khz, R L = kω db Channel-to-Channel Crosstalk C T V A = mv rms, f = khz, R L = kω 9 db SECTION Digital Input High V INH = V. V S V Digital Input Low V INL = V.8 V Turn-On Time t ON See Test Circuit 8 ms Turn-Off Time t OFF See Test Circuit 3 ms Break-Before-Make Time Delay t ON -t OFF 3 ms Logic Input Current Logic HI V INH =. V.3 + na Logic LO V INL =.8 V. + na POWER SUPPLY Supply Voltage Range V S Single Supply + + V Dual Supply ±. ± V Positive Supply Current I SY+ All Channels On.9 ma Negative Supply Current I SY All Channels On.. ma Ground Current All Channels On..3 ma NOTES Turn-on time is measured from the time the logic input reaches the % point to the time the output reaches % of the final value. Turn-off time is measured from the time the logic input reaches the % point to the time the output reaches % of the initial value. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS Supply Voltage Single Supply V Dual Supply ±3. V Analog Input Voltage (V A ) V S Logic Input Voltage (V INL/INH ) V S Maximum Current Through Any Switch ma Operating Temperature Range C to +8 C Storage Temperature Range C to + C Junction Temperature (T J ) C Lead Temperature (Soldering, sec) C Thermal Resistance -Pin Plastic DIP (P): θ JA = 7, θ JC = C/W -Pin SOIC (S): θ JA = 9, θ JC = C/W NOTE θ JA is specified for worst case mounting conditions, i.e., θ JA is specified for device in socket for P-DIP package. ORDERING GUIDE Operating Temperature Package Model Range Package Option* SSMP C to +8 C -Pin Plastic DIP N- SSMS C to +8 C -Pin SOIC R- *N = Plastic DIP, R = SOIC.

3 SSM V A (IN) = mvrms f = Hz TO khz V A (IN) Ω R = kω AND kω L OFF ISOLATION = LOG VA (IN) OFF Isolation Test Circuit LOGIC INPUT V A (IN) LOW HIGH.V t tr ns f ns DC VOLTAGE CLOSED.V LOW Figure. Headroom (V S = ± V, f = khz, with 8 khz Filter) OPEN % % OPEN. t ON t OFF t ON /t OFF Timing Diagram. +V THD + N %. V A (IN) SWITCH CONROL. GND V. k k k LOAD RESISTANCE Ω Test Circuit for t ON /t OFF Timing Specification, t ON /t OFF Switching Response, and ON/OFF Transition Photos Figure 3. THD+N vs. Load (V S = ± V, V A = V rms, f = khz, with 8 khz Filter). THD + N %. Figure. THD+N vs. Frequency (V S = ± V, V A = V rms, with 8 khz Filter). ± ±8 ± SUPPLY VOLTAGE V Figure. THD+N vs. Supply Voltage (V A = V rms, f = khz, R L = kω, with 8 khz Filter) 3

4 SSM 9. OUTPUT VOLTAGE SWING V RMS T A = C f = khz Figure. Frequency Response (V S = ± V, V A = V rms, R L = kω). k k k LOAD RESISTANCE Ω Figure 8. Output Voltage Swing vs. Load Resistance 9 CH A: 8.µV FS MKR:.µV/ Hz.µV/DIV OUTPUT VOLTAGE SWING V RMS T A = C R L = kω f = khz.% THD + N Hz MKR: Hz khz BW: Hz Figure. SSM Spectral Noise Density e n [ Devices ( Switches) Chained Together] ± ± ±8 ± ± SUPPLY VOLTAGE Volts Figure 9. Output Voltage Swing vs. Supply Voltage 3 T A = C V A = mv RMS V 9 V % V V µs INPUT OUTPUT Figure 7. Square Wave Response (T A = + C, V S = ± V, R L = kω, f = khz) OFF ISOLATION db R = k L R = k L k k k FREQUENCY Hz Figure. OFF-Isolation vs. Frequency

5 SSM CROSSTALK db R = k L T A = C V A = mvrms R = k L SWITCH LEAKAGE CURRENT na 3 V INL=.8V R L = C TO +8 C k k k FREQUENCY Hz Figure. Channel-to-Channel Crosstalk vs. Frequency (Worst Case Conditions, as Measured Between Switches and, or and 3) ANALOG INPUT VOLTAGE Volts Figure. Leakage Current vs. Analog Voltage R L = I A = ma 8 V A = ±V R L = ON RESISTANCE Ω 3 +8 C + C C SWITCHING TIME ms 8 T ON T OFF ANALOG INPUT VOLTAGE Volts Figure. ON Resistance vs. Analog Voltage 8 TEMPERATURE C Figure. Switching Time vs. Temperature 9. SWITCH LEAKAGE CURRENT ma T A = C R L = V =.8V IL V =.V IH SUPPLY CURRENT ma V A = GND V INH =.V I SY+ I SY I GND.8 ANALOG INPUT VOLTAGE Volts Figure 3. Overvoltage Characteristics. 8 TEMPERATURE C Figure. Supply Current vs. Temperature

6 SSM V V 9 V % ms/div ANALOG OUTPUT LOGIC INPUT V INL/INH SSM can also be configured as a : multiplexer, or by using additional packages, as 8: or : and up. The breakbefore-make feature is guaranteed from part to part allowing such multiple-package applications. As Figure shows, the SSM is easy to use, and no additional devices are needed. The load resistors are recommended for improved OFF-isolation and charge injection. The ON resistance of the switch is only 8 Ω typically, which causes very little signal attenuation even with a load resistor. Figure 7. t ON /t OFF Switching Response OUT R L IN 3 SW SW 9 8 IN R L OUT 9 SW SW TOP VIEW (Not to Scale) SSM 7 +V SW SW3 OPEN (SWITCH OFF) % mv µs CLOSED (SWITCH ON) OUT R L IN SW SW3 R IS OPTIONAL L 3 V R L IN3 OUT3 SW SWITCH STATE OFF ON Figure 8. Switch OFF-to-ON Transition (R L = kω) CLOSED (SWITCH ON) 9 % mv µs OPEN (SWITCH OFF) Figure 9. Switch ON-to-OFF Transition (R L = kω) APPLICATIONS INFORMATION The SSM integrates four analog CMOS switches with guaranteed break-before-make operation to provide high quality audio switching. Each switch has complementary N-channel and P-channel MOSFETs to allow the analog input voltage range to include the positive and negative rails and improve linearity. In addition, the topology permits fully bilateral switching. When using the SSM there is full flexibility in configuring the switches. For example, they can be used individually as shown in Figure, or as a double-pole, double-throw (DPDT) switch, which is explained later. The Figure. Basic Circuit Configuration OPTIMIZING PERFORMANCE As the performance curves show, the switch is optimized for high impedance loads. The distortion performance is at its best when the switch has a load impedance of kω or greater as shown in Figure. However, even at lower values of load resistances, the khz distortion performance is still excellent,.% for a kω load. The main trade-off with THD is OFF-isolation and crosstalk. This is shown in Figures and, again with two different load conditions. As these graphs show, the kω load yields approximately a db improvement in both characteristics. Thus, the optimum operating point depends on the most critical parameters. When THD is critical then high load impedances should be used; however, when crosstalk and OFFisolation are critical, lower impedances on the order of kω should be used. An additional benefit of using the smaller load resistor is that any charge injected onto the output will be shunted to ground through the resistor. If improved OFFisolation is needed, the SSM dual audio switch should be considered with its excellent db OFF-isolation at khz. It is important that all of the pins be connected to the system analog ground. These pins isolate the input and output of each switch. Without connecting these pins, the OFFisolation will degrade significantly.

7 SSM DETAILED SWITCH OPERATION A simplified circuit schematic with the functional sections is shown in Figure. The TTL interface has an internally regulated V to ensure TTL logic levels regardless of the supply voltage. The logic threshold is with respect to the pin, which can be offset. For example, if is connected to the negative supply, then the SSM will operate with negative rail logic. The interface shifts the control logic down to the negative supply and inverts it to drive N. SW TTL INTERFACE na N C pf BREAK-BEFORE-MAKE P N P na P3 N3 RAMP GENERATOR Figure. Simplified Schematic BIAS C pf N SW A SW B N in combination with C and the na current source provides the break-before-make operation of the switch. When the switch is on, N is off and C is charged up to the positive rail. However, when the SW is turned off, then the gate of N is pulled high. This turns N on, providing a low impedance path to quickly discharge C to the negative rail, which quickly breaks the switch. On the other hand, when the SW goes high again, the gate of N is pulled low, turning it off. This leaves C to be slowly charged up to the positive rail by the na current source. The difference in the discharge and charging times ensures break-before-make operation, even from device to device. The voltage on C is inverted by P to drive the ramp generator differential pair, consisting of P, P3 and N, N3. This differential pair steers the na of tail current to either charge or discharge C. As discussed above, when the switch is on, C is charged up to the positive rail. P inverts this, putting a low voltage equivalent to the negative supply on the gate of P. The BIAS voltage is approximately equal to the midpoint of the two supply voltages. Thus, when P is pulled down, it is turned on and P3 is off. All of the na flows through N and is mirrored by N3. Thus, the na discharges C through N3. When C is pulled low, the inverter turns N on by pulling its gate high, and the second inverter turns P on. To turn the switch off the gate of P is pulled above the BIAS so that all na charges C through P3. This is then inverted to turn off N and P. The internal ramp has rise and fall times on the order of a few milliseconds which is sped up by the inverters. As the gate P voltages of N and P are changing, the ON resistance of each switch is ramping from its OFF state to 8 Ω and vice versa. The actual rise and fall times are shown in Figures 8 and 9 for a kω load. These times are significantly slower than typical switches, minimizing the SSM s charge injection and giving it clickless performance. DOUBLE-POLE DOUBLE-THROW SWITCH The SSM is ideal as a one-chip solution for a stereo switch. The schematic in Figure shows the typical configuration. This circuit will select one of two stereo sources, channel A or B. The switch controls for the left and right input of each channel are tied together so that both will be turned on or off simultaneously. An inverter is inserted between the channel A and B controls so that only one logic signal is needed. The outputs can be configured many different ways, such as an inverting or noninverting amplifier stage, and the kω load resistors are added to improve the OFF-isolation. The performance of this stereo switch is equivalent to each individual switch, yielding a high quality audio switch that is virtually transparent to the signal. SSM 8 L INA SW 3 L INB SW SW SWA/SWB 9 SW3 SW 9 SW R INA R INB SW3 SW L OUT kω SWA/SWB R OUT kω CHANNEL SELECTED Figure. Double-Pole, Double-Throw Stereo Switch VIRTUAL GROUND SWITCHING The SSM was built on a CMOS process with a V operating limit for the total supply voltage across the part. This leads to a corresponding limit on the analog voltage range. However, to achieve larger signal swings, the SSM should be configured in the virtual ground mode. As shown in Figure 3, the output of the SSM is connected to the inverting input of an amplifier. Since the noninverting input is grounded, the SSM will also be biased at ground, and large voltage swings on the circuit s input will not significantly change the voltage on the switch. The only limitation is that the current through the switch needs to be less than ± ma, and the voltage range is limited only by the op amp and its supply voltages. B A 7

8 SSM The circuit was tested with an SSM3 high slew rate audio amplifier and the results are shown in Figures and. This configuration yields excellent THD performance that is primarily determined by the amplifier. Also, the headroom is now + dbu ( dbu =.77 V rms), which is due to the amplifier s output voltage swing. Thus, even though the SSM has a ± V limitation on its supplies, it can be used in systems with much higher voltage ranges. For example, the double-pole double-throw switch from Figure can be reconfigured in the virtual ground mode to allow higher voltage swings, as shown in Figure. This application realizes the excellent performance of Figures and while providing a low cost switching solution. AUDIO IN N9 R kω +V SSM SW A 3 SW B R kω +8V SSM3 AUDIO OUT kω L INA kω L INB SWA/SWB kω R INA kω R INB 7 SSM 8 SW 3 SW SW SW3 9 SW 9 SW 3 SW3 8 SW k Ω L OUT SSM3 kω R OUT SSM3 C /9 V 8V Figure 3. Virtual Ground Switching Figure. Double-Pole, Double-Throw Stereo Switch Using Virtual Ground Operation OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Mini-DIP (P Suffix) Figure. Virtual Ground Switch THD+N vs. Frequency (V S = ± V, V A = V rms, with 8 khz Filter) PIN. (.33) MAX. (.). (3.8). (.8). (.3). (.9).9 (3.). (.) BSC.8 (7.). (.). (.). (.38). (3.8) MIN.7 (.77) SEATING. (.) PLANE.3 (8.).3 (7.). (.38).8 (.).9 (.9). (.93) SOIC (S Suffix) PIN.8 (3.).9 (.).99 (7.).9 (7.).93 (.).3937 (.) PRINTED IN U.S.A.. (.7) BSC.3 (.).9 (.3).9 (.7).98 (.) X - 8 Figure. Virtual Ground Switch Headroom (V S = ± V for SSM; V S = ±8 V for Op Amp, f = khz, with 8 khz Filter).8 (.3). (.).9 (.9).38 (.3). (.3).9 (.3). (.7).7 (.) 8

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