LT1780/LT1781 Low Power 5V RS232 Dual Driver/Receiver with ±15kV ESD Protection DESCRIPTIO

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Violet Beasley
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1 FEATRES ma Max Supply Current ESD Protection to IEC -- Level ±1kV Air Gap, ±kv Contact ses Small Capacitors:.1µF kbaud Operation for R L = 3k, C L = pf kbaud Operation for R L = 3k, C L = pf Outputs Withstand ±3V Without Damage CMOS Comparable Low Power: mw Operates from a Single V Supply Rugged Bipolar Design Outputs Assume a High Impedance State When Off or Powered Down Meets All RS3 Specifications Available With or Without Shutdown Absolutely No Latch-up APPLICATI LOGIC INPTS LOGIC OTPTS.1µF.1µF ON/OFF 1 O S Portable Computers Battery-Powered Systems Power Supply Generator Terminals Modems TYPICAL APPLICATI LT17 k k O.1µF.1µF V INPT V + OT V OT 17/1 TA1 LT17/LT171 Low Power V RS3 Dual Driver/Receiver with ±1kV ESD Protection DESCRIPTIO, LTC and LT are registered trademarks of Linear Technology Corporation. TransZorb is a registered trademark of General Instruments, GSI. DRIVER OTPT R L = 3k C L = pf RECEIVER OTPT R C L = pf INPT The LT 17/LT171 are dual RS3 driver/receiver pairs with integral charge pump to generate RS3 voltage levels from a single V supply. sing only.1µf external capacitors, these circuits consume only mw of power, and can operate to kbaud even while driving heavy capacitive loads. New ESD structures on the chip allow the LT17/LT171 to survive ±1kV air gap and ±kv contact ESD tests per IEC --, eliminating the need for costly TransZorbs on the RS3 line pins. The LT17/ LT171 are fully compliant with EIA RS3 standards. Driver outputs are protected from overload, and can be shorted to ground or up to ±3V without damage. During SHTDOWN or power-off conditions, driver and receiver outputs are in a high impedance state, allowing line sharing. The LT17/LT171 are direct upgrades to the LTA/ LT1A, LTA/LT1A and LT1 for applications which require the utmost ESD protection. The LT171 is available in 1-pin DIP,SO and SW packages. The LT17 is supplied in 1-pin DIP and SW packages for applications which require SHTDOWN. Output Waveforms 17/1 TA 1

2 LT17/LT171 ABSOLTE AXI RATI GS W W W Supply Voltage (V CC )... V V +....V V....V Input Voltage Driver... V to V + Receiver... 3V to 3V ON/OFF....3V to V Output Voltage Driver... V + 3V to V + 3V Receiver....3V to V CC +.3V PACKAGE/ORDER I FOR NC C1 + V + C1 C + C V TR OT REC IN N PACKAGE 1-LEAD PLASTIC DIP TOP VIEW 1 ON/OFF 17 V CC 1 GND 1 TR1 OT REC1 IN REC1 OT TR1 IN TR IN REC OT SW PACKAGE 1-LEAD PLASTIC SO T JMAX = C, θ JA = C/ W, θ JC = 3 C/W (N) T JMAX = C, θ JA = C/ W, θ JC = C/W (SW) W Consult factory for Industrial and Military grade parts. ATIO ORDER PART NMBER LT17CN LT17CSW ELECTRICAL CHARA CTERISTICS (Note ) (Note 1) Short-Circuit Duration V sec V... 3 sec Driver Output... Indefinite Receiver Output... Indefinite Operating Temperature Range... C to 7 C Storage Temperature Range... C to 1 C Lead Temperature (Soldering, sec)... 3 C C1 + 1 V + C1 3 C + C V TR OT 7 REC IN N PACKAGE 1-LEAD PLASTIC DIP TOP VIEW S PACKAGE 1-LEAD PLASTIC SO 1 V CC 1 GND TR1 OT REC1 IN REC1 OT TR1 IN TR IN REC OT SW PACKAGE 1-LEAD PLASTIC SO T JMAX = C, θ JA = C/ W, θ JC = C/W (N) T JMAX = C, θ JA = C/ W, θ JC = 3 C/W (S) T JMAX = C, θ JA = C/ W, θ JC = 7 C/W (SW) ORDER PART NMBER LT171CN LT171CS LT171CSW PARAMETER CONDITIONS MIN TYP MAX NITS Power Supply Generator V + Output 7. V V Output 7 V Supply Current (V CC ) (Note 3), T A = C ma ma Supply Current When OFF (V CC ) SHTDOWN (Note ) LT17 Only 1 µa Supply Rise Time C1 = C = C3 = C =.1µF. ms SHTDOWN to Turn-On LT17 Only. ms ON/OFF Pin Thresholds Input Low Level (Device SHTDOWN). 1. V Input High Level (Device Enabled) 1.. V ON/OFF Pin Current V V ON/OFF V 1 µa Oscillator Frequency khz Driver Output Voltage Swing Load = 3k to GND Positive. 7. V Negative.3 V Logic Input Voltage Level Input Low Level (V OT = High) 1.. V Input High Level (V OT = Low). 1. V

3 ELECTRICAL CHARA CTERISTICS (Note ) LT17/LT171 PARAMETER CONDITIONS MIN TYP MAX NITS Logic Input Current.V V IN.V µa Output Short-Circuit Current V OT = V ±7 17 ma Output Leakage Current SHTDOWN V OT = ±3V (Note ) µa Data Rate R L = 3k, C L = pf kbaud R L = 3k, C L = pf kbaud Slew Rate R L = 3k, C L = 1pF 1 3 V/µs R L = 3k, C L = pf 7 V/µs Propagation Delay Output Transition t HL High-to-Low (Note ). 1.3 µs Output Transition t LH Low-to-High. 1.3 µs Receiver Input Voltage Thresholds Input Low Threshold (V OT = High). 1.3 V Input High Threshold (V OT = Low) 1.7. V Hysteresis.1. 1 V Input Resistance V IN = ±V 3 7 kω Output Leakage Current SHTDOWN (Note ) V OT V CC 1 µa Output Voltage Output Low, I OT = 1.mA.. V Output High, I OT = 1µA (V CC = V) 3.. V Output Short-Circuit Current Sinking Current, V OT = V CC ma Sourcing Current, V OT = V ma Propagation Delay Output Transition t HL High-to-Low (Note ) ns Output Transition t LH Low-to-High 3 ns The denotes specifications which apply over the operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note : Testing done at V CC = V and V ON/OFF = 3V, unless otherwise specified. Note 3: Supply current is measured as the average over several charge pump cycles. C + = C = C1 = C =.1µF. All outputs are open, with all driver inputs tied high. Note : Supply current measurements in SHTDOWN are performed with V ON/OFF.1V. Note : For driver delay measurements, R L = 3k and C L = 1pF. Trigger points are set between the driver s input logic threshold and the output transition to the zero crossing (t HL = 1.V to V and t LH = 1.V to V). Note : For receiver delay measurements, C L = 1pF. Trigger points are set between the receiver s input logic threshold and the output transition to standard TTL/CMOS logic threshold (t HL = 1.3V to.v and t LH = 1.7V to.v). 3

4 LT17/LT171 TYPICAL PERFOR A W CE CHARA CTERISTICS PEAK OTPT VOLTAGE (V) Driver Maximum Output Voltage vs Load Capacitance k BAD k BAD k BAD PEAK OTPT VOLTAGE (V) Driver Minimum Output Voltage vs Load Capacitance k BAD k BAD k BAD DRIVER OTPT VOLTAGE (V) Driver Output Voltage R L = 3k V CC =.V V CC = V V CC =.V OTPT HIGH OTPT LOW V CC =.V V CC = V V CC =.V LOAD CAPACITANCE (nf) LOAD CAPACITANCE (nf) 7 TEMPERATRE ( C) 17 G1 17 G 17 G3 THRESHOLD VOLTAGE (V) Receiver Input Thresholds INPT HIGH INPT LOW 7 TEMPERATRE ( C) 17 G SPPLY CRRENT (ma) 3 Supply Current vs Data Rate DRIVERS ACTIVE R L = 3k C L = pf 7 DATA RATE (kbad) 1 17 G 3. ON/OFF Thresholds Supply Current THRESHOLD VOLTAGE (V) ON THRESHOLD OFF THRESHOLD SPPLY CRRENT (ma) 1 DRIVERS LOADED R L = 3k 1 DRIVER LOADED R L = 3k NO LOAD 7 TEMPERATRE ( C) 7 TEMPERATRE ( C) 17 G 17 G7

1 7 TEMPERATRE ( C) 17 G 7 TEMPERATRE ( C) 17 G Receiver Short-Circuit Current 1 Slew Rate vs Load Capacitance SHORT-CIRCIT CRRENT (ma) 3 RX ISC + RX

5 LT17/LT171 TYPICAL PERFOR A W CE CHARA CTERISTICS Driver Leakage in Shutdown 3 Driver Short-Circuit Current LEAKAGE CRRENT (µa) 1 V OT = 3V V OT = 3V SHORT-CIRCIT CRRENT (ma) 1 ISC + ISC.1 7 TEMPERATRE ( C) 17 G 7 TEMPERATRE ( C) 17 G Receiver Short-Circuit Current 1 Slew Rate vs Load Capacitance SHORT-CIRCIT CRRENT (ma) 3 RX ISC + RX ISC SLEW RATE (V/µs) SLEW +SLEW 7 TEMPERATRE ( C) LOAD CAPACITANCE (nf) 17 G 17 G DRIVER 1 OTPT DRIVER OTPT V V GND GND V V Shutdown to Driver Outputs DRIVER OTPT R L = 3k C L = pf DRIVER OTPT R L = 3k Driver Output Waveforms ON/OFF PIN INPT 17 G 17 G

6 LT17/LT171 PI F CTIO S V CC : V Input Supply Pin. This pin should be decoupled with a.1µf ceramic capacitor close to the package pin. Insufficient supply bypassing can result in low output drive levels and erratic charge pump operation. GND: Ground Pin. ON/OFF: A TTL/CMOS Compatible Operating Mode Control. A logic low puts the LT17 in SHTDOWN mode. Supply current drops to zero and both driver and receiver outputs assume a high impedance state. A logic high fully enables the device. V + : Positive Supply Output (RS3 Drivers). V + V CC 1.V. This pin requires an external charge storage capacitor C.1µF, tied to ground or V CC. Larger value capacitors may be used to reduce supply ripple. With multiple transceivers, the V + and V pins may be paralleled into common capacitors. V : Negative Supply Output (RS3 Drivers). V (V CC.V). This pin requires an external charge storage capacitor C.1µF. Larger value capacitors may be used to reduce supply ripple. With multiple transceivers, the V + and V pins may be paralleled into common capacitors. TR1 IN, TR IN: RS3 Driver Input Pins. These inputs are TTL/CMOS compatible. Inputs should not be allowed to float. Tie unused inputs to V CC. TR1 OT, TR OT: Driver Outputs at RS3 Voltage Levels. Driver output swing meets RS3 levels for loads up to 3k. Slew rates are controlled for lightly loaded lines. Output current capability is sufficient for load conditions up to pf. Outputs are in a high impedance state when in SHTDOWN mode or V CC = V. Outputs are fully shortcircuit protected from V + 3V to V + 3V. Applying higher voltages will not damage the device if the overdrive is moderately current limited. Short circuits on one output can load the power supply generator and may disrupt the signal levels of the other outputs. The driver outputs are protected against ESD to IEC--- Level discharges. REC1 IN, REC IN: Receiver Inputs. These pins accept RS3 level signals (±3V) into a protected k terminating resistor. The receiver inputs are protected against ESD to IEC--- Level discharges. Each receiver provides.v of hysteresis for noise immunity. Open receiver inputs result in a logic high receiver output state. REC1 OT, REC OT: Receiver outputs with TTL/CMOS Voltage Levels. Outputs are in a high impedance state when in SHTDOWN mode to allow data line sharing. Outputs are fully short-circuit protected to ground or V CC with the power ON, OFF or in the SHTDOWN mode. C1 +, C1, C +, C : Commutating Capacitor Inputs. These pins require two external capacitors C.1µF: one from C1 + to C1 and another from C + to C. C1 should be deleted if a separate V supply is available and connected to pin C1 +. Similarly, C should be deleted if a separate V supply is connected to pin V.

7 LT17/LT171 ESD PROTECTIO The RS3 line inputs of the LT17/LT171 have on-chip protection from ESD transients up to ±1kV air gap and ±kv contact tested to IEC--- test methods. The protection structures act to divert the static discharge safely to system ground. In order for the ESD protection to function effectively, the power supply and ground pins of the circuit must be connected to ground through low impedances. The power supply decoupling capacitors and charge pump storage capacitors provide this low impedance in normal application of the circuit. The only constraint is that low ESR capacitors must be used for bypassing and charge storage. ESD testing must be done with pins V CC, V L, V +, V, and GND shorted to ground or connected with low ESR capacitors..1µf.1µf.1µf.1µf RS3 LINE PINS PROTECTED TO IEC--- LEVEL DR OT 1 NC C1 + RX IN V + 3 C1 C + C V 7 ESD Test Circuit LT17 1 ON/OFF 17 V V CC 1 GND 1 DR1 OT RX1 IN RX1 OT DR1 IN DR IN RX OT 17 ESD TC.1µF RS3 LINE PINS PROTECTED TO IEC--- LEVEL TYPICAL APPLICATIO Operation sing V and V Power Supplies V INPT 17 V INPT 3 LT17.1µF 7.1µF V OT LOGIC INPTS LOGIC OTPTS k 1 k ON/OFF /1 TA3 7

8 LT17/LT171 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N Package 1-Lead PDIP (Narrow.3) (LTC DWG # --1).77* (1.) MAX 1 1. ±.1* (.77 ±.31) (7..). ±. (3.3 ±.7).. ( )..1 (..31) ( ). (.) MIN. (3.17) MIN. ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (1.1) TYP.1 ±.3 (.7 ±.7) N1 7 N Package 1-Lead PDIP (Narrow.3) (LTC DWG # --1).* (.) MAX ±.1* (.77 ±.31).3.3 (7..). ±. (3.3 ±.7) ( )..1 (..31) ( ). (.) MIN. (3.17) MIN *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.7) MIN. ±. (. ±.). (1.1) TYP.1 ±.3 (.7 ±.7) N1 7

9 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 1-Lead Plastic Small Outline (Wide.3) (LTC DWG # --1).3.* (..) 1 1 LT17/LT171 NOTE (.7.3).1.** ( ).. (..737).3. (.3.) (. 1.3) TYP.. (..33). (1.7) TYP..1 (.3.) TYP NOTE 1.1. (. 1.7) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.1mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..3) S1 (WIDE) 3

10 LT17/LT171 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. SW Package 1-Lead Plastic Small Outline (Wide.3) (LTC DWG # --1).7.3* (.3.7) SEE NOTE.3.1 (.7.3).1.** ( ).. (..737).3. (.3.) (. 1.3) TYP.. (..33) NOTE 1.1. (. 1.7). (1.7) TYP..1 (.3.) TYP NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.1mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..3) S1 (WIDE) 3

11 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. LT17/LT171 S Package 1-Lead Plastic Small Outline (Narrow.1) (LTC DWG # --1).3.3* (..) (.71.17).1.17** (3. 3.).. (.3.).. (..) TYP.3. ( ) (.1.) *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.1mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE..1 (.3.3). (1.7) TYP S1 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

12 LT17/LT171 TYPICAL APPLICATIO Supporting an LT3 (Triple Driver/Receiver) SHTDOWN 1 ON/OFF V CC 17 LT17 TTL INPT V 1 V CC ON/OFF 17 LT3 1 TTL INPT TTL INPT 1 TTL INPT TTL INPT TTL OTPT k 1 TTL OTPT 3k 3 TTL OTPT k TTL OTPT 3k 1µF 1µF C1 + C1 C + C GND 1 V + V 3 7 TTL OTPT 1 1µF 1µF V + V 7 3k GND 17/1 TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LT37A 3Driver/Receiver RS3 Transceiver IEC--- Level ESD Compliance LTC3 V Low Power RS3 Driver/Receiver Transceiver Low Supply Current I CC = µa LTC7 Single V RS3/RS Multiprotocol Transceiver Configurable as Dual RS3 or Single RS Transceiver Linear Technology Corporation McCarthy Blvd., Milpitas, CA () 3-1 FAX: () f LT/TP K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 1

LT1342 5V RS232 Transceiver with 3V Logic Interface DESCRIPTIO

LT1342 5V RS232 Transceiver with 3V Logic Interface DESCRIPTIO V RS Transceiver with V Logic Interface FEATRES ESD Protection Over ±kv V Logic Interface ses Small Capacitors:.µF,.µF µa Supply Current in Shutdown Low Power Driver Disable Operating Mode Pin Compatible