LTC1518/LTC Mbps Precision Delay RS485 Quad Line Receivers DESCRIPTIO FEATURES APPLICATIO S TYPICAL APPLICATIO

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1 FEATRES Precision Propagation Delay: 8.ns ±.ns Over C to C Temperature Range High Data Rate: Mbps Low t PLH /t PHL Skew: ps Typ Low Channel-to-Channel Skew: ps Typ Guaranteed Fail-Safe Operation over the Entire Common Mode Range V to V RS8 Input Common Mode Range Input Resistance k, Even When npowered Hot Swap TM Capable High Common Mode Rejection to MHz Short-Circuit Protection: ma Typ Output Current for an Indefinite Short Three-State Output Capability Will Not Oscillate with Slow Moving Input Signals Single V Supply Pin Compatible with LTC88, LTC89 APPLICATIO S High Speed RS8/RS Receivers STS-/OC- Data Receivers PECL Line Receivers Level Translators Fast-/Fast- SCSI Receiver, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. LTC8/LTC9 Mbps Precision Delay RS8 Quad Line Receivers DESCRIPTIO The LTC 8/LTC9 are high speed, precision delay differential quad bus/line receivers that can operate at data rates as high as Mbps. They are pin compatible with the LTC88/LTC89 RS8 line receivers and operate over the entire V to V common mode range. A unique architecture provides very stable propagation delays and low skew over wide input common mode, input overdrive and ambient temperature ranges. Propagation delay is 8.ns ±.ns over the commercial temperature range. Typical t PLH /t PHL and channel-to-channel skew is ps. Each receiver translates differential input levels ( V ID mv) into valid CMOS and TTL output levels. Its high input resistance ( k) allows many receivers to be connected to the same driver. The receiver outputs go into a high impedance state when disabled. The receivers have a fail-safe feature that guarantees a high output state when the inputs are shorted or left floating. Other protection features include thermal shutdown and a controlled maximum short-circuit current (ma Max). Input resistance remains k when the device is unpowered or disabled, thus allowing hot swapping without loading the data lines. The LTC8/LTC9 operate from a single V supply and draw ma of supply current. TYPICAL APPLICATIO Mbps Data Communication over Twisted Pair Propagation Delay Guaranteed to Fall Within Shaded Area (±.ns) T A = C TO C RE RO DI DE LTC8 Ω A EN EN RO RE RO Ω DI B DE / LTC8 LTC8 8/9 F8 V IN = V/DIV V OT = V/DIV OTPT V DD = V INPT V ID =.V TIME (ns) 8/9 TA

2 LTC8/LTC9 ABSOLTE AXI RATI GS W W W (Note ) Supply Voltage... V Digital Input Currents... ma to ma Digital Input Voltages....V to V Receiver Input Voltages... ±V Receiver Output Voltages....V to V DD.V Receiver Input Differential... V Short-Circuit Duration... Indefinite Operating Temperature Range LTC8C/LTC9C... C to C LTC8I/LTC9I... C to 8 C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C W PACKAGE/ORDER I FOR ATIO B TOP VIEW V DD ORDER PART NMBER B TOP VIEW V DD ORDER PART NMBER A OT EN B A OT LTC8CS LTC8IS A OT EN B A OT LTC9CS LTC9IS OT EN OT EN A OT A OT B A B A GND 8 9 B GND 8 9 B S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/ W Consult factory for Military grade parts. DC ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V DD = V ±% (Notes, ) per receiver, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V CM Input Common Mode Voltage A, B Inputs V V IH Input High Voltage EN, EN, EN, EN V V IL Input Low Voltage EN, EN, EN, EN.8 V I IN Input Current EN, EN, EN, EN µa I IN Input Current (A, B) V A, V B = V µa V A, V B = V µa R IN Input Resistance V V CM V (Figure ) kω C IN Input Capacitance (Note ) pf V OC Open-Circuit Input Voltage V DD = V (Note ) (Figure )... V V ID(MIN) Differential Input Threshold Voltage V V CM V.. V dv ID Input Hysteresis V CM =.V mv V OH Output High Voltage I OT = ma, V ID =.V, V DD = V. V V OL Output Low Voltage I OT = ma, V ID =.V, V DD = V. V I OZR Three-State Output Current V < V OT < V µa I DD Total Supply Current All Receivers V ID >.V, No Load, Device Enabled ma I OSR Short-Circuit Current V OT = V, V OT = V (Note ) ma

3 LTC8/LTC9 DC ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V DD = V ±% (Notes, ) per receiver, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Max V ID for Fail-Safe Detection V V CM V mv Min Time to Detect Fault Condition µs CMRR Common Mode Rejection Ratio V CM =.V, f = MHz (Note ) db SWITCHI G TI E CHARACTERISTICS W The denotes specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V DD = V ±% (Notes, ) V ID =.V, V CM =.V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS t PLH, t PHL Input-to-Output Propagation Delay C L = pf, C T A C (Figure ) 8. ns C L = pf, C T A 8 C (Figure ) ns t r, t f Rise/Fall Times C L = pf. ns t SKD t PLH t PHL Skew C L = pf, Same Receiver (Note ) ps t ZL Enable to Output Low C L = pf, C T A C (Figure ) ns C L = pf, C T A 8 C (Figure ) ns t ZH Enable to Output High C L = pf, C T A C (Figure ) ns C L = pf, C T A 8 C (Figure ) ns t LZ Disable from Output Low C L = pf, C T A C (Figure ) ns C L = pf, C T A 8 C (Figure ) ns t HZ Disable from Output High C L = pf, C T A C (Figure ) ns C L = pf, C T A 8 C (Figure ) ns t CH-CH Channel-to-Channel Skew C L = pf (Figure, Note ) ps t PKG-PKG Package-to-Package Skew C L = pf, Same Temperature. ns (Figure, Note ) t r, t f Input Maximum Input Rise or Fall Time (Note ) ns Minimum Input Pulse Width C T A C (Note ) 9. ns C T A 8 C (Note ) ns f IN(MAX) Maximum Input Frequency Square Wave, C T A C (Note ) MHz Square Wave, C T A 8 C (Note ) MHz Maximum Data Rate C T A C (Note ) 8 Mbps C T A 8 C (Note ) Mbps C L Load Capacitance (Note ) pf Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : All currents into the device pins are positive; all currents out of the device pins are negative. Note : All typicals are given for V DD = V, T A = C. Note : Guaranteed by design, but not tested. Note : Worst-case t PLH t PHL skew for a single receiver in a package over the full operating temperature range. Note : Maximum difference between any two t PLH or t PHL transitions in a single package over the full operating temperature range. Note : Short-circuit current does not represent output drive capability. When the output detects a short-circuit condition, output drive current is significantly reduced until the short is removed.

4 LTC8/LTC9 TYPICAL PERFOR A CE CHARACTERISTICS W CMRR vs Frequency Propagation Delay (t PLH /t PHL ) vs Temperature Supply Current vs Data Rate COMMON MODE REJECTION RATIO (db) T A = C V CM =.V k k M FREQENCY (Hz) PROPAGATION DELAY (ns) V CM =.V V ID =.V TEMPERATRE ( C) SPPLY CRRENT (ma) T A = C V CM =.V V ID =.V S SWITCHING SWITCHING DATA RATE (Mbps) 89 G 89 G 89 G SPPLY CRRENT (ma) Supply Current vs Temperature and Data Rate V CM =.V V ID =.V SWITCHING C C C C C DATA RATE (Mbps) PROPAGATION DELAY (ns) Propagation Delay vs Load Capacitance T A = C V CM =.V V ID =.V LOAD CAPACITANCE (pf) PROPAGATION DELAY (ns) Propagation Delay vs Common Mode T A = C V ID =.V 8 COMMON MODE (V) 89 G 89 G 89 G Propagation Delay vs Input Differential Voltage Maximum Data Rate vs Input Differential Voltage PROPAGATION DELAY (ns) T A = C V CM =.V DATA RATE (Mbps) T A = C V CM =.V..... INPT DIFFERENTIAL (V) INPT DIFFERENTIAL (V). 89 G 89 G8

5 LTC8/LTC9 PI F CTIO S LTC8 B (Pin ): Receiver Inverting Input. A (Pin ): Receiver Noninverting Input. OT (Pin ): Receiver Output. EN (Pin ): A high enables all outputs; a low on Pin and a high on Pin will put all outputs into a high impedance state. Do not float. OT (Pin ): Receiver Output. A (Pin ): Receiver Noninverting Input. B (Pin ): Receiver Inverting Input. GND (Pin 8): Ground Pin. A ground plane is recommended for all LTC8 applications. B (Pin 9): Receiver Inverting Input. A (Pin ): Receiver Noninverting Input. OT (Pin ): Receiver Output. EN (Pin ): A low enables all outputs; a low on Pin and a high on Pin will put all outputs into a high impedance state. Do not float. OT (Pin ): Receiver Output. A (Pin ): Receiver Noninverting Input. B (Pin ): Receiver Inverting Input. V DD (Pin ): Power Supply Input. This pin should be decoupled with a.µf ceramic capacitor as close as possible to the pin. Recommended: V DD = V ±%. LTC9 B (Pin ): Receiver Inverting Input. A (Pin ): Receiver Noninverting Input. OT (Pin ): Receiver Output. EN (Pin ): A high enables receivers and ; a low will put the outputs of receivers and into a high impedance state. Do not float. OT (Pin ): Receiver Output. A (Pin ): Receiver Noninverting Input. B (Pin ): Receiver Inverting Input. GND (Pin 8): Ground Pin. A ground plane is recommended for all LTC9 applications. B (Pin 9): Receiver Inverting Input. A (Pin ): Receiver Noninverting Input. OT (Pin ): Receiver Output. EN (Pin ): A high enables receivers and ; a low will put the outputs of receivers and into a high impedance state. Do not float. OT (Pin ): Receiver Output. A (Pin ): Receiver Noninverting Input. B (Pin ): Receiver Inverting Input. V DD (Pin ): Power Supply Input. This pin should be decoupled with a.µf ceramic capacitor as close as possible to the pin. Recommended: V DD = V ±%.

6 LTC8/LTC9 W W SWITCHI G TI E WAVEFOR S t r = t f ns for all input and enable signals. INPT.V / LTC8 LTC9 OTPT pf 8/9 Fb V ENABLE V V OT V OL.V t ZL.V OTPT NORMALLY LOW.V t LZ.V INPT OTPT t PLH V.V.V t PHL V DD / V DD / V V OH OT V OTPT t ZH C L.V k S S OTPT NORMALLY HIGH k V DD t HZ.V 8/9 F 8/9 F Figure. Propagation Delay Test Circuit and Waveforms Figure. Receiver Enable and Disable Timing Test Circuit and Waveforms INPT A, A V B, B =.V V CH OT V DD / V DD / t CH-CH t CH-CH CH OT V DD / V DD / 8/9 F Figure. Any Channel to Any Channel Skew, Same Package INPT A, B V ID =.V SAME INPT FOR BOTH PACKAGES PACKAGE OT PACKAGE OT t PKG-PKG t PKG-PKG 8/9 F Figure. Package-to-Package Propagation Delay Skew

7 LTC8/LTC9 EQIVALE T I PT NETWORKS A B k k.v.v A B k k ENABLED, V DD = V DISABLED OR V DD = V Figure. Input Thevenin Equivalent 8/9 F APPLICATIO S I FOR ATIO W Theory of Operation nlike typical line receivers whose propagation delay can vary by as much as % from package to package and show significant temperature drift, the LTC8/LTC9 employ a novel architecture that produces a tightly controlled and temperature compensated propagation delay. The differential timing skew is also minimized between rising and falling output edges, and the propagation delays of any two receivers within a package are very tightly matched. The precision timing features of the LTC8/LTC9 reduce overall system timing constraints by providing a narrow ±.ns window during which valid data appears at the receiver output. This output timing window applies to all receivers in all packages over the commercial operating temperature range, thereby making the LTC8/LTC9 well suited for high speed data transmission. In clocked data systems, the low skew minimizes duty cycle distortion of the clock signal. The LTC8/LTC9 can propagate signals at frequencies of MHz (Mbps) with less than % duty cycle distortion. When a clock signal is used to retime parallel data, the maximum recommended data transmission rate is Mbps to avoid timing errors due to clock distortion. Thermal shutdown and short-circuit protection prevent latchup damage to the LTC8/LTC9 during fault conditions. Fail-Safe Features The LTC8/LTC9 have a fail-safe feature that guarantees the output to be in a logic HIGH state when the inputs are either shorted or left open (note that when inputs are left open, any external large leakage current might override the fail-safe). The fail-safe feature detects shorted inputs over the entire common mode range. When a fault is detected, the output will typically go high in µs. When some of the receivers within a package are not used, the open fail-safe feature will allow the user to let the receiver inputs float and maintain a high logic state at the output. Without the open fail-safe feature, any noise at the input would cause unwanted glitches at the output. When the inputs are left open, one must make sure that there are no sources of leakage current connected to one or both of the inputs. This can happen if the device is being driven single-endedly and both the signal and the DC bias are disconnected. If the capacitor used to bypass the DC bias is left connected to the input of the device and is leaky (>µa), the output of the device might not be the desired high logic state. Also keep in mind that the inputs are high impedance ( kω). When left open, noisy traces should be kept away from the receiver inputs to minimize capacitive coupling of undesired signals. Even with the open fail-safe feature, for maximum noise immunity, grounding the negative input of unused receivers is recommended.

8 LTC8/LTC9 APPLICATIO S I FOR ATIO W When the inputs are accidentally shorted (by cutting through a cable, for example), the short-circuit fail-safe feature will guarantee a high output logic level. Note also that if the line driver is removed and the termination resistors are left in place, the receiver will see this as a short and output a logic high. Both of these fail-safe features will keep the receiver from outputting false data pulses under fault conditions. Single-Ended Applications Over short distances, the LTC8/LTC9 can be configured to receive single-ended data by tying one input to a fixed bias voltage and connecting the other input to the driver output. In such applications, standard high speed CMOS logic may be used as a driver for the LTC8/LTC9. With a k minimum input resistance, the receiver trip points may be easily adjusted to accommodate different driver output swings by changing the resistor divider at the fixed input. Figure a shows a single-ended receiver configuration with the driver and receiver connected via PC traces. Note that at very high speeds, transmission line and driver ringing effects must be considered. Motorola s MECL System Design Handbook serves as an excellent reference for transmission line and termination effects. To mitigate transmission errors and duty cycle distortion due to driver ringing, a small output filter or a dampening resistor on the driver s V DD may be needed as shown in Figure b. With an open circuit voltage of.v at both inputs, the receivers can be used without an external bias applied to the fixed inputs. The fixed input should be bypassed with a.µf ceramic capacitor. The positive input should be driven with a V CMOS part in order to minimize the skew caused by the.v threshold. Figure c shows this configuration. MCACT (TTL INPT) MCAC (CMOS INPT) PC TRACE V.k.µF.k / LTC8 LTC9 MCAC Ω PC TRACE OR pf Ω.µF PC TRACE 8/9 Fa 8/9 Fb Figure a. Single-Ended Receiver Figure b. Techniques to Minimize Driver Ringing MCACT (TTL INPT) MCAC (CMOS INPT) PC TRACE.µF / LTC8 LTC9 8/9 Fc Figure c. Self Biased Single Ended Receiver 8

9 LTC8/LTC9 APPLICATIO S I FOR ATIO W Note that due to the increased skew, this configuration might not operate at the highest data rates. To transmit single-ended data over short to medium distances, twisted pair is recommended with the unused wire grounded at both ends (Figure ). Differential Transmission Data rates up to Mbps can be transmitted over feet of high quality category twisted pair. Figure 8 shows the LTC8 receiving differential data from an LTC8 transceiver. As in the single-ended configurations, care must be taken to properly terminate the differential data lines to avoid unwanted reflections, etc. V MCACT MCAC Ω -FT TWISTED PAIR V Ω / LTC8 LTC9.k.µF k 8/9 F Figure. Medium Distance Single-Ended Transmission sing a CMOS Driver RO RE RE RO DI DE LTC8 Ω A EN EN RO Ω DI B DE / LTC8 LTC8 8/9 F8 Figure 8. LTC8 Connected to LTC8 High Speed RS8 Transceiver 9

10 LTC8/LTC9 APPLICATIO S I FOR ATIO W Figure 9 shows a trace with ft category TP between an LTC8 driver and an LTC8 receiver. Notice that at the far end of the cable, the signal to the LTC8 input has been reduced. Figure shows a Mbps square wave. Output Short-Circuit Protection The LTC8/LTC9 employ voltage sensing shortcircuit protection at the output terminals. For a given input differential, this circuitry determines what the correct output level should be. For example, if the input differential is mv, it expects the output to be a logic high. If the output is subsequently shorted to a voltage below V DD /, this circuitry shuts off the output devices and turns on a smaller device in its place. A timeout period of about ns is used in order to maintain normal high frequency operation, even under heavy capacitive loads (>ma transient current into the load). V/DIV V/DIV CABLE DELAY DRIVER INPT INPT NOTES: TOP TRACE: LTC8 DRIVER INPT MID TRACE: LTC8 INPT AT FAR END OF ft CATAGORY TP BOTTOM TRACE: LTC8 OTPT V/DIV OTPT ns/div LTC8/9 F9 Figure 9. ns Pulse Propagating Down ft of Category TP V/DIV INPT NOTES: TOP TRACE: LTC8 INPT AT FAR END OF ft CAT TP BOTTOM TRACE: LTC8 OTPT V/DIV OTPT ns/div LTC8/9 F Figure. Mbps Pulse Train Over ft of Category TP

11 LTC8/LTC9 PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S Package -Lead Plastic Small Outline (Narrow.) (LTC DWG # -8-).8.9* (9.8.8) 9.8. (.9.9)..** (.8.988).8. (..).. (..8) 8 TYP..9 (..) 8.. (..).. (..) * DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE..9 (..8) TYP. (.) BSC S 98 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

12 LTC8/LTC9 TYPICAL APPLICATIO High Speed Receiver with Hot Swap Control V CC BACK PLANE PLG-IN CARD R.Ω Q MTBNV R Ω % R.8k % C µf V CC V A ON/RESET V CC ON 8 SENSE GATE FB C.µF R.k % GND CONNECTOR CONNECTOR TIMER LTC RESET GND C.µF µp RESET.k DATA BS 8 LTC8 D D.k.µF 9 D 8 D LTC8 D D 9 D 8 D 8 TA RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC8/LTC8 Low Power Quad RS8 Drivers Mbps, V to V Common Mode Range LTC88/LTC89 Low Power Quad RS8 Receivers Mbps, V to V Common Mode Range LT ltrafast TM Precision Comparator Single V Supply, ns Propagation Delay LTC High Speed, Precision Quad Differential Line Receiver Mbps, ±mv Threshold, Rail-to-Rail Common Mode LTC8/LTC8/ High Speed, Precision RS8 Transceivers Mbps, Pin Compatible with LTC8/9/9 LTC8 LTC88/LTC89 High Speed, RS8 Quad Drivers Mbps, Pin Compatible with LTC8/LTC8 ltrafast is a trademark of Linear Technology Corporation. Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- (8) -9 FAX: (8) fa LT/TP 9 K REV A PRINTED IN THE SA LINEAR TECHNOLOGY CORPORATION 99

DESCRIPTIO TYPICAL APPLICATIO. LTC1383 5V Low Power RS232 Transceiver FEATURES APPLICATIO S

DESCRIPTIO TYPICAL APPLICATIO. LTC1383 5V Low Power RS232 Transceiver FEATURES APPLICATIO S LTC V Low Power RS Transceiver FEATRES Operates from a Single V Supply Low Supply Current: I CC = µa ESD Protection Over ±kv Available in -Pin SOIC Narrow Package ses Small Capacitors: Operates to kbaud