DESCRIPTIO TYPICAL APPLICATIO. LT1803/LT1804/LT1805 Single/Dual/Quad 100V/µs, 85MHz, Rail-to-Rail Input and Output Op Amps FEATURES APPLICATIO S

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1 FEATURES Slew Rate: V/µs Gain Bandwidth Product: 8MHz Input Common Mode Range Includes Both Rails Output Swings Rail-to-Rail Low Quiescent Current: 3mA Max per Amplifier Large Output Current: 42mA Voltage Noise: 21nV/ Hz Power Supply Rejection: 9dB Open-Loop Gain: V/mV Operating Temperature Range: C to 8 C Single Available in the 8-Pin SO and -Pin Low Profile (1mm) SOT-23 (ThinSOT TM ) Package Dual Available in 8-Lead DFN and SO Packages Quad Available in the 14-Pin Narrow SO Package APPLICATIO S U Low Voltage, High Frequency Signal Processing Driving A/D Converters Rail-to-Rail Buffer Amplifiers Active Filters Video Line Driver, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. TYPICAL APPLICATIO U Inverting DC Restore R2 k DESCRIPTIO Single/Dual/Quad V/µs, 8MHz, Rail-to-Rail Input and Output Op Amps U The LT 183/LT184/LT18 are single/dual/quad, low power, high speed rail-to-rail input and output operational amplifiers with excellent DC performance. The LT183/ LT184/LT18 feature reduced supply current, lower input offset voltage, lower input bias current and higher DC gain than other devices with comparable bandwidth and slew rate. Typically, the have an input offset voltage of 3µV, an input bias current of 12nA and an open-loop gain of V/mV. The have an input range that includes both supply rails and an output that swings within mv of either supply rail to maximize the signal dynamic range in low supply applications. The are specified at 3V, V and ±V supplies and typically maintain their performance for supplies from 2.3V to 12.V. The inputs can be driven beyond the supplies without damage or phase reversal of the output. The LT183 is available in the 8-pin SO package with the standard op amp pinout and in the -pin SOT-23 package. The LT184 is available in 8-pin DFN and SO packages with the standard op amp pinouts. The LT18 features the standard quad op amp configuration and is available in a 14-pin plastic SO package. Inverting DC Restore Circuit Response V IN R1 1k A 1/2 LT184 V OUT V IN mv/div GND D2 1N4148 C1.1µF V S V S R 1M R 2k D1 1N4148 R4 k B 1/2 LT184 R3 1k 184 TA1 V OUT mv/div GND µs/div 184 TA2 1

2 ABSOLUTE MAXIMUM RATINGS W W W Total Supply Voltage (V to V ) V Input Current (Note 2)... ±ma Output Short-Circuit Duration (Note 3)... Indefinite Operating Temperature Range (Note 4).. C to 8 C Specified Temperature Range (Note )... C to 8 C Maximum Junction Temperature... C PACKAGE/ORDER INFORMATION U U W U (Note 1) Maximum Junction Temperature (DD Package).. 12 C Storage Temperature Range... C to C Storage Temperature Range (DD Package)... C to 12 C Lead Temperature (Soldering, sec)... 3 C V OUT 1 V 2 IN 3 TOP VIEW V 4 IN S PACKAGE -LEAD PLASTIC TSOT-23 T JMAX = C, θ JA = C/W TOP VIEW NC 1 8 NC IN 2 IN 3 V 4 7 V V OUT NC S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = 19 C/W ORDER PART NUMBER LT183CS LT183IS S PART MARKING* LTAFN ORDER PART NUMBER LT183CS8 LT183IS8 S8 PART MARKING I OUT A IN A IN A V TOP VIEW A B DD PACKAGE 8-LEAD (3mm 3mm) PLASTIC DFN T JMAX = 12 C, θ JA = C/W UNDERSIDE METAL INTERNALLY CONNECTED TO V (PCB CONNECTION OPTIONAL) 8 7 V OUT B IN B IN B OUT A 1 IN A 2 IN A 3 V 4 TOP VIEW A 8 7 S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = 19 C/W B V OUT B IN B IN B OUT A 1 IN A 2 IN A 3 V 4 IN B IN B OUT B 7 TOP VIEW A B D C S PACKAGE 14-LEAD PLASTIC SO 14 OUT D 13 IN D 12 IN D 11 V IN C 9 IN C 8 OUT C T JMAX = C, θ JA = C/W ORDER PART NUMBER LT184CDD LT184IDD DD PART MARKING* LADJ ORDER PART NUMBER LT184CS8 LT184IS8 Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grades are identified by a label on the shipping container. S8 PART MARKING I ORDER PART NUMBER LT18CS LT18IS 2

3 ELECTRICAL CHARACTERISTICS T A = 2 C; V S = V, V; V S = 3V, V; V CM = V OUT = half supply, unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = V.3 2 mv V CM = V (DD Package) 1. 3 mv V CM = V (SOT-23 Package) 1. mv V CM = V S 1. 8 mv V OS Input Offset Shift V CM = V to V S 2V.12. mv Input Offset Voltage Match V CM = V. 3. mv (Channel-to-Channel) (Note 9) V CM = V (DD Package) 1.. mv I B Input Bias Current V CM = 1V 12 7 na V CM = V S 3. µa Input Bias Current Match V CM = 1V 1 na (Channel-to-Channel) (Note 9) V CM = V S na I OS Input Offset Current V CM = 1V na V CM = V S na Input Noise Voltage.1Hz to Hz 4 µv P-P e n Input Noise Voltage Density f = khz 21 nv/ Hz i n Input Noise Current Density f = khz 2. pa/ Hz C IN Input Capacitance 2 pf A VOL Large-Signal Voltage Gain V S = V, V O =.V to 4.V, R L = 1k to V S /2 V/mV V S = V, V O = 1V to 4V, R L = Ω to V S / V/mV V S = 3V, V O =.V to 2.V, R L = 1k to V S /2 1 4 V/mV CMRR Common Mode Rejection Ratio V S = V, V CM = V to 3V 7 9 db V S = 3V, V CM = V to 1V 9 db CMRR Match (Channel-to-Channel) (Note 9) V S = V, V CM = V to 3V 9 91 db V S = 3V, V CM = V to 1V 8 db Input Common Mode Range V S V PSRR Power Supply Rejection Ratio V S = 2.V to V, V CM = V 8 9 db PSRR Match (Channel-to-Channel) (Note 9) V S = 2.V to V, V CM = V 2 9 db Minimum Supply Voltage (Note ) V V OL Output Voltage Swing Low (Note 7) No Load 17 mv I SINK = ma 8 mv I SINK = 1mA 18 3 mv V OH Output Voltage Swing High (Note 7) No Load 17 mv I SOURCE = ma 12 mv I SOURCE = 1mA 3 mv I SC Short-Circuit Current (Note 3) V S = V 42 ma V S = 3V ma I S Supply Current per Amplifier ma GBW Gain Bandwidth Product V S = V, Frequency = 2MHz, R L = 1k to 2.V 8 MHz SR Slew Rate V S = V, A V = 1, R L = 1k to V S /2, V O =.V to 4.V V/µs Measured at V O = 1.V, 3.V FPBW Full Power Bandwidth (Note ) V S = V, A V = 1, V O =.V to 4.V, R L = 1k to V S /2 8 MHz HD Harmonic Distortion V S = V, A V = 1, R L = 1k, V O = 2V P-P, f C = 1MHz 7 dbc t S Settling Time.1%, V S = V, V STEP = 2V, A V = 1, R L = 1k 3 ns G Differential Gain (NTSC) V S = V, A V = 2, R L = Ω.1 % θ Differential Phase (NTSC) V S = V, A V = 2, R L = Ω 1 Deg 3

4 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the C T A 7 C temperature range. V S = V, V; V S = 3V, V; V CM = V OUT = half supply unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = V. 3. mv V CM = V (DD Package) 1.2 mv V CM = V (SOT-23 Package) 1.2 mv V CM = V S mv V OS Input Offset Shift V CM = V to V S 2V..8 mv Input Offset Voltage Match V CM = V.7. mv (Channel-to-Channel) (Note 9) V CM = V (DD Package) mv V OS TC Input Offset Voltage Drift (Note 8) 3 µv/ C I B Input Bias Current V CM = 1V 1 na V CM = V S.2V 3.2 µa Input Bias Current Match V CM = 1V 1 na (Channel-to-Channel) (Note 9) V CM = V S.2V 1 18 na I OS Input Offset Current V CM = 1V 1 na V CM = V S.2V 1 na A VOL Large-Signal Voltage Gain V S = V, V O =.V to 4.V, R L = 1k to V S /2 1 V/mV V S = V, V O = 1V to 4V, R L = Ω to V S / V/mV V S = 3V, V O =.V to 2.V, R L =1k to V S /2 V/mV CMRR Common Mode Rejection Ratio V S = V, V CM = V to 3V 71 9 db V S = 3V, V CM = V to 1V 1 9 db CMRR Match (Channel-to-Channel) (Note 9) V S = V, V CM = V to 3V 9 db V S = 3V, V CM = V to 1V 8 db Input Common Mode Range V S V PSRR Power Supply Rejection Ratio V S = 2.V to V, V CM = V 87 db PSRR Match (Channel-to-Channel) (Note 9) V S = 2.V to V, V CM = V 9 87 db Minimum Supply Voltage (Note ) V V OL Output Voltage Swing Low (Note 7) No Load 19 8 mv I SINK = ma 22 mv I SINK = 1mA mv V OH Output Voltage Swing High (Note 7) No Load 19 8 mv I SOURCE = ma 3 mv I SOURCE = 1mA 9 mv I SC Short-Circuit Current (Note 3) V S = V 17 ma V S = 3V 1 28 ma I S Supply Current per Amplifier ma GBW Gain Bandwidth Product V S = V, Frequency = 2MHz, R L = 1k to 2.V 4 82 MHz SR Slew Rate V S = V, A V = 1, R L = 1k to V S /2, V O =.V to 4.V 4 93 V/µs Measured at V O = 1.V, 3.V 4

5 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the C T A 8 C temperature range. V S = V, V; V S = 3V, V; V CM = V OUT = half supply unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = V.7 4 mv V CM = V (DD Package) 1.. mv V CM = V (SOT-23 Package) 1. 7 mv V CM = V S mv V OS Input Offset Shift V CM = V to V S 2V mv Input Offset Voltage Match V CM = V 1. mv (Channel-to-Channel) (Note 9) V CM = V (DD Package) 2 9 mv V OS TC Input Offset Voltage Drift (Note 8) 3 µv/ C I B Input Bias Current V CM = 1V na V CM = V S.2V 3.4. µa Input Bias Current Match V CM = 1V na (Channel-to-Channel) (Note 9) V CM = V S.2V 2 na I OS Input Offset Current V CM = 1V na V CM = V S.2V na A VOL Large-Signal Voltage Gain V S = V, V O =.V to 4.V, R L = 1k to V S / V/mV V S = V, V O = 1.V to 3.V, R L = Ω to V S / V/mV V S = 3V, V O =.V to 2.V, R L =1k to V S /2 8 3 V/mV CMRR Common Mode Rejection Ratio V S = V, V CM = V to 3V 9 9 db V S = 3V, V CM = V to 1V 9 db CMRR Match (Channel-to-Channel) (Note 9) V S = V, V CM = V to 3V 3 9 db V S = 3V, V CM = V to 1V 4 8 db Input Common Mode Range V S V PSRR Power Supply Rejection Ratio V S = 2.V to V, V CM = V 4 8 db PSRR Match (Channel-to-Channel) (Note 9) V S = 2.V to V, V CM = V 8 8 db Minimum Supply Voltage (Note ) V V OL Output Voltage Swing Low (Note 7) No Load 9 mv I SINK = ma mv I SINK = ma 17 3 mv V OH Output Voltage Swing High (Note 7) No Load 9 mv I SOURCE = ma 17 mv I SOURCE = ma 3 mv I SC Short-Circuit Current (Note 3) V S = V 12 3 ma V S = 3V ma I S Supply Current per Amplifier ma GBW Gain Bandwidth Product V S = V, Frequency = 2MHz, R L = 1k to 2.V 77 MHz SR Slew Rate V S = V, A V = 1, R L = 1k to V S /2, V O =.V to 4.V 3 7 V/µs Measured at V O = 1.V, 3.V

6 ELECTRICAL CHARACTERISTICS T A = 2 C,, V CM = V, V OUT = V, unless otherwise noted SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = V.3 2. mv V CM = V (DD Package) mv V CM = V (SOT-23 Package) 1. mv V CM = V 1. 8 mv V OS Input Offset Shift V CM = V to 3V.3 1 mv Input Offset Voltage Match V CM = V. 4 mv (Channel-to-Channel) (Note 9) V CM = V (DD Package) 1. mv I B Input Bias Current V CM = 4V 12 7 na V CM = V 2.. µa Input Bias Current Match V CM = 4V 1 na (Channel-to-Channel) (Note 9) V CM = V na I OS Input Offset Current V CM = 4V na V CM = V na Input Noise Voltage.1Hz to Hz 4 µv P-P e n Input Noise Voltage Density f = khz 21 nv/ Hz i n Input Noise Current Density f = khz 2. pa/ Hz C IN Input Capacitance f = khz 2 pf A VOL Large-Signal Voltage Gain V O = 4V to 4V, R L = 1k V/mV V O = 1.V to 1.V, R L = Ω 2 V/mV CMRR Common Mode Rejection Ratio V CM = V to 3V 78 9 db CMRR Match (Channel-to-Channel) (Note 9) V CM = V to 3V 72 9 db Input Common Mode Range V S V S V PSRR Power Supply Rejection Ratio V S = 2.V to V, V S = V, V OUT = V S /2 8 9 db PSRR Match (Channel-to-Channel) (Note 9) V S = 2.V to V, V S = V, V OUT = V S /2 2 9 db V OL Output Voltage Swing Low (Note 7) No Load 17 mv I SINK = ma 8 mv I SINK = 1mA 3 mv V OH Output Voltage Swing High (Note 7) No Load 17 mv I SOURCE = ma 12 mv I SOURCE = 1mA 3 mv I SC Short-Circuit Current (Note 3) 2 ma I S Supply Current per Amplifier 2. 3 ma GBW Gain Bandwidth Product Frequency = 2MHz, R L = 1k 83 MHz SR Slew Rate A V = 1, R L = 1k, V O = ±4V 88 V/µs Measured at V O = ±2V FPBW Full Power Bandwidth (Note ) V O = 8V P-P, A V = 1, R L = 1k 4 MHz HD Harmonic Distortion A V = 1, R L = 1k, V O = 2V P-P, f C = 1MHz 7 dbc t S Settling Time.1%, V STEP = V, A V = 1, R L = 1k ns G Differential Gain (NTSC) A V = 2, R L = Ω.7 % θ Differential Phase (NTSC) A V = 2, R L = Ω.8 Deg

7 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the C T A 7 C temperature range., V CM = V, V OUT = V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = V. 3. mv V CM = V (DD Package) 1. mv V CM = V (SOT-23 Package) 1. 7 mv V CM = V mv V OS Input Offset Shift V CM = V to 3V.3 1. mv Input Offset Voltage Match V CM = V.7. mv (Channel-to-Channel) (Note 9) V CM = V (DD Package) mv V OS TC Input Offset Voltage Drift (Note 8) 3 µv/ C I B Input Bias Current V CM = 4V 17 na V CM = 4.8V 2. µa Input Bias Current Match V CM = 4V 17 na (Channel-to-Channel) (Note 9) V CM = 4.8V na I OS Input Offset Current V CM = 4V 1 na V CM = 4.8V 1 na A VOL Large-Signal Voltage Gain V O = 4V to 4V, R L = 1k 1 47 V/mV V O = 1.V to 1.V, R L = Ω V/mV CMRR Common Mode Rejection Ratio V CM = V to 3V 74 9 db CMRR Match (Channel-to-Channel) (Note 9) V CM = V to 3V 8 9 db Input Common Mode Range V S V S V PSRR Power Supply Rejection Ratio V S = 2.V to V, V S = V, V OUT = V S /2 87 db PSRR Match (Channel-to-Channel) (Note 9) V S = 2.V to V, V S = V, V OUT = V S / db V OL Output Voltage Swing Low (Note 7) No Load 19 8 mv I SINK = ma 22 mv I SINK = 1mA 2 47 mv V OH Output Voltage Swing High (Note 7) No Load 19 8 mv I SOURCE = ma 3 mv I SOURCE = 1mA 9 mv I SC Short-Circuit Current (Note 3) 4 ma I S Supply Current per Amplifier ma GBW Gain Bandwidth Product Frequency = 2MHz, R L = 1k 8 MHz SR Slew Rate A V = 1, R L = 1k, V O = ±4V, 84 V/µs Measured at V O = ±2V 7

8 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the C T A 8 C temperature range., V CM = V, V OUT = V unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OS Input Offset Voltage V CM = V 1 4. mv V CM = V (DD Package) 2. mv V CM = V (SOT-23 Package) 2 8 mv V CM = V 2 9 mv V OS Input Offset Shift V CM = V to 3V mv Input Offset Voltage Match V CM = V 1. mv (Channel-to-Channel) (Note 9) V CM = V (DD Package) 2 9. mv V OS TC Input Offset Voltage Drift (Note 8) 3 µv/ C I B Input Bias Current V CM = 4V na V CM = 4.8V 2.. µa Input Bias Current Match V CM = 4V na (Channel-to-Channel) (Note 9) V CM = 4.8V 2 na I OS Input Offset Current V CM = 4V na V CM = 4.8V na A VOL Large-Signal Voltage Gain V O = 4V to 4V, R L = 1k 12 4 V/mV V O = 1V to 1V, R L = Ω V/mV CMRR Common Mode Rejection Ratio V CM = V to 3V 73 9 db CMRR Match (Channel-to-Channel) (Note 9) V CM = V to 3V 7 9 db Input Common Mode Range V S V S V PSRR Power Supply Rejection Ratio V S = 2.V to V, V S = V, V OUT = V S /2 4 8 db PSRR Match (Channel-to-Channel) (Note 9) V S = 2.V to V, V S = V, V OUT = V S /2 8 8 db V OL Output Voltage Swing Low (Note 7) No Load 9 mv I SINK = ma 1 mv I SINK = ma 17 3 mv V OH Output Voltage Swing High (Note 7) No Load 9 mv I SOURCE = ma 17 mv I SOURCE = ma 3 mv I SC Short-Circuit Current (Note 3) ma I S Supply Current per Amplifier ma GBW Gain Bandwidth Product Frequency = 2MHz, R L = 1k 7 MHz SR Slew Rate A V = 1, R L = 1k, V O = ±4V, V/µs Measured at V O = ±2V Note 1: Absolute Maximium Ratings are those values beyond which the life of the device may be impaired. Note 2: The inputs are protected by back-to-back diodes and by ESD diodes to supply rails. If the differential input voltage exceeds 1.4V, or if an input is driven beyond the supply rails, the input current should be limited to less than ma. This parameter is not tested; however it is guaranteed by characterization. Note 3: A heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted indefinitely. Note 4: The LT183C/LT183I, LT184C/LT184I and LT18C/LT18I are guaranteed functional over the temperature range of C and 8 C. Note : The LT183C/LT184C/LT18C are guaranteed to meet specified performance from C to 7 C. The LT183C/LT184C/LT18C are designed, characterized and expected to meet specified performance from 8 C to 8 C but are not tested or QA sampled at these temperatures. The LT183I/LT184I/LT18I are guaranteed to meet specified performance from C to 8 C. Note : Minimum supply voltage is guaranteed by power supply rejection ratio test. Note 7: Output voltage swings are measured between the output and power supply rails. Note 8: This parameter is not % tested. Note 9: Matching parameters are the difference between amplifiers A and D and between B and C on the LT18; between the two amplifiers on the LT184. Note : Full power bandwidth is based on slew rate: FPBW = SR/2πV P

9 TYPICAL PERFOR A CE CHARACTERISTICS UW PERCENT OF UNITS (%) V OS Distribution, V CM = V (SO-8, PNP Stage) V S = V, V V CM = V PERCENT OF UNITS (%) V OS Distribution, V CM = V (SO-8, NPN Stage) V S = V, V V CM = V PERCENT OF UNITS (%) V OS Distribution, V CM = V (SOT-23, PNP Stage) V S = V, V V CM = V INPUT OFFSET VOLTAGE (µv) INPUT OFFSET VOLTAGE (mv) INPUT OFFSET VOLTAGE (mv) 1834 G G G3 2 V OS Distribution, V CM = V (SOT-23, NPN Stage) V S = V, V V CM = V Supply Current vs Supply Voltage PER AMPLIFIER Offset Voltage vs Input Common Mode Voltage V S = V, V TYPICAL PART PERCENT OF UNITS (%) 1 SUPPLY CURRENT (ma) T A = 12 C T A = 2 C T A = C OFFSET VOLTAGE (µv) T A = 12 C T A = 2 C T A = C INPUT OFFSET VOLTAGE (mv) TOTAL SUPPLY VOLTAGE (V) INPUT COMMON MODE VOLTAGE (V) 1834 G G 1834 G INPUT BIAS CURRENT (µa) Input Bias Current vs Common Mode Voltage V S = V, V T A = C T A = 2 C T A = 12 C INPUT BIAS CURRENT (µa) Input Bias Current vs Temperature NPN ACTIVE V S = V, V V CM = V PNP ACTIVE V S = V, V V CM = 1V OUTPUT SATURATION VOLTAGE (V) Output Saturation Voltage vs Load Current (Output Low) V S = V, V T A = 2 C T A = C T A = 12 C COMMON MODE VOLTAGE (V) TEMPERATURE ( C) LOAD CURRENT (ma) 1834 G G G9 9

10 TYPICAL PERFOR A CE CHARACTERISTICS UW OUTPUT SATURATION VOLTAGE (V) Output Saturation Voltage vs Load Current (Output High) V S = V, V T A = 2 C T A = 12 C T A = C CHANGE IN OFFSET VOLTAGE (mv) Minimum Supply Voltage T A = 2 C T A = C V CM = V T A = 12 C OUTPUT SHORT-CIRCUIT CURRENT (ma) 8 Output Short-Circuit Current vs Power Supply Voltage SINKING T A = 2 C T A = C SOURCING T A = 12 C T A = C T A = 12 C T A = 2 C LOAD CURRENT (ma) 1834 G TOTAL SUPPLY VOLTAGE (V) 1834 G POWER SUPPLY VOLTAGE (±V) 1834 G Open-Loop Gain V S = 3V, V R L TO GND Open-Loop Gain V S = V, V R L TO GND 8 Open-Loop Gain R L TO GND INPUT VOLTAGE (mv) R L = Ω R L = 1k INPUT VOLTAGE (mv) R L = Ω R L = 1k INPUT VOLTAGE (mv) R L = Ω R L = 1k OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1834 G G G1 CHANGE IN OFFSET VOLTAGE (mv) Offset Voltage Change vs Output Current T A = 2 C T A = 12 C T A = C 8 OUTPUT CURRENT (ma) CHANGE IN OFFSET VOLTAGE (µv) 1 1 Warm-Up Drift vs Time (LT184S8) V S = 3V V S = V TIME AFTER POWER-UP (SECONDS) INPUT NOISE VOLTAGE (nv/ Hz) Input Noise Voltage vs Frequency.1 NPN ACTIVE V CM = 4.2V PNP ACTIVE V CM = 2.V V S = V, V.1 1 FREQUENCY (khz) 1834 G G G18

11 TYPICAL PERFOR A CE CHARACTERISTICS INPUT NOISE CURRENT (pa/ Hz) Input Current Noise vs Frequency.1 NPN ACTIVE V CM = 4.2V PNP ACTIVE V CM = 2.V UW V S = V, V.1 1 FREQUENCY (khz) INPUT NOISE VOLTAGE (µv) Hz to Hz Voltage Noise V S = V, V TIME (SECONDS) GAIN BANDWIDTH (MHz) PHASE MARGIN (DEG) Gain Bandwidth and Phase Margin vs Supply Voltage T A = 2 C GAIN BANDWIDTH PRODUCT PHASE MARGIN TOTAL SUPPLY VOLTAGE (V) 1834 G G 1834 G21 GAIN BANDWIDTH (MHz) PHASE MARGIN (DEG) Gain Bandwidth and Phase Margin vs Temperature Slew Rate vs Temperature Gain and Phase vs Frequency GAIN BANDWIDTH PHASE MARGIN V S = ±2.V V S = ±2.V TEMPERATURE ( C) TEMPERATURE ( C) 1834 G22 SLEW RATE (V/µs) V S = ±2.V A V = 1 R F = R G = 1k R L = 1k 1834 G23 GAIN (db) 1 8 PHASE 1 GAIN T A = 2 C C L = pf 18 R L = 1k V S = ±2.V FREQUENCY (MHz) 1834 G PHASE SHIFT (DEG) GAIN (db) Gain vs Frequency (A V = 1) Gain vs Frequency (A V = 2) Output Impedance vs Frequency C L = pf R L = Ω A V = 1 V S = ±2.V FREQUENCY (MHz) 1834 G2 GAIN (db) 3 C L = pf 24 R L = Ω 18 A V = 2 12 V S = ±2.V FREQUENCY (MHz) 1834 G2 OUTPUT IMPEDANCE (Ω) V S = ±2.V A V = A V = 2 A V = FREQUENCY (khz) 1834 G27 11

12 TYPICAL PERFOR A CE CHARACTERISTICS UW COMMON MODE REJECTION RATIO (db) 8 Common Mode Rejection Ratio vs Frequency V S = V, V R L = 1kΩ T A = 2 C FREQUENCY (MHz) 1834 G28 POWER SUPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency NEGATIVE SUPPLY POSITIVE SUPPLY V S = V, V T A = 2 C FREQUENCY (MHz) 1834 G29 OVERSHOOT (%) Overshoot and Series Output Resistor vs Capacitive Load (A V = 1) V S = V, V A V = 1 R S = Ω, R L = Ω R S = Ω CAPACITIVE LOAD (pf) 1834 G3 OVERSHOOT (%) Overshoot and Series Output Resistor vs Capacitive Load (A V = 2) Distortion vs Frequency (A V = 1) Distortion vs Frequency (A V = 2) V S = V, V A V = 2 C F = pf R G = 1k R F = 1k R S = Ω, R L = Ω R S = Ω CAPACITIVE LOAD (pf) DISTORTION (dbc) V S = V, V A V = 1 V OUT = 2V P-P V CM = 2V R L = Ω, 2ND 7 R L = Ω, 2ND 8 R L = Ω, 3RD R L = 1kΩ, 2ND 9 R L = 1kΩ, 2ND R L = 1kΩ, 3RD R L = 1kΩ, 3RD FREQUENCY (MHz) FREQUENCY (MHz) 1834 G G32 DISTORTION (dbc) 3 V S = V, V A V = 2 V OUT = 2V P-P R L = Ω, 3RD 1834 G33.2 Maximum Undistorted Output Signal vs Frequency V Large-Signal Response V Small-Signal Response OUTPUT VOLTAGE SWING (V P-P ) V S = V, V T A = 2 C HD 2, HD 3 < dbc A V = 2 A V = FREQUENCY (MHz) 1V/DIV V V S = V, V A V = 1 R L = 1k ns/div 1834 G3 mv/div 2.V V S = V, V A V = 1 R L = 1k ns/div 1834 G G34 12

13 TYPICAL PERFOR A CE CHARACTERISTICS UW ±V Large-Signal Response ±V Small-Signal Response Output Overdrive Recovery V 2V/DIV mv/div V V IN 1V/DIV V V OUT 2V/DIV A V = 1 R L = 1k ns/div 1834 G37 A V = 1 R L = 1k ns/div 1834 G38 V S = V, V A V = 2 R L = 1k ns/div 1834 G39 APPLICATIO S I FOR ATIO Circuit Description U W U U The have input and output signal ranges from the negative power supply to the positive power supply. Figure 1 depicts a simplified schematic of one amplifier. The input stage is comprised of two differential amplifiers, a PNP stage Q1/Q2 and an NPN stage Q3/ Q4 that are active over the different ranges of the common mode input voltage. The PNP differential pair is active between the negative supply and approximately 1.3V below the positive supply. As the input voltage moves toward the positive supply, the transistor Q will steer the tail current I 1 to the current mirror Q/Q7 activating the NPN differential pair. The PNP pair becomes inactive for the rest of the input common mode range up to the positive supply. Also at the input stage, devices Q18 and Q19 act to cancel the bias current of the PNP input pair. When Q1 and Q2 are active, the current in Q1 is controlled to be the same as the current in Q1 and Q2; therefore, the base current of Q1 is nominally equal to the base current of the input devices. The base current of Q1 is then mirrored by devices Q17 through Q19 to cancel the base current of the input devices Q1 and Q2. A pair of complementary common emitter stages Q14/ Q1 that enable the output to swing from rail-to-rail constructs the output stage. The capacitors C1 and C2 form the local feedback loops that lower the output impedance at high frequency. The are fabricated on Linear Technology s proprietary high speed complementary bipolar process. Power Dissipation There is a need to ensure that the die s junction temperature does not exceed C. Junction temperature T J is calculated from the ambient temperature T A, power dissipation P D and thermal resistance θ JA : T J = T A (P D θ JA ) The power dissipated in the IC is a function of the supply voltage, amplifier current, output voltage and output current. For a given supply voltage, the worst-case power dissipation, P DMAX, occurs when the output current and voltage drop in the amplifier product is maximized. For example, if the amplifier is sourcing a constant current then the P DMAX occurs when the output voltage is at about V S. On the other hand, for a given load resistance to ground, the P DMAX will occur when the output voltage is at half of either supply voltage. P DMAX for a given resistance to ground is given by: P DMAX = (V S V S ) I SMAX (V S /2) 2 /R L Example: An LT184 in an SO-8 package operating on ±V supplies and driving a Ω load to ground, the P DMAX per amplifier is given by: P DMAX = ( 3.2mA) (2.) 2 / =.42.2 =.9W I SMAX is approximated for a typical part from the Supply Currrent vs Supply Voltage graph. 13

14 APPLICATIO S I FOR ATIO V U W U U R3 R4 R V V I 2 IN ESDD1 ESDD2 D D D8 D7 D1 D2 Q V BIAS I 1 Q11 Q12 C C V Q13 I 3 C2 Q1 OUT IN Q4 Q3 Q1 Q2 Q1 Q17 ESDD4 Q18 V ESDD3 V Q19 Q7 Q D3 D4 Q Q9 Q8 BUFFER AND OUTPUT BIAS C1 Q14 V R1 R F1 Figure 1. Simplified Schematic Diagram If both amplifiers are loaded simultaneously, then the total power dissipation is.19w. The maximum ambient temperature that the part is allowed to operate is: T A = T J (P DMAX 19 C/W) = C (.19W 19 C/W) = C Similar calculations can be carried out for specific packages and conditions. Also worth noting, the DD package includes a low θ JA underside metal which is internally connected to V S. If the underside metal is properly soldered to a PCB, the θ JA of the part will be close to C/W. This θ JA is significantly less than leaving the underside metal unattached and can be useful for certain applications. Input Offset Voltage The input offset voltage will change greatly based upon which input stage is active. The PNP input stage is active from the negative supply voltage to about 1.3V below the positive supply rail, then the NPN input stage is activated for the remaining input range up to the positive supply rail during which the PNP stage remains inactive. The offset 14 voltage is typically less than µv in the range the PNP input stage is active. Input Bias Current The employ a patent-pending technique to reduce the input bias current to less than 1µA for the input common mode voltage range of.2v above the negative supply rail to 1.7V below the positive rail. The low input offset voltage and low input bias current provide precision performance in high source impedance applications. Output The can deliver a large output current, so the short-circuit current limit is set around ma to prevent damage to the device. Attention must be paid to keep the junction temperature of the IC below the absolute maximum rating of C (refer to the Power Dissipation section) when the output is continuously short circuited. The output of the amplifier has reverse-biased diodes connected to each supply. If the output is forced beyond either supply, unlimited current will flow through these diodes. If the current is transient and limited to less than ma and the total supply voltage is less than

15 APPLICATIO S I FOR ATIO U W U U 12.V, the absolute maximum rating, no damage will occur to the device. Overdrive Protection When the input voltage exceeds the power supplies, two pairs of crossing diodes D1 through D4 will prevent the output from reversing polarity. If the input voltage exceeds either power supply by 7mV, diode D1/D2 or D3/D4 will turn on to keep the output at the proper polarity. For the phase reversal protection to perform properly, the input current must be limited to less than ma. If the amplifier is severely overdriven, an external resistor should be used to limit the overdrive current. The s input stages are also protected against a large differential input voltage of 1.4V or higher by a pair of back-to-back diodes D through D8 to prevent the emitter-base breakdown of the input transistors. The current in these diodes should be limited to less than ma when they are active. The worst-case differential input voltage usually occurs when the input is driven while the output is shorted to ground in a unity gain configuration. In addition, the amplifier is protected against ESD strikes up to 3kV on all pins by a pair of protection diodes on each pin that is connected to the power supplies as shown in Figure 1. Capacitive Load The are optimized for wide bandwidth, low power and precision applications. They can drive a capacitive load of about pf in a unity-gain configuration, and more for higher gain. When driving a larger capacitive load, a resistor of Ω to Ω should be connected between the output and the capacitive load to avoid ringing or oscillation. The feedback should still be taken from the output so that the resistor will isolate the capacitive load to ensure stability. Graphs on capacitive load indicate the transient response of the amplifier when driving a capacitive load with a specified resistor. Feedback Components When feedback resistors are used to set up gain, care must be taken to ensure that the pole formed by the feedback resistors and the total capacitance at the inverting input does not degrade stability. For instance, the LT183/ LT184/LT18 in a noninverting gain of 2 setup with two k resistors and a capacitance of pf (part plus PC board) will probably oscillate. The pole formed at 12.7MHz, reduces phase margin by about 8 degrees when the crossover frequency of the amplifier is around MHz. A capacitor of pf or higher connected across the feedback resistor will eliminate any ringing or oscillation. 1

16 PACKAGE DESCRIPTIO U S Package -Lead Plastic TSOT-23 (Reference LTC DWG # -8-13).2 MAX.9 REF 2.9 BSC (NOTE 4) 1.22 REF 3.8 MAX 2.2 REF 1.4 MIN 2.8 BSC (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR.9 BSC.3.4 TYP PLCS (NOTE 3).8.9. BSC DATUM A 1. MAX REF BSC NOTE: (NOTE 3) S TSOT DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR. MOLD FLASH SHALL NOT EXCEED.24mm. JEDEC PACKAGE REFERENCE IS MO-193 1

17 PACKAGE DESCRIPTIO U DD Package 8-Lead Plastic DFN (3mm 3mm) (Reference LTC DWG # ).7 ±. 3. ±. 2.1 ±. 1. ±. (2 SIDES) PACKAGE OUTLINE.28 ±.. BSC 2.38 ±. (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R =.11 TYP 8.38 ±. PIN 1 TOP MARK 3. ±. (4 SIDES) 1. ±. (2 SIDES). REF.7 ± ± ±. (2 SIDES) BOTTOM VIEW EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M-229 VARIATION OF (WEED-1) 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.1mm ON ANY SIDE 4. EXPOSED PAD SHALL BE SOLDER PLATED 1. BSC (DD8) DFN 3 17

18 PACKAGE DESCRIPTIO U S8 Package 8-Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # -8-1). BSC.4 ± (4.81.4) NOTE MIN. ± ( )..17 ( ) NOTE 3.3 ±. TYP RECOMMENDED SOLDER PAD LAYOUT (.3.24).. (.24.8) 4 8 TYP.3.9 ( ).4. (.1.24).1. (. 1.27) NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) (.3.483) TYP 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED." (.1mm). (1.27) BSC SO

19 PACKAGE DESCRIPTIO U S Package 14-Lead Plastic Small Outline (Narrow. Inch) (Reference LTC DWG # -8-1). BSC.4 ± ( ) NOTE 3 N MIN N/2. ± ( ) N N/2..17 ( ) NOTE 3.3 ±. TYP RECOMMENDED SOLDER PAD LAYOUT (.3.24).. (.24.8) 4 8 TYP.3.9 ( ).4. (.1.24).1. (. 1.27) NOTE: INCHES 1. DIMENSIONS IN (MILLIMETERS) (.3.483) TYP 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED." (.1mm). (1.27) BSC S14 2 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19

20 TYPICAL APPLICATIO U LED Array Driver ma Pulse Response of LED Array Driver V IN 3.1k 3 332Ω 2 V 7 LT183 4 Ω 27pF 332Ω I OUT = V IN 1A (NOT CURRENT LIMITED UNDER SHORT-CIRCUIT CONDITIONS) V INTERNATIONAL RECTIFIER IRLL333 I OUT 2 FOOT WIRE V SENSE R SENSE.1Ω SCANNER LED ARRAY RATED ma AT V 183 TAO3a PIN 3 V V SENSE V PIN FET SOURCE V 183 TA3b RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1399 Triple 3MHz Current Feedback Amplifier.1dB Gain Flatness to MHz, Shutdown LT1498/LT1499 Dual/Quad MHz, Vµs Rail-to-Rail Input and Output High DC Accuracy, 47µV V OS(MAX), 4µV/ C Max Drift, C-Load TM Op Amps Max Supply Current 2.2mA per Amp LT13/LT131 Dual/Quad 3MHz, V/µs Rail-to-Rail Input and Output Op Amps High DC Accuracy, 2µV V OS(MAX), 7mA Output Current, Max Supply Current 4.4mA per Amplifier LT18/LT181 Single/Dual/Quad 8MHz, 2V/µs Low Power Rail-to-Rail High DC Accuracy, 3µV V OS(MAX), Max Supply Currrent LT182 Input/Output Precision Op Amps 2mA per Amplifier LT18/LT187 Single/Dual 32MHz, 1V/µs Rail-to-Rail Input/Output Amps High DC Accuracy, µv V OS(MAX), Low Noise 3.nV/ Hz, Low Distortion 8dB at MHz, Power-Down (LT18) LT189/LT18 Single/Dual 18MHz Rail-to-Rail Input/Output Op Amps 3V/µs Slew Rate, Low Distortion 9dB at MHz, Power-Down (LT189) LT/LT1 Single/Dual Ultralow Noise Rail-to-Rail Amplifier.9nV/Hz, 1MHz Gain Bandwidth, 44V/µs LT- Single Ultralow Noise Rail-to-Rail Amplifier.9nV/Hz, 8MHz Gain Bandwidth, 2V/µs, A V LT- Single Ultralow Noise Rail-to-Rail Amplifier.9nV/Hz, 1.GHz Gain Bandwidth, 3V/µs, A V LT2/LT3 Single/Dual/Quad 9MHz, 24V/µs Rail-to-Rail Input/Output, High DC Accuracy, µv V OS(MAX), Max Supply Currrent LT4 Ultralow 1.9nV/ Hz Noise, Low Power Op Amps 3mA per Amplifier C-Load is a trademark of Linear Technology Corporation. Linear Technology Corporation 13 McCarthy Blvd., Milpitas, CA (8) FAX: (8) LT/TP 83 1K PRINTED IN THE USA LINEAR TECHNOLOGY CORPORATION 3