LT Dual 200MHz, 30V/µs 16-Bit Accurate A V 2 Op Amp DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION

Size: px

Start display at page:

Download "LT Dual 200MHz, 30V/µs 16-Bit Accurate A V 2 Op Amp DESCRIPTION FEATURES APPLICATIONS TYPICAL APPLICATION"

Jasmin Miles
5 years ago
Views:

1 FEATURES n Stable in Gain A (A = ) n MHz Gain Bandwidth Product n /μs Slew Rate n Settling Time: 8ns (μ, Step) n Specifi ed at and Supplies n Maximum Input Offset oltage: μ n Low Distortion: 9. for khz, P-P n Maximum Input Offset oltage Drift: μ/ C n Maximum Inverting Input Bias Current: na n Minimum DC Gain: /m n Minimum Output Swing into k: ±.8 n Input Noise oltage: n/ Hz n Input Noise Current:.pA/ Hz n Total Input Noise Optimized for kω < R S < kω n Available in 8-Lead Plastic SO and -Lead (mm mm) DFN Packages APPLICATIONS n Precision Instrumentation n High Accuracy Data Acquisition Systems n -Bit DAC Current-to-oltage Converter n ADC Buffer n Low Distortion Active Filters n Photodiode Amplifi ers DESCRIPTION LT9- Dual MHz, /µs -Bit Accurate A Op Amp The LT 9- is a dual, precision high speed operational amplifier with -bit accuracy, decompensated to be stable in a gain of or greater. The combination of precision and AC performance makes the LT9- the optimum choice for high accuracy applications such as DAC current-to-voltage conversion and ADC buffers. The initial accuracy and drift characteristics of the input offset voltage and inverting input bias current are tailored for inverting applications. The MHz gain bandwidth ensures high open-loop gain at frequency for reducing distortion. In noninverting applications such as an ADC buffer, the low distortion and DC accuracy allow full -bit AC and DC performance. The high slew rate of the LT9- improves large-signal performance in applications such as active filters and instrumentation amplifiers compared to other precision op amps. The LT9- is specified on power supply voltages of and and from C to 8 C. It is available in an 8-lead SOIC package and a space saving mm mm leadless package. For a unity-gain stable op amp with same DC performance, see the LT9 datasheet. L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION -Bit DAC I-to- Converter Large-Signal Transient, A = DAC INPUTS LTC 97 k pf / LT9- OFFSET: OS + I B (kω) < LSB OPTIONAL NOISE FILTER SETTLING TIME TO μ =.μs SETTLING LIMITED BY k AND pf TO COMPENSATE DAC OUTPUT CAPACITANCE + k OUT pf /DI 9 TAa ns/di S = A = R F = R G = k C F = pf 9 TA 9f

2 LT9- ABSOLUTE MAXIMUM RATINGS (Note ) Total Supply oltage ( + to )... Input Current (Note )...± Output Short-Circuit Duration (Note )... Indefinite Operating Temperature Range (Note )... C to 8 C Specified Temperature Range (Note )... C to 8 C Maximum Junction Temperature... C Storage Temperature Range... C to C PIN CONFIGURATION TOP IEW OUT A + IN A OUT B A +IN A IN B B 9 +IN B N/C N/C 8 7 N/C N/C OUT A IN A +IN A A TOP IEW B OUT B IN B +IN B DF PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = 7 C/W EXPOSED PAD (PIN ) IS GND, MUST BE CONNECTED TO S8 PACKAGE 8-LEAD PLASTIC SO T JMAX = C, θ JA = 9 C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT9CS8-#PBF LT9CS8-#TRPBF 9 8-Lead Plastic Small Outline C to 7 C LT9IS8-#PBF LT9IS8-#TRPBF 9 8-Lead Plastic Small Outline C to 8 C LT9ACDF-#PBF LT9ACDF-#TRPBF 9 -Lead (mm mm) Plastic DFN C to 7 C LT9AIDF-#PBF LT9AIDF-#TRPBF 9 -Lead (mm mm) Plastic DFN C to 8 C LT9CDF-#PBF LT9CDF-#TRPBF 9 -Lead (mm mm) Plastic DFN C to 7 C LT9IDF-#PBF LT9IDF-#TRPBF 9 -Lead (mm mm) Plastic DFN C to 8 C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: For more information on tape and reel specifi cations, go to: ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. CM = unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS OS Input Offset oltage S8 Package LT9A, DF Package LT9, DF Package I OS Input Offset Current to ± na μ μ μ μ μ μ 9f

3 LT9- ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at. CM = unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS I B Inverting Input Bias Current to ± na I B + Noninverting Input Bias Current to ± na Input Noise oltage.hz to Hz to. μ P-P e n Input Noise oltage Density f = khz to n/ Hz i n Input Noise Current Density f = khz to. pa/ Hz R IN Input Resistance Common Mode, CM = ±. Differential C IN Input Capacitance pf CM Input oltage Range (Positive) Guaranteed by CMRR Input oltage Range (Negative) Guaranteed by CMRR CMRR Common Mode Rejection Ratio CM = ±. CM = ±. Minimum Supply oltage Guaranteed by PSRR ±. ±. PSRR Power Supply Rejection Ratio S = ±. to A OL Large-Signal oltage Gain OUT = ±., R L = k OUT = ±., R L = k OUT = ±., R L = k OUT = ±., R L = k OUT Maximum Output Swing R L = k, m Overdrive R L = k, m Overdrive R L = k, m Overdrive R L = k, m Overdrive I OUT Maximum Output Current OUT = ±., m Overdrive OUT = ±., m Overdrive I SC Output Short-Circuit Current OUT =,. Overdrive (Note ) ± ± SR Slew Rate R L = k (Note ) FPBW Full-Power Bandwidth Peak, (Note 7) Peak, (Note 7) GBW Gain Bandwidth Product f = khz, R L = k t S Settling Time Step,.%, A = Step, μ, A = R OUT Output Resistance A =, f = khz. Ω Channel Separation OUT = ±., R L = k OUT = ±., R L = k I S Supply Current Per Amplifi er Δ OS Input Offset oltage Match ΔI B Inverting Input Bias Current Match to 8 na ΔI B + Noninverting Input Bias Current Match to 78 na ΔCMRR Common Mode Rejection Match CM = ±. (Note 9) CM = ±. (Note 9) ΔPSRR Power Supply Rejection Match S = ±. to (Note 9) ±. ±.8 ±. ±.8 ± ± ±. ±. ±.7 ±. ± ± MΩ kω /m /m /m /m /μs /μs khz khz MHz MHz ns ns μ μ 9f

4 LT9- ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, C T A 7 C. CM = unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS OS Input Offset oltage S8 Package LT9A, DF Package LT9, DF Package Δ OS /ΔT Input Offset oltage Drift (Note 8) I OS Input Offset Current to ±8 na ΔI OS /ΔT Input Offset Current Drift (Note 8) to pa/ C I B Inverting Input Bias Current to ± na ΔI B /ΔT Inverting Input Bias Current Drift (Note 8) to pa/ C I B + Noninverting Input Bias Current to ± na CM Input oltage Range (Positive) Guaranteed by CMRR Input oltage Range (Negative) Guaranteed by CMRR CMRR Common Mode Rejection Ratio CM = ±. 9 CM = ±. 9 Minimum Supply oltage Guaranteed by PSRR ±. PSRR Power Supply Rejection Ratio S = ±. to 9 A OL Large-Signal oltage Gain OUT = ±., R L = k OUT = ±., R L = k OUT = ±., R L = k OUT = ±., R L = k OUT Maximum Output Swing R L = k, m Overdrive R L = k, m Overdrive R L = k, m Overdrive R L = k, m Overdrive I OUT Maximum Output Current OUT = ±., m Overdrive OUT = ±., m Overdrive.. ±.9 ±.7 ±.9 ±.7 ±. ±. I SC Output Short-Circuit Current OUT =,. Overdrive (Note ) ±7 SR Slew Rate R L = k (Note ) GBW Gain Bandwidth Product f = khz, R L = k Channel Separation OUT = ±., R L = k OUT = ±., R L = k I S Supply Current Per Amplifi er Δ OS Input Offset oltage Match ΔI B Inverting Input Bias Current Match to 8 na ΔI B + Noninverting Input Bias Current Match to 8 na ΔCMRR Common Mode Rejection Match CM = ±. (Note 9) CM = ±. (Note 9) ΔPSRR Power Supply Rejection Match S = ±. to (Note 9) μ μ μ μ μ μ μ/ C μ/ C /m /m /m /m /μs /μs MHz MHz μ μ 9f

5 LT9- ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, C T A 8 C, CM = unless otherwise noted. (Note ) SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS OS Input Offset oltage S8 Package LT9A, DF Package LT9, DF Package Δ OS /ΔT Input Offset oltage Drift (Note 8) I OS Input Offset Current to ± na ΔI OS /ΔT Input Offset Current Drift (Note 8) to pa/ C I B Inverting Input Bias Current to ± na ΔI B /ΔT Inverting Input Bias Current Drift (Note 8) to 8 pa/ C I B + Noninverting Input Bias Current to ±8 na CM Input oltage Range (Positive) Guaranteed by CMRR Input oltage Range (Negative) Guaranteed by CMRR CMRR Common Mode Rejection Ratio CM = ±. CM = ± ±. Minimum Supply oltage Guaranteed by PSRR PSRR Power Supply Rejection Ratio S = ±. to 9 A OL Large-Signal oltage Gain OUT = ±,, R L = k OUT = ±., R L = k OUT = ±., R L = k OUT = ±., R L = k OUT Maximum Output Swing R L = k, m Overdrive R L = k, m Overdrive R L = k, m Overdrive R L = k, m Overdrive I OUT Maximum Output Current OUT = ±., m Overdrive OUT = ±., m Overdrive ±.8 ±. ±.8 ±. ±7 ±7 I SC Output Short-Circuit Current OUT =,. Overdrive (Note ) ± SR Slew Rate R L = k (Note ) GBW Gain Bandwidth Product f = khz, R L = k Channel Separation OUT = ±., R L = k OUT = ±., R L = k I S Supply Current Per Amplifi er Δ OS Input Offset oltage Match ΔI B Inverting Input Bias Current Match to 78 na ΔI B + Noninverting Input Bias Current to 8 na Match ΔCMRR Common Mode Rejection Match CM = ±. (Note 9) CM = ±. (Note 9) ΔPSRR Power Supply Rejection Match S = ±. to (Note 9) μ μ μ μ μ μ μ/ C μ/ C /m /m /m /m /μs /μs MHz MHz μ μ 9f

6 LT9- ELECTRICAL CHARACTERISTICS Note : Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note : The inputs are protected by back-to-back diodes and two Ω series resistors. If the differential input voltage exceeds.7, the input current should be limited to less than. Input voltages outside the supplies will be clamped by ESD protection devices and input currents should also be limited to less than. Note : A heat sink may be required to keep the junction temperature below absolute maximum when the output is shorted indefi nitely. Note : The LT9C- and LT9I- are guaranteed functional over the operating temperature range of C to 8 C. Note : The LT9C- is guaranteed to meet specifi ed performance from C to 7 C and is designed, characterized and expected to meet specifi ed performance from C to 8 C but is not tested or QA sampled at these temperatures. The LT9I- is guaranteed to meet specifi ed performance from C to 8 C. Note : Slew rate is measured between ±8 on the output with ± swing for supplies and ± on the output with ± swing for supplies. Tested in A = Note 7: Full-power bandwidth is calculated from the slew rate. FPBW = SR/π P. Note 8: This parameter is not % tested. Note 9: ΔCMRR and ΔPSRR are defi ned as follows: ) CMRR and PSRR are measured in μ/ on each amplifi er; ) the difference between the two sides is calculated in μ/; ) the result is converted to. TYPICAL PERFORMANCE CHARACTERISTICS PERCENTAGE OF UNITS (%) Distribution of Input Offset oltage S = PERCENTAGE OF UNITS (%) Distribution of Inverting Input Bias Current S = SUPPLY CURRENT () Supply Current vs Supply oltage and Temperature 8 C C C INPUT OFFSET OLTAGE (μ) INERTING INPUT BIAS CURRENT (na) SUPPLY OLTAGE (±) 9 G 9 G 9 G INPUT OLTAGE NOISE (n/ Hz) Input Noise Spectral Density i n e n S = A = R S = k FOR i n. INPUT CURRENT NOISE (pa/ Hz) OLTAGE NOISE (n/di).hz to Hz oltage Noise S = TOTAL NOISE OLTAGE (n/ Hz) Total Noise vs Unmatched Source Resistance S = f = khz TOTAL NOISE R S + RESISTOR NOISE ONLY. k k k FREQUENCY (Hz) TIME (s/di) 9 G. k k k SOURCE RESISTANCE, R S (Ω) 9 G 9 G 9f

7 TYPICAL PERFORMANCE CHARACTERISTICS LT9- INPUT BIAS CURRENT (na) Input Bias Current vs Temperature S = I B I B + 7 TEMPERATURE ( C) INPUT BIAS CURRENT (na) 8 8 Input Bias Current vs Input Common Mode oltage S = I B I B + INPUT COMMON MODE OLTAGE () COMMON MODE RANGE () Input Common Mode Range vs Supply oltage Δ OS < μ 9 SUPPLY OLTAGE (±) 8 9 G7 9 G8 9 G9 OUTPUT OLTAGE SWING () + Output oltage Swing vs Supply oltage R L = k R L = k R L = k R L = k SUPPLY OLTAGE (±) +. OUTPUT OLTAGE SWING () Output oltage Swing vs Load Current S = C 8 C C C 8 C C OUTPUT CURRENT () OUTPUT SHORT-CIRCUIT CURRENT () Output Short-Circuit Current vs Temperature S = IN = ±. SOURCE SINK 7 TEMPERATURE ( C) 9 G 9 G 9 G OPEN-LOOP GAIN () Open-Loop Gain vs Resistive Load S = S = k k LOAD RESISTANCE (Ω) 9 G OPEN-LOOP GAIN () 9 Open-Loop Gain vs Temperature R L = k S = S = 7 TEMPERATURE ( C) 9 G OFFSET OLTAGE DRIFT (μ) 7 8 Warm-Up Drift vs Time S-8 S-8 8 TIME AFTER POWER UP (s) 9 G 9f 7

8 LT9- TYPICAL PERFORMANCE CHARACTERISTICS GAIN () 7 Open-Loop Gain and Phase vs Frequency Gain vs Frequency, A = GAIN PHASE A = R F = R G =.k C F = pf R L = k k k M M M FREQUENCY (Hz) 9 G 8 PHASE (DEG) GAIN () A = C L = pf R F = R G = k C F =.8pF C L = 7pF R L = Ω C L = pf NO C L k M M M FREQUENCY (Hz) 9 G7 OUTPUT IMPEDANCE (Ω).. Output Impedance vs Frequency S = A = A = A =. k k M M M FREQUENCY (Hz) 9 G8 OUTPUT OLTAGE SWING ( P-P ) Undistorted Output Swing vs Frequency, S = A = S = R L = k THD<% FREQUENCY (khz) 9 G9 OUTPUT OLTAGE SWING ( P-P ) Undistorted Output Swing vs Frequency, S = A = S = R L = k THD<% FREQUENCY (khz) 9 G OUTPUT STEP () 8 Settling Time vs Output Step, A = S = μ R F = R G =.k R L =.k.% INTO DIODES C F = 8pF.%.% 8 μ.% SETTLING TIME (ns) 9 G OUTPUT STEP () 8 Settling Time vs Output Step, A =.% S =.% R F = R G = k R L =.k INTO DIODES 8 C F = pf R S = Ω//pF SETTLING TIME (ns) 9 G m/di Small-Signal Transient, A = Large-Signal Transient, A = ns/di S = 9 G /DI ns/di S = A = R F = R G = k C L = pf 9 G 8 9f

9 LT9- APPLICATIONS INFORMATION Gain of Stable The LT9- is a decompensated version of the LT9. The DC precision performance is identical, but the internal compensation capacitors have been reduced to a point where the op amp needs a gain of or greater in order to be stable. In general, for applications where the gain around the op amp is, the decompensated version should be used, because it will give the best AC performance. In applications where the gain is <, the unity-gain stable version should be used. The appropriate way to define the gain is as the inverse of the feedback ratio from output to differential input, including all relevant parasitics. Moreover, as with all feedback loops, the stability of the loop depends on the value of that feedback ratio at frequencies where the total loop-gain would cross unity. Therefore, it is possible to have circuits in which the gain at DC is lower than the gain at high frequency, and these circuits can be stable even with a non unity-gain stable op amp. An example is many current-output DAC buffer applications. Layout and Passive Components The LT9 requires attention to detail in board layout in order to maximize DC and AC performance. For best AC results (for example, fast settling time) use a ground plane, short lead lengths and RF quality bypass capacitors (.μf to.μf) in parallel with low ESR bypass capacitors (μf to μf tantalum). For best DC performance, use star grounding techniques, equalize input trace lengths and minimize leakage (e.g.,.gω of leakage between an input and a supply will generate na equal to the maximum I B specification). Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close to that of the inputs: for inverting configurations tie the ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will increase which may require a compensating capacitor as discussed below). Microvolt level error voltages can also be generated in the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the contacts to the inputs can exceed the inherent drift of the amplifier. Air currents over device leads should be minimized, package leads should be short and the two input leads should be as close together as possible and maintained at the same temperature. The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause peaking or even oscillations. A feedback capacitor of value C F = R G C IN /R F may be used to cancel the input pole and optimize dynamic performance. For applications where the DC noise gain is one, and a large feedback resistor is used, C F should be less than or equal to one half of C IN. An example would be a DAC I-to- converter as shown on the front page of the data sheet where the DAC can have many tens of picofarads of output capacitance. + C F +IN R Ω Q Q R Ω IN R G R F IN C IN / LT9- + OUT 9 F 9 F Figure. Nulling Input Capacitance Figure. Input Stage Protection 9f 9

10 LT9- APPLICATIONS INFORMATION Input Considerations Each input of the LT9 is protected with a Ω series resistor and back-to-back diodes across the bases of the input devices. If large differential input voltages are anticipated, limit the input current to less than with an external series resistor. Each input also has two ESD clamp diodes one to each supply. If an input is driven beyond the supply, limit the current with an external resistor to less than. The LT9 employs bias current cancellation at the inputs. The inverting input current is trimmed at zero common mode voltage to minimize errors in inverting applications such as I-to- converters. The noninverting input current is not trimmed and has a wider variation and therefore a larger maximum value. As the input offset current can be greater than either input current, the use of balanced source resistance is NOT recommended as it actually degrades DC accuracy and also increases noise. The input bias currents vary with common mode voltage. The cancellation circuitry was not designed to track this common mode voltage because the settling time would have been adversely affected. The LT9 inputs can be driven to the negative supply and to within. of the positive supply without phase reversal. As the input moves closer than. to the positive supply, the output reverses phase. Total Input Noise The total input noise of the LT9 is optimized for a source resistance between k and k. Within this range, the total input noise is dominated by the noise of the source resistance itself. When the source resistance is below k, voltage noise of the amplifier dominates. When the source resistance is above k, the input noise current is the dominant contributor. SIMPLIFIED SCHEMATIC + I I I Q8 Q9 Q OUT +IN Q Q IN Q Q Q7 Q Q Q BIAS C I I I 9 SS 9f

11 PACKAGE DESCRIPTION S8 Package 8-Lead Plastic Small Outline (Narrow.) (Reference LTC DWG # -8-) LT9-. BSC. ± (.8.) NOTE 8 7. MIN. ±..8. (.79.97)..7 (.8.988) NOTE. ±. TYP RECOMMENDED SOLDER PAD LAYOUT.8. (..).. (..8) 8 TYP..9 (..7).. (..)....9 (..7) (..8) NOTE: INCHES TYP. DIMENSIONS IN (MILLIMETERS). DRAWING NOT TO SCALE. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED." (.mm). (.7) BSC SO8 DF Package -Lead Plastic DFN (mm mm) (Reference LTC DWG # Rev Ø). REF. ±. ( SIDES) 7. REF.7 ±.. ±.. ±.. ±..8 ±.. ±..8 ±.. ±.. ±.. BSC PACKAGE OUTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED. REF PIN TOP MARK (NOTE ).7 ±. R =. TYP BOTTOM IEW EXPOSED PAD. ±.. BSC PIN NOTCH R =. TYP OR. CHAMFER (DF) DFN 8 RE Ø.. NOTE:. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO- ARIATION (WGGD-X) TO BE APPROED. DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A REFERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 9f

12 LT9- RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT7 Precision Instrumentation Amplifi er Single Resistor Gain Set,.% Max Gain Error, ppm Max Gain Nonlinearity LT8 Single 9MHz, /μs, -Bit Accurate Op Amp 7μ Max OS, Single ersion of LT9 LTC9/LTC9 -Bit Serial Multiplying I OUT DAC ±LSB Max INL/DNL, Low Glitch, DAC8 -Bit Upgrade LTC97 -Bit Parallel Multiplying I OUT DAC ±LSB Max INL/DNL, Low Glitch, On-Chip Bipolar Resistors LTC -Bit, ksps Sampling ADC ±. Input, SINAD = 9, THD = LTC Single, -Bit, ksps Sampling ADC Low Power, ± Inputs, Parallel/Byte Interface LT 88 PRINTED IN USA Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9-77 (8) -9 FAX: (8) -7 LINEAR TECHNOLOGY CORPORATION 8 9f

LT MHz, 30V/µs 16-Bit Accurate A V 2 Op Amp. Description. Features. Applications. Typical Application

LT MHz, 30V/µs 16-Bit Accurate A V 2 Op Amp. Description. Features. Applications. Typical Application Features n Stable in Gain A (A = ) n MHz Gain Bandwidth Product n /μs Slew Rate n Settling Time: 8ns ( Step, ) n Specified at and Supplies n Low Distortion, 9.dB for khz, P-P n Maximum Input Offset oltage: