DESCRIPTIO APPLICATIO S TYPICAL APPLICATIO. LT MHz, 1000V/µs Gain Selectable Amplifier FEATURES

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1 LT MHz, /µs Gain Selectable Amplifier FEATURES Internal Gain Setting Resistors Pin Configurable as a Difference Amplifier, Inverting and Noninverting Amplifier Difference Amplifier: Gain Range to CMRR > db Noninverting Amplifier: Gain Range to Inverting Amplifier: Gain Range to Gain Error: <.% Slew Rate: /µs Bandwidth: MHz (Gain = ) Op Amp Input Offset oltage:.m Max Quiescent Current: ma Max Wide Supply Range: ±. to ± Available in -Lead MSOP and -Lead (mm mm) DFN Packages APPLICATIO S U Instrumentation Amplifier Current Sense Amplifier ideo Difference Amplifier Automatic Test Equipment DESCRIPTIO U The LT is a high speed, high slew rate, gain selectable amplifier with excellent DC performance. Gains from to with a gain accuracy of.% can be achieved using no external components. The device is particularly well suited for use as a difference amplifier, where the excellent resistor matching results in a typical common mode rejection ratio of db. The amplifier is a single gain stage design similar to the LT and features superb slewing and settling characteristics. Input offset of the internal operational amplifier is less than.m and the slew rate is /µs. The output can drive a Ω load to ±. on ± supplies, making it useful in cable driver applications. The resistors have excellent matching,.% maximum at room temperature and.% from C to C. The temperature coefficient of the resistors is typically ppm/ C. The resistors are extremely linear with voltage, resulting in a gain nonlinearity of ppm. The LT is fully specified at ±., ± and ± supplies and from C to C. The device is available in space saving -lead MSOP and -Lead (mm mm) DFN packages. For a micropower precision amplifier with precision resistors, see the LT and LT., LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATIO U High Slew Rate Differential Gain of M M M OUT k k Large-Signal Transient (G = ) k INPUT RANGE TO k k k LT k k P P P TAa TAb fb

2 LT ABSOLUTE MAXIMUM RATINGS W W W Total Supply oltage ( to )... Input Current (Note )... ±ma Output Short-Circuit Duration (Note )... Indefinite Operating Temperature Range (Note ).. C to C Specified Temperature Range (Note )... C to C U (Note ) Storage Temperature Range MS Package... C to C DD Package... C to C Maximum Junction Temperature MS Package... C DD Package... C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER INFORMATION P P P S TOP IEW M M M S OUT DD PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = C/W (NOTE ) EXPOSED PAD INTERNALLY CONNECTED TO S PCB CONNECTION OPTIONAL U W U ORDER PART NUMBER LTCDD LTIDD DD PART MARKING LBJF LBJF P P P S TOP IEW M M M S OUT MS PACKAGE -LEAD PLASTIC MSOP T JMAX = C, θ JA = C/W (NOTE ) ORDER PART NUMBER LTCMS LTIMS MS PART MARKING LTBJD LTBJD Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: Consult LTC Marketing for parts specified with wider operating temperature ranges. The temperature grades are identified by a label on the shipping container. ELECTRICAL CHARACTERISTICS Difference Amplifier Configuration. T A = C, = CM = and unused gain pins are unconnected, unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS GE Gain Error = ±, R L = k, G = ±.. % = ±, R L = k, G = ±.. % = ±, R L = k, G = ±.. % = ±, R L = Ω, G = ±.. % = ±., R L = Ω, G = ±.. % = ±., R L = Ω, G = ±.. % GNL Gain Nonlinearity = ±, R L = k, G = ± ppm OS Input Offset oltage G = (MS) ± m Referred to Input (Note ) G = (DD) ±. m G = (MS) ±. m G = (DD) ±.. m G = (MS) ±.. m G = (DD) ±.. m G = (MS) ± m G = (DD) ±. m G = (MS) ±. m G = (DD) ±.. m fb

3 ELECTRICAL CHARACTERISTICS Difference Amplifier Configuration. T A = C, = CM = and unused gain pins are unconnected, unless otherwise noted. LT SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS OS_OA Op Amp Input Offset oltage G = (MS) ±., ±, ±.. m (Note ) G = (DD) ±., ±, ±.. m e n Input Noise oltage G =, f = khz ±. to ± n/ Hz G =, f = khz ±. to ± n/ Hz G =, f = khz ±. to ± n/ Hz R IN Common Mode Input Resistance CM = ±, G = ± kω C IN Input Capacitance ±. pf Input oltage Range G = ± ± ±. ± ± ±. ±. ± ±. CMRR Common Mode Rejection Ratio G =, CM = ± ± db Referred to Input G =, CM = ± ± db G =, CM = ± ± db G =, CM = ± ± db G =, CM = ± ±. db PSRR Power Supply Rejection Ratio P = M =, G =, S = ±. to ± db Output oltage Swing R L = k ± ±. ± R L = Ω ± ± ±. R L = Ω ± ±. ± R L = Ω ±. ±. ± I SC Short-Circuit Current G = ± ± ± ma SR Slew Rate G =, = ±, P = ± /µs Measured at = ± G =, = ±., P = ± /µs Measured at = ± FPBW Full Power Bandwidth Peak, G = (Note ) ± MHz Peak, G = (Note ) ± MHz HD Total Harmonic Distortion G =, f = MHz, R L = k, = P-P ± db db Bandwidth G = ± MHz ± MHz ±. MHz t r, t f Rise Time, Fall Time % to %,., G = ± ns ± ns OS Overshoot., G =, C L = pf ± % ± % t pd Propagation Delay % to %,., G = ± ns ± ns t s Settling Time Step,.%, G = ± ns Step,.%, G = ± ns G Differential Gain G =, R L = Ω ±. % θ Differential Phase G =, R L = Ω ±. Deg R OUT Output Resistance f = MHz, G = ±. Ω I S Supply Current G = ±.. ma ±.. ma fb

4 LT ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the C T A C. Difference Amplifier Configuration. = CM = and unused gain pins are unconnected, unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS GE Gain Error = ±, R L = k, G = ±.. % = ±, R L = k, G = ±.. % = ±, R L = k, G = ±.. % = ±., R L = Ω, G = ±.. % = ±., R L = Ω, G = ±.. % OS Input Offset oltage G = (MS) ±.. m Referred to Input (Note ) G = (DD) ±.. m G = (MS) ±.. m G = (DD) ±. m G = (MS) ±. m G = (DD) ±.. m G = (MS) ±. m G = (DD) ±.. m G = (MS) ±.. m G = (DD) ±... m OS TC Input Offset oltage Drift G = (MS) ± µ/ C Referred to Input (Note ) G = (DD) ± µ/ C OS_OA Op Amp Input Offset oltage G = (MS) ±., ±, ±.. m (Note ) G = (DD) ±., ±, ±.. m Input oltage Range G = ± ± ±. ± ± ±. ±. ± ±. CMRR Common Mode Rejection Ratio CM = ±, G = ± db Referred to Input CM = ±, G = ± db CM = ±, G = ± db CM = ±, G = ± db CM = ±, G = ±. db PSRR Power Supply Rejection Ratio P = M =, G =, S = ±. to ± db Output oltage Swing R L = k ± ±. ± R L = Ω ± ±. ±. R L = Ω ± ±. ± R L = Ω ±. ±. ± I SC Short-Circuit Current G = ± ± ± ma SR Slew Rate G =, = ±, P = ± /µs Measured at = ± I S Supply Current G = ±.. ma ±.. ma The denotes the specifications which apply over the C T A C. Difference Amplifier Configuration. = CM = and unused gain pins are unconnected, unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS GE Gain Error = ±, R L = k, G = ±.. % = ±, R L = k, G = ±.. % = ±, R L = k, G = ±.. % = ±., R L = Ω, G = ±.. % = ±. R L = Ω, G = ±.. % fb

5 LT ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the C T A C. Difference Amplifier Configuration. = CM = and unused gain pins are unconnected, unless otherwise noted. SYMBOL PARAMETER CONDITIONS SUPPLY MIN TYP MAX UNITS OS Input Offset oltage G = (MS) ±.. m Referred to Input (Note ) G = (DD) ±. m G = (MS) ±. m G = (DD) ±. m G = (MS) ±.. m G = (DD) ±.. m G = (MS) ±.. m G = (DD) ±. m G = (MS) ±... m G = (DD) ±.. m OS TC Input Offset oltage Drift G = (MS) ± µ/ C Referred to Input (Note ) G = (DD) ± µ/ C OS_OA Op Amp Input Offset oltage G = (MS) ±., ±, ±.. m (Note ) G = (DD) ±., ±, ±.. m Input oltage Range G = ± ± ±. ± ± ±. ±. ± ±. CMRR Common Mode Rejection Ratio CM = ±, G = ± db Referred to Input CM = ±, G = ± db CM = ±, G = ± db CM = ±, G = ± db CM = ±, G = ±. db PSRR Power Supply Rejection Ratio P = M =, G =, S = ±. to ± db Output oltage Swing R L = k ± ± ± R L = Ω ± ±. ±. R L = Ω ± ±. ± R L = Ω ±. ±. ± I SC Short-Circuit Current G = ± ± ± ma SR Slew Rate G =, = ±, P = ± /µs Measured at = ± I S Supply Current G = ±.. ma ±.. ma Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : The inputs are protected by diodes connected to S and S. If an input goes beyond the supply range, the input current should be limited to ma. Note : A heat sink may be required to keep the junction temperature below absolute maximum. Note : The LTC and LTI are guaranteed functional over the operating temperature range of C to C. Note : The LTC is guaranteed to meet specified performance from C to C. The LTC is designed, characterized and expected to meet specified performance from C to C but is not tested or QA sampled at these temperatures. The LTI is guaranteed to meet specified performance from C to C. Note : Thermal resistance (θ JA ) varies with the amount of PC board metal connected to the leads. The specified values are for short traces connected to the leads. If desired, the thermal resistance can be reduced slightly in the MS package to about C/W by connecting the used leads to a larger metal area. A substantial reduction in thermal resistance down to about C/W can be achieved by connecting the Exposed Pad on the bottom of the DD package to a large PC board metal area which is either open-circuited or connected to S. Note : Input offset voltage is pulse tested and is exclusive of warm-up drift. OS and OS TC refer to the input offset of the difference amplifier configuration. The equivalent input offset of the internal op amp can be calculated from OS_OA = OS G/(G ). Note : Full Power bandwidth is calculated from the slew rate measurement: FPBW = SR/π P. Note : This parameter is not % tested. Note : The input offset of the internal op amp is calculated from the input offset voltage: OS_OA = OS G/(G ). fb

6 LT TYPICAL PERFOR A CE CHARACTERISTICS UW (Difference Amplifier Configuration) NUMBER OF UNITS (%) OS Distribution S = ± CM = G = MS PACKAGE SUPPLY CURRENT (ma) Supply Current vs Supply oltage and Temperature T A = C T A = C T A = C INPUT OLTAGE NOISE (n/ Hz) Input Noise Spectral Density S = ± T A = C G = G = G = G = INPUT OFFSET OLTAGE (m) SUPPLY OLTAGE (±).. FREQUENCY (khz) G G G CHANGE IN GAIN ERROR (%) Change in Gain Error vs Resistive Load G = G = G = G = S = ± T A = C = ± RESISTIE LOAD (kω) G OUTPUT OLTAGE ()... Output oltage Swing vs Supply oltage T A = C R L = Ω R L = k R L = Ω R L = k SUPPLY OLTAGE (±) G... OUTPUT OLTAGE () Output oltage Swing vs Load Current S = ± C C C C OUTPUT CURRENT (ma) C C G.... CHANGE IN INPUT OFFSET OLTAGE (µ) Warm-Up Drift vs Time S = ± T A = C MS PACKAGE G = G = TIME AFTER POWER ON (MINUTES) G OUTPUT SHORT-CIRCUIT CURRENT (ma) Output Short-Circuit Current vs Temperature S = ± TEMPERATURE ( C) SINK SOURCE G OUTPUT IMPEDACNE (Ω) Output Impedance vs Frequency S = ± T A = C G = G =. k k M M M FREQUENCY (Hz) G fb

7 LT TYPICAL PERFOR A CE CHARACTERISTICS UW (Difference Amplifier Configuration) GAIN (db) Gain vs Frequency G = G = G = G = S = ± T A = C R L = k k k M M M FREQUENCY (Hz) G OUTPUT STEP () Settling Time vs Output Step (Non-Inverting) S = ± T A = C R L = k G = m m m m SETTLING TIME (ns) G OUTPUT STEP () Settling Time vs Output Step (Inverting) S = ± T A = C R L = k G = m m m m SETTLING TIME (ns) G SETTLING TIME (ns) Settling Time vs Gain (Non-Inverting) S = ± T A = C = R L = k.% SETTLING GAIN (/) db BANDWIDTH (MHz) db Bandwidth and Overshoot vs Supply oltage T A = C G = db BANDWIDTH OERSHOOT C L = pf SUPPLY OLTAGE (±) OERSHOOT (%) db BANDWIDTH (MHz) db Bandwidth and Overshoot vs Temperature S = ± db BANDWIDTH S = ± G = OERSHOOT C L = pf S = ± S = ± TEMPERATURE ( C) OERSHOOT (%) G G G GAIN (db) Frequency Response vs Supply oltage (G =, G = ) TA = C R L = k k ±. ± ± M M M FREQUENCY (Hz) G OLTAGE MAGNITUDE (db) Frequency Response vs Capacitive Load S = ± T A = C R L = G = C = pf C = pf C = pf C = pf FREQUENCY (MHz) G COMMON MODE REJECTION RATIO (db) Common Mode Rejection Ratio vs Frequency k S = ± T A = C G = k k M M M FREQUENCY (Hz) G fb

8 LT TYPICAL PERFOR A CE CHARACTERISTICS UW (Difference Amplifier Configuration) POWER SUPPLY REJECTION RATIO (db) Power Supply Rejection Ratio vs Frequency PSRR PSRR S = ± T A = C G = SLEW RATE (/µs) Slew Rate vs Supply oltage T A = C G = = S S P-P SLEW RATE (/µs) Slew Rate vs Temperature S = ± = P-P S = ± = P-P G = k k k M M M FREQUENCY (Hz) SUPPLY OLTAGE (±) TEMPERATURE ( C) G G G SLEW RATE (/µs) Slew Rate vs Input Level T A = C S = ± G = INPUT LEEL ( P-P ) G TOTAL HARMONIC DISTORTION (%).... Total Harmonic Distortion vs Frequency T A = C o = RMS R L = Ω G = G =. FREQUENCY (khz) G OUTPUT OLTAGE ( P-P ) Undistorted Output Swing vs Frequency (±) G = G = S = ± T A = C HD <%. FREQUENCY (MHz) G OUTPUT OLTAGE ( P-P ) Undistorted Output Swing vs Frequency (±) S = ± T A = C HD <% G = G =. FREQUENCY (MHz) G DISTORTION (dbc). nd and rd Harmonic Distortion vs Frequency S = ± = P-P R L = Ω G = ND HARMONIC RD HARMONIC FREQUENCY (MHz) G DIFFERENTIAL PHASE (DEG)..... Differential Gain and Phase vs Supply oltage DIFFERENTIAL GAIN DIFFERENTIAL PHASE SUPPLY OLTAGE () T A = C R L = Ω G = G..... DIFFERENTIAL GAIN (%) fb

9 LT TYPICAL PERFOR A CE CHARACTERISTICS UW (Difference Amplifier Configuration) OERSHOOT (%) Capacitive Load Handling S = ± T A = C G = R L = G = G = G = pf pf pf.µf.µf µf CAPACITIE LOAD G OERSHOOT (%) Capacitive Load Handling pf S = ± T A = C R L = G = G = G = pf pf.µf.µf µf CAPACITIE LOAD G = G Small-Signal Transient (G = ) Small-Signal Transient (G = ) Small-Signal Transient (Noninverting, G =, C L = pf) S = ± ns/di G R L = k S = ± ns/di G R L = k S = ± ns/di G R L = k Large-Signal Transient (G = ) Large-Signal Transient (G = ) Large-Signal Transient (Noninverting, G =, C L = pf) S = ± ns/di G R L = k S = ± ns/di G R L = k S = ± ns/di G R L = k fb

10 LT PI FU CTIO S U U U (Difference Amplifier Configuration) P (Pin ): Noninverting Gain-of- Input. Connects a k internal resistor to the op amp s noninverting input. P (Pin ): Noninverting Gain-of- Input. Connects a k internal resistor to the op amp s noninverting input. P (Pin ): Noninverting Gain-of- Input. Connects a k internal resistor to the op amp s noninverting input. S (Pin ): Negative Supply oltage. (Pin ): Reference oltage. Sets the output level when the difference between the inputs is zero. Connects a k internal resistor to the op amp s non inverting input. OUT (Pin ): Output oltage. = ( P M ) ( P M ) ( P M ). S (Pin ): Positive Supply oltage. M (Pin ): Inverting Gain-of- Input. Connects a k internal resistor to the op amp s inverting input. M (Pin ): Inverting Gain-of- Input. Connects a k internal resistor to the op amp s inverting input. M (Pin ): Inverting Gain-of- Input. Connects a k internal resistor to the op amp s inverting input. fb

11 LT BLOCK DIAGRA W S P R P = k.pf R FB = k.pf P R P = k P R P = k M R M = k M R M = k.pf.pf M R M = k R FB = k OUT S BD APPLICATIO S I FOR ATIO Configuration Flexibility U W U U The LT combines a high speed precision operational amplifier with eight ratio-matched on-chip resistors. The resistor configuration and pinout of the device is shown in the Block Diagram. The topology is extremely versatile and provides for simple realizations of most classic functional configurations including difference amplifiers, inverting gain stages, noninverting gain stages (including Hi-Z input buffers) and summing amplifiers. The LT delivers load currents of at least ma, making it ideal for cable driving applications as well. The input voltage range depends on gain and configuration. ESD diodes will clamp any input voltage that exceeds the supply potentials by more than several tenths of a volt; and the internal op amp input ports must remain at least. within the rails to assure normal operation of the part. The output will swing to within one and a half volts of the rails, which in low supply voltage and high gain configurations will create a limitation on the usable input range. It should be noted that while the internal op amp can withstand transient differential input voltages of up to without damage, this does generate large supply current increases (tens of ma) as required for high slew rates. If the device is used with sustained differential input across the internal op amp (such as when the output is clipping), the average supply current will increase, excessive power dissipation will result, and the part may be damaged (i.e., the LT is not recommended for use in comparator applications or with the output clipped). Difference Amplifier The LT can be connected as a classic difference amplifier with an output function given by: = G ( ) fb

12 LT APPLICATIO S I FOR ATIO U W U U As shown in Figure, the options for fixed gain G include:,.,.,,,,, and, all achieved by pinstrapping alone. With split-supply applications where the output is to be ground referenced, the input is simply tied to ground. The input common mode voltage is rejected by the high CMRR of the part within the usable input range. Inverting Gain Amplifier The LT can be connected as an inverting gain amplifier with an output function given by: = (G IN ) As shown in Figure, the options for fixed gain G include:,.,.,,,,, and, all achieved by pin strapping alone. The IN connection used in the difference amp configuration is simply tied to ground (or a low impedance potential equal to the input signal bias to create an input virtual ground ). With split-supply applications where the output is to be ground referenced, the input is simply tied to ground as well. Noninverting Gain Buffer Amplifier The LT can be connected as a high input impedance noninverting gain buffer amplifier with an output function given by: = G As shown in Figure, the options for fixed gain G include:,.,.,.,.,.,,.,.,,,,, and, all achieved by pin strapping alone. With single supply applications, the grounded M input pins may be tied to a low impedance potential equal to the input signal bias to create a virtual ground for both the input and output signals. While there is no input attenuation from to the internal noninverting op amp port in these configurations, the P connections vary to minimize offset by providing balanced input resistances to the internal op amp. Noninverting Gain Amplifier Input Attenuation The LT can also be connected as a noninverting gain amplifier having an input attenuation network to provide a wide range of additional noninverting gain options. In combination with the feedback configurations for gains of G shown in Figure (connections to the M inputs), the P and inputs may be connected to form several resistor divider attenuation ratios A, so that a compound output function is given by: = A G As shown in Figure, the options for fixed attenuation A include.,.,.,.,.,.,.,. and., all achieved by pin strapping alone. With just the attenuation configurations of Figure and the feedback configurations of Figure, seventy-three unique composite gains in the range of to are available (many options for gain below unity also exist). Figure does not include the additional pin-strap configurations offering A values of.,.,.,.,.,.,.,.,. and., as these values tend to compromise the low noise performance of the part and don t generally contribute many more unique gain options. It should be noted that with these configurations some degree of imbalance will generally exist between the effective resistances R P and R M seen by the internal op amp input ports, noninverting and inverting, respectively. Depending on the specific combination of A and G, the following DC offset error due to op amp input bias current (I B ) should be anticipated: The I B of the internal op amp is typically.µa and is prepackage tested to a limit of µa. Additional output-referred offset = I B (R P R M ) G. In some configurations, this could be as much as.m G additional output offset. The I OS of the internal op amp is typically na and is prepackage tested to a limit of na. The Electrical Characteristics table includes the effects of I B and I OS. fb

13 LT APPLICATIO S I FOR ATIO U W U U M M M P P P LT G =. IN M M M LT P P P G =. IN M M M LT P P P G =. IN M M M P P P LT IN M M M P P P LT IN IN M M M P P P LT G =. G =. G =. IN M M M P P P LT IN M M M P P P LT IN M M M P P P LT F G =. G =. G =. Figure. Difference (and Inverting) Amplifier Configurations Table. Pin Use, Input Range, Input Resistance, Bandwidth in Difference Amplifier Configuration GAIN Use of P/M Open Open Open Use of P/M Open Open Open Use of P/M Open Open Open Positive Input Range: =, S = ± ± ± ± ± ± ± ± Positive Input Range: =, S = ± ± ±. ±. ±. ±. ±. ±. Positive Input Range: =, S = ±. ±. ±. ± ±. ±. ±. ±. Positive Input Resistance k k.k k.k.k.k Minus Input Resistance k k.k k Ω Ω Ω Ref Input Resistance k k.k k.k.k.k Input Common Mode Resistance, = k k.k.k.k.k.k Input Differential Mode Resistance, = k k.k k.k.k.k db Bandwidth MHz MHz MHz MHz MHz MHz MHz fb

14 LT APPLICATIO S I FOR ATIO U W U U M M M P P P LT M M M P P P LT M M M P P P LT G =. G =. G =. M M M P P P LT M M M P P P LT M M M P P P LT G =. G =. G =. F M M M P P P LT M M M P P P LT M M M P P P LT G =. G =. G =. M M M P P P LT M M M P P P LT M M M P P P LT G =. G =. G =. M M M P P P LT M M M P P P LT M M M P P P LT G =. G =. G =. Fb Figure. Noninverting Buffer Amplifier Configurations (Hi-Z Input) fb

15 LT APPLICATIO S I FOR ATIO U W U U M M M P P P LT M M M P P P LT M M M P P P LT A =. A =. A =. M M M P P P LT M M M P P P LT M M M P P P LT A =. A =. A =. M M M P P P LT M M M P P P LT M M M P P P LT F A =. A =. A =. CONFIGURE M INPUTS FOR DESIRED G PARAMETER; ER TO FIGURE FOR CONNECTIONS Figure. Noninverting Amplifier Input Attenuation Configurations (A >.) AC-Coupling Methods for Single Supply Operation The LT can be used in many single-supply applications using AC-coupling without additional biasing circuitry. AC-coupling the LT in a difference amplifier configuration (as in Figure ) is a simple matter of adding coupling capacitors to each input and the output as shown in the example of Figure. The input voltage BIAS applied to the pin establishes the quiescent voltage on the input and output pins. The BIAS signal should have a low source impedance to avoid degrading the CMRR (.Ω for db CMRR change typically). NONINERTING GAIN GAIN COMBINATION F Figure. Unique Noninverting Gain Configurations fb

16 LT APPLICATIO S I FOR ATIO U W U U Using the LT as an AC-coupled inverting gain stage, the pin and the relevant P inputs may all be driven from a BIAS source as depicted in the example of Figure, thus establishing the quiescent voltage on the input and output pins. The BIAS signal will only have to source the bias current (I B ) of the noninverting input of the internal op amp (.µa typically), so a high BIAS source impedance (R S ) will cause the quiescent level of the amplifier output to deviate from the intended BIAS level by I B R S. In operation as a noninverting gain stage, the P and inputs may be configured as a supply splitter, thereby providing a convenient mid-supply operating point. Figure illustrates the three attenuation configurations that generate % mid-supply biasing levels with no external components aside from the desired coupling capacitors. As with the DC-coupled input attenuation ratios, A, a compound output function including the feedback gain parameter G is given by: = A G C IN C IN M M M P P P LT C OUT C IN M M M P P P LT C OUT BIAS F BIAS F Figure. AC-Coupled Difference Amplifier General Configuation (G = Example) Figure. AC-Coupled Inverting Gain Amplifier General Configuration (G = Example) C IN M M M P P P LT C OUT M M M P P P LT C OUT C IN M M M P P P LT C OUT C IN F A =. A =. CONFIGURE M INPUTS FOR DESIRED G PARAMETER; ER TO FIGURE FOR CONNECTIONS. ANY M INPUTS SHOWN GROUNDED IN FIGURE SHOULD INSTEAD BE CAPACITIELY COUPLED TO GROUND A =. Figure. AC-Coupled Noninverting Amplifier Input Attenuation Configurations (Supply Splitting) fb

17 LT APPLICATIO S I FOR ATIO U W U U If one of the A parameter configurations in Figure is preferred, or the use of an external biasing source is desired, the P and input connections shown grounded in a Figure circuit may be instead driven by a BIAS voltage to establish a quiescent operating point for the input and output pins. The connections of the Figure circuit are then driven via a coupling capacitor. Any grounded M inputs for the desired G configuration (refer to Figure ) must be individually or collectively AC-coupled to ground. Figure illustrates a complete example circuit of an externally biased AC-coupled noninverting amplifier. The BIAS source impedance should be low (a few ohms) to avoid degrading the inherent accuracy of the LT..% of additional Gain Error for each ohm of resistance on the pin is typical. BIAS C BYP C IN M M M P P P LT F C OUT CONFIGURATION EXAMPLE: A =. G =. ( / =.) Figure. AC-Coupled Noninverting Amplifier with External Bias Source (Example) Resistor Considerations The resistors in the LT are very well matched, low temperature coefficient thin film based elements. Although their absolute tolerance is fairly wide (typically ±% but ±% worst case), the resistor matching is to within.% at room temperature, and to within.% over temperature. The temperature coefficient of the resistors is typically ppm/ C. The resistors have been sized to accommodate across each resistor, or in terms of power, mw in the k resistors, mw in the k resistors, and mw in the k resistors. Power Supply Considerations As with any high speed amplifier, the LT printed circuit layout should utilize good power supply decoupling practices. Good decoupling will typically consist of one or more capacitors employing the shortest practical interconnection traces and direct vias to a ground plane. This practice minimizes inductance at the supply pins so the impedance is low at the operating frequencies of the part, thereby suppressing feedback or crosstalk artifacts that might otherwise lead to extended settling times, frequency response anomalies, or even oscillation. For high speed parts like the LT, nf ceramics are suitable close-in bypass capacitors, and if high currents are being delivered to a load, additional.µf capacitors in parallel can help minimize induced power supply transients. Because unused input pins are connected via resistors to the input of the op amp, excessive capacitances on these pins will degrade the rise time, slew rate, and step response of the output. Therefore, these pins should not be connected to large traces which would add capacitance when not in use. Since the LT has a wide operating supply voltage range, it is possible to place the part in situations of relatively high power dissipation that may cause excessive die temperatures to develop. Maximum junction temperature (T J ) is calculated from the ambient temperature (T A ) fb

18 LT APPLICATIO S I FOR ATIO U W U U and power dissipation (P D ) as follows for a nominal PCB layout: T J = T A (P D θ JA ) For example, in order to maintain a maximum junction temperature of C at C ambient in an MS package, the power must be limited to.w. It is important to note that when operating at ± supplies, the quiescent current alone will typically account for.w, so careful thermal management may be required if high load currents and high supply voltages are involved. By additional copper area contact to the supply pins or effective thermal coupling to extended ground plane(s), the thermal impedance can be reduced to C/W in the MS package. A substantial reduction in thermal impedance of the DD package down to about C/W can be achieved by connecting the Exposed Pad on the bottom of the package to a large PC board metal area which is either opencircuited or connected to S. Frequency Compensation The LT comfortably drives heavy resistive loads such as back-terminated cables and provides nicely damped responses for all gain configurations when doing so. Small capacitances are included in the on-chip resistor network to optimize bandwidth in the basic difference gain configurations of Figure. For the noninverting configurations of Figure, where the gain parameter G is or less, significant overshoot can occur when driving light loads. For these low gain cases, providing an RC output network as shown in Figure to create an artificial load at high frequency will assure good damping behavior. M M M P P P LT nf Ω CONFIGURATION EXAMPLE: G =. F Figure. Optional Frequency Compensation Network for ( G ) Figure. Step Response of Circuit in Figure fb

19 LT PACKAGE DESCRIPTIO U MS Package -Lead Plastic MSOP (Reference LTC DWG # --). ±. (. ±.). ±. (. ±.) (NOTE ). ±. (. ±.). (.) MIN.. (..) GAUGE PLANE. (.) DETAIL A TYP. ±. (. ±.). ±. (. ±.) (NOTE ). ±. (. ±.) TYP. (.) BSC RECOMMENDED SOLDER PAD LAYOUT. (.) DETAIL A. ±. (. ±.). (.) MAX. (.) SEATING NOTE: PLANE. DIMENSIONS IN MILLIMETER/(INCH). DRAWING NOT TO SCALE. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.mm (.") PER SIDE. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.mm (.") PER SIDE. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.mm (.") MAX.. (..) TYP. (.) BSC. ±. (. ±.) MSOP (MS). ±. DD Package -Lead Plastic DFN (mm mm) (Reference LTC DWG # --) R =. TYP. ±.. ±.. ±.. ±. ( SIDES). ±.. BSC. ±. ( SIDES) PACKAGE OUTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS PIN TOP MARK (SEE NOTE ).. ±. ( SIDES). ±.... ±. ( SIDES) (DD) DFN. ±.. BSC. ±. ( SIDES) BOTTOM IEW EXPOSED PAD NOTE:. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M- ARIATION OF (WEED-). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF ARIATION ASSIGNMENT. DRAWING NOT TO SCALE. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED. SHADED AREA IS ONLY A ERENCE FOR PIN LOCATION ON THE TOP AND BOTTOM OF PACKAGE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. fb

20 LT TYPICAL APPLICATIO S U High Input Impedance Precision Gain of Configuration Tracking Negative Reference M M M P P P LT I IN = na LT-. µf. M LT G = P. TA TA A to A Current Source Current Sense with Alarm TO R S.Ω M M P P IRF LT G = k LT nf Ω I.Ω P LT G = M k SENSE OUTPUT m/a LT- m k FLAG OUTPUT A LIMIT I OUT nf I OUT = R S TA TA Single Supply ideo Line Driver µf µf M M M P P P LT Ω µf k f db = MHz R L = Ω TA RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT MHz, /µs Op Amp ns Settling Time to.%, C LOAD Stable LT High oltage Difference Amplifier ± Common Mode oltage, Micropower, Pin Selectable G =, LT Precision Gain Selectable Amplifier Micropower, Precision, Pin Selectable G = to LTC Fully Differential Amplifier Differential Input and Output, Rail-to-Rail Output, I S =.ma, C LOAD Stable to,pf, Adjustable Common Mode oltage LTC-x Programmable Gain Amplifiers Gain Configurations, Rail-to-Rail Input and Output Linear Technology Corporation McCarthy Blvd., Milpitas, CA - () - FAX: () - fb LT/LT RE B PRINTED IN THE USA LINEAR TECHNOLOGY CORPORATION